JP3011450B2 - Vertical synchronization frequency discrimination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention is used for, for example, a television receiver capable of receiving a multi-system broadcast, a monitor receiver of a VTR (video tape recorder), and the like. And a suitable vertical synchronization frequency discrimination circuit.

(Prior Art) As is well known, for example, VTRs capable of recording and reproducing television signals of various systems such as PAL and SECAM and NTSC having a color subcarrier frequency of 4.43 or 3.58 MHz have been developed. In a monitor receiver used for such a VTR, a vertical synchronization frequency discrimination circuit for discriminating a difference in vertical synchronization frequency between television signals of each system is provided, and a reception mode is switched based on the discrimination output. ing.

FIG. 7 shows such a conventional vertical synchronization frequency discrimination circuit. That is, in the figure, reference numeral 11 denotes an input terminal, which is a vertical synchronization signal VSYNC separated from the television composite video signal.
Is supplied. This vertical synchronization signal VSYNC includes PAL
TV system with a vertical synchronization frequency of 50 Hz and one frame of 625 scanning lines (hereinafter 50/62)
5 system) or a color subcarrier frequency of 3.58 MHz
Like the NTSC system, the vertical synchronization frequency is 60 Hz and the number of scanning lines of one frame is 525 television systems (hereinafter 60/525).
Method).

The vertical synchronization signal V supplied to the input terminal 11
SYNC is supplied to the vertical down counter 12. The vertical down counter 12 counts down a clock CK supplied to the clock terminal 13 and having a frequency that is an integral multiple of the horizontal frequency. The vertical down counter 12 presets a predetermined value with a vertical synchronization signal VSYNC to provide a digital PLL (phase synchronization). Loop). That is, when the vertical down counter 12 is preset by the input vertical synchronizing signal VSYNC, the clock CK is down-counted from the preset value to a predetermined value M to generate a window signal W1. Further, the clock CK is counted down to a predetermined value S, and the output of the window signal W1 is stopped. It is assumed that the generation timing of the window signal W1 of the vertical down counter 12 is set so as to correspond to the 60 Hz vertical synchronization signal VSYNC.

When the vertical down counter 12 further counts down from the predetermined value S, that is, when the vertical synchronization signal VSYNC is not input and preset, the count value is output to the no-signal detection circuit 14. Stop counting operation. Then, this no-signal detection circuit 14
Is to output a reset signal R1 as a no-signal detection signal to the continuity detection counter 15 when a count value equal to or less than the predetermined value S is output from the vertical down counter 12.

Here, the window signal W1 output from the vertical down counter 12 is supplied to the coincidence detection circuit 16. When the vertical synchronizing signal VSYNC is input during the input period of the window signal W1, the coincidence detecting circuit 16 supplies the input vertical synchronizing signal VSYNC as it is to the continuity detection counter 15 as a counting pulse. The continuity detection counter 15 counts the vertical synchronization signal VSYNC output from the coincidence detection circuit 16 by a predetermined number (for example, three times), and determines at this time that the 60 Hz vertical synchronization signal VSYNC is being input. The signal is output to the output terminal 17. The continuity detection counter 15 is reset when the reset signal R1 is output from the no-signal detection circuit 14, and at this time, a determination signal indicating that the 50 Hz vertical synchronization signal VSYNC is being input is output to the output terminal 17. Output.

The above operation will be described in detail with reference to the timing charts shown in FIGS. FIG. 8 shows an operation when a 60 Hz vertical synchronization signal VSYNC arrives from a no-signal state. First, when the input is in the no-signal state, the H-level reset signal R1 indicating the no-signal state is output from the no-signal detection circuit 14, so that the continuity detection counter 15 is reset and the discrimination signal output therefrom is output. Is at the L level corresponding to the vertical synchronization signal VSYNC of 50 Hz. The window signal W1 is also at the L level.

In this state, when the vertical synchronizing signal VSYNC is input at the time T1, the vertical down counter 12 is preset and starts the counting operation. Therefore, the reset signal R1 output from the no-signal detection circuit 14 becomes L level. Then, the reset state of the continuity detection counter 15 is released. When the count value of the vertical down counter 12 becomes M, the vertical down counter 12 outputs an H level window signal W1,
During the generation period of this window signal W1, the next vertical synchronizing signal V
When SYNC is input, the vertical down counter 12 is preset and generation of the window signal W1 is stopped. Thereafter, the same operation is repeated, and when the input of the vertical synchronization signal VSYNC is repeated three times during the generation period of the window signal W1, the continuity detection counter 15 outputs the 60 Hz vertical synchronization signal VSY.
An H-level determination signal corresponding to NC is output.

Next, FIG. 9 shows an operation in a case where the signal is changed from a state where the vertical synchronization signal VSYNC of 60 Hz has arrived to a state where there is no signal. That is, while the vertical synchronization signal VSYNC is being input during the generation period of the window signal W1, the reset signal R1
Is at the L level, the continuity detection counter 15 is reset, and the H level discrimination signal corresponding to the 60 Hz vertical synchronization signal VSYNC is output. In this state, the vertical synchronization signal V
Assuming that SYNC is no longer input, the count value is set to S since the vertical preset counter 12 was last preset.
Since no preset operation is performed even when the following condition is satisfied, the no-signal detection circuit 14 generates a reset signal R1 at H level, and the continuity detection counter 15 is reset. Therefore, the discrimination signal output from the continuity detection counter 15 has an L level corresponding to the 50 Hz vertical synchronization signal VSYNC.

Therefore, according to the vertical synchronization frequency discriminating circuit configured as described above, when the vertical synchronization signal VSYNC of 60 Hz is being input, the vertical synchronization signal VSYNC is obtained during the generation period of the window signal W1. When the discrimination signal is at the H level and the 50 Hz vertical synchronization signal VSYNC is being input, the vertical synchronization signal VSYNC cannot be obtained during the generation period of the window signal W1, so the discrimination signal is at the L level. / 60 Hz vertical synchronization signal VSYNC can be determined.

However, in the above-described conventional vertical synchronization frequency determination circuit, if the vertical synchronization signal VSYNC is not input even once, for example, in the state where the vertical synchronization signal VSYNC of 60 Hz is input, it has been determined that the frequency is 60 Hz. in spite of,
Since the discrimination signal is inverted to the L level corresponding to 50 Hz, the input television signal is interrupted momentarily as in the case of a weak electric field or channel switching, or a 60 Hz television signal again after a small time from 60 Hz. There is a problem that the screen is disturbed when receiving an image.

(Problems to be Solved by the Invention) As described above, in the conventional vertical synchronization frequency determination circuit,
There is a problem that a malfunction occurs when the input television signal is interrupted for a moment.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an extremely good vertical synchronization frequency discriminating circuit which is resistant to input television signal dropout or noise and hardly malfunctions.

[Configuration of the Invention] (Means for solving the problem) A vertical synchronization frequency discriminating circuit according to the present invention comprises a first and a second vertical synchronization signals having periods different from each other and having a period corresponding to the first and second vertical synchronization signals. A window generating means for generating a window signal; and first and second detecting means for detecting a substantial coincidence between the first and second window signals generated by the window generating means and the input vertical synchronizing signal, respectively.
, A first and a second counting means for counting a predetermined number of coincidence detection outputs of the first and the second coincidence detecting means to generate outputs, and a first and a second counting means.
Output means which is set while one of the outputs of the counting means is supplied first, and whose setting state is inverted only when the other output is supplied in the setting state, and a detection means which detects that the vertical synchronization signal is not input. The signal detecting means and the first and second counting means are reset based on the output of the no-signal detecting means, and the second counting is performed by the output of the first counting means.
And control means for resetting the first counting means with the output of the second counting means.

(Operation) According to the above configuration, the first and second window signals are generated corresponding to the first and second vertical synchronization signals, respectively, and the first and second window signals are generated. First and second coincidence detecting means for detecting substantial coincidence with the input vertical synchronizing signal, and a predetermined number of coincidence detection outputs of the first and second coincidence detection means, respectively. There are provided two vertical synchronization frequency detection systems comprising first and second counting means for generating an output, and one of the outputs of the two vertical synchronization frequency detection systems is set while being supplied first, and the setting state And output means for inverting the setting state only when the other output is supplied,
Both vertical sync frequency detection systems are reset when there is no signal, and the output of one vertical sync frequency detection system is used to reset the other vertical sync frequency detection system. In the case where the input television signal is interrupted for a moment, the discrimination output is not interrupted, so that the input television signal is less liable to malfunction due to lack of input television signal and noise.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, reference numeral 18 denotes an input terminal, which is a vertical synchronizing signal VSY separated from a television composite video signal.
NC is supplied. This vertical synchronization signal VSYNC is output from a vertical synchronization separation circuit (not shown) in a synchronization circuit mounted on a television receiver, for example.
There are a 50/625 system such as the L and SECAM systems, and a 60/525 system such as the NTSC system having a color subcarrier frequency of 3.58 MHz.

The vertical synchronizing signal V supplied to the input terminal 18
SYNC is supplied to the vertical down counter 19. The vertical down counter 19 counts down the clock CK supplied to the clock terminal 20 and having a frequency that is an integral multiple of the horizontal frequency, and is preset to a predetermined value every time the vertical synchronization signal VSYNC is supplied. Then, the output count value of the vertical down counter 19 is supplied to the decoder circuit 21 and the narrow pulse VP having the cycle of the vertical synchronization signal VSYNC is supplied.
And a window signal W11 for 60/525 detection, a window signal W12 for 50/625 detection, and a vertical down counter 19
To generate a self-reset pulse RP.

Among them, the window signal W11 and the narrow pulse VP are supplied to the coincidence detection circuit 22. When the narrow pulse VP is input during the input period of the window signal W11, the coincidence detection circuit 22 supplies the input narrow pulse VP as it is to the continuity detection counter 23 as a pulse for counting.
The continuity detection counter 23
A predetermined number (for example, three times) of the narrow pulse VP output from the counter is counted, and at this time, a determination signal DATA1 indicating that a 60 Hz vertical synchronization signal VSYNC is being input is output.

The window signal W12 and the narrow pulse VP are supplied to the coincidence detection circuit 24. When the narrow pulse VP is input during the input period of the window signal W12, the coincidence detection circuit 24 supplies the input narrow pulse VP as it is to the continuity detection counter 25 as a pulse for counting. Then, the continuity detection counter 25 counts a predetermined number (for example, three) of the narrow pulse VP output from the coincidence detection circuit 24, and determines at this time that the 50 Hz vertical synchronization signal VSYNC is being input. Outputs signal DATA2.

Here, the discrimination signals DATA1 and DATA2 output from the continuity detection counters 23 and 25 are supplied to one input terminals of OR circuits 26 and 27, respectively. In addition, the above OR circuits 26, 2
7, the output of the no-signal detection circuit 28 for detecting that the vertical synchronizing signal VSYNC does not exist, that is, is in the no-signal state, based on the narrow pulse VP output from the decoder circuit 21. Supplied. And each OR circuit
Outputs of 26 and 27 are reset signals R12 and R11 of the continuity detection counters 25 and 23, respectively, in the form of crossing.

Therefore, when continuity is confirmed by one of the continuity detection counters 23, 25, the other continuity detection counters 25, 23 are reset. For example, if continuity is confirmed by the continuity detection counter 23 in the reception state of the 60/525 system, that is, if the determination signal DATA1 is obtained, the continuity detection counter 2 is output by the reset signal R12 output from the OR circuit 26.
By resetting 5, the function of the 50/625 detection system consisting of the coincidence detection circuit 24 and the continuity detection counter 25 is stopped, and the next continuity detection of the same system can be performed normally. The continuity detection counter 25 is initialized.

In the no-signal state, the reset signal R1 output from each of the OR circuits 26 and 27 based on the output of the no-signal detection circuit 28
Since 2, R11 is supplied to the bicontinuity detection counters 25,23,
Both continuity detection counters 23, 25 are reset and 60/52
The function of each detection system of the 5 system and the 50/625 system is stopped, and the continuity detection counters 23 and 25 are initialized so that the continuity detection of the same system can be normally performed next time.

On the other hand, the discrimination signals DATA1 and DATA2 output from the continuity detection counters 23 and 25 are supplied to different input terminals of the discrimination result holding memory 29, respectively. The determination result holding memory 29 outputs a signal determined by which input terminal is supplied with data to the output terminal 30. Once the signal determined by the data supplied to one input terminal is output, As long as data is not supplied to the other input terminal, the same signal output is continued even if data supply to the one input terminal is stopped.

For example, the discrimination signal output from the continuity detection counter 23
In a state where DATA1 is input once and a signal indicating the 60/525 system is output as the output of the determination result holding memory 29,
Even if the determination signal DATA1 cannot be obtained due to the no-signal state, the output of the determination result holding memory 29 continues to be a signal indicating the 60/525 system. Then, the determination result holding memory 29 outputs a signal indicating the 50/625 system only after the determination signal DATA2 is output from the continuity detection counter 25.

Here, the above-described window signals W11 and W12 are generated by processing the count value of the vertical down counter 19 by the decoder circuit 21 as described above. The clock CK for counting of the vertical down counter 19 is obtained by configuring a digital PLL circuit using a horizontal down counter (not shown). The oscillation frequency of the VCO (Voltage Controlled Oscillator) used in this digital PLL circuit is selected to be 32 times the horizontal frequency, and is divided to the horizontal frequency by a frequency divider with five stages of FF (flip-flop) circuits connected. I am trying to do it.

By the way, since the vertical synchronization signal VSYNC has a period of 262.5H and 312.5H, it is necessary to use the clock CK at a frequency twice or more the horizontal frequency. If the horizontal frequency is used, the phase of the clock CK is shifted from the phase of the vertical synchronization signal VSYNC for each field, resulting in a system that is extremely difficult to use. However,
As described above, since the horizontal down counter has a signal of the horizontal frequency × 2 to the power of n (1 ≦ n ≦ 5), a frequency suitable for the vertical down counter 19 system may be selected from these signals. Uses a double signal (2fH).

Then, the vertical down counter 19 divides the frequency of the clock CK having a frequency of 2fH, and resets the reset pulse RP for resetting the vertical down counter 19 based on the narrow pulse VP obtained from the input vertical synchronization signal VSYNC. By generating reset signals R11 and R12 for the continuity detection counters 23 and 25, a digital PLL is configured. By supplying the output count value of the vertical down counter 19 to the decoder circuit 21, the decoder circuit 21 can generate a signal that rises and falls at an arbitrary phase. For example, FIGS. 2 and 3 show timing diagrams in the case where the window signals W11 and W12 are respectively generated by the output count value (address) of the vertical down counter 19 described below.

Window signal W11 Address 488 to 576 (for 60 Hz detection) Window signal W12 Address 576 to 664 (for 50 Hz detection) Of these, FIG. 2 shows the operation in the 60/525 system, and the vertical synchronization signal VSYNC has arrived. Narrow pulse VP at time
Since the vertical down counter 19 is reset, that is, the address is set to 0, by the reset pulse RP generated from, the synchronization with the vertical synchronization signal VSYNC is achieved. This means that the window signal W11 does not exist, and the window signal W11 falls at the same time when the vertical down counter 19 is reset. FIG. 3 shows the operation in the 50/625 system. When the narrow pulse VP arrives, the vertical down counter
In addition to resetting 19, the window signal W12 falls.

Next, FIG. 4 shows a specific example of the coincidence detection circuits 22, 24, the continuity detection counters 23, 25, and the determination result holding memory 29. That is, 31 and 32 in the figure are input terminals to which the window signals W11 and W12 are supplied, respectively, and 33 in the figure is an input terminal to which the narrow pulse VP is supplied. Then, the window signal W11 supplied to the input terminal 31 and the narrow pulse VP supplied to the input terminal 33 are input to an AND circuit 22a constituting the coincidence detection circuit 22. Further, the window signal W12 supplied to the input terminal 32 and the narrow pulse VP supplied to the input terminal 33 are connected to an AND circuit 24a constituting the coincidence detection circuit 24.
Is input to

The output of the AND circuit 22a is a two-stage toggle FF (flip-flop) circuit 23a, 23b and an AND circuit 2a.
It is supplied to a continuity detection counter 23 composed of 3c. The output of the AND circuit 24a is supplied to a continuity detection counter 25 including two-stage toggle FF circuits 25a and 25b and an AND circuit 25c. The discrimination signals DATA1 and DATA2 output from the continuity detection counters 23 and 25 are supplied to one input terminals of the OR circuits 26 and 27, respectively, and the S-signals constituting the discrimination result holding memory 29 are provided. It is supplied to a set input terminal S and a reset input terminal R of an R (set-reset) FF circuit 29a. The output terminal Q of the S-RFF circuit 29a is connected to the output terminal 30. In FIG. 4, reference numeral 34 denotes an input terminal to which a no-signal detection signal output from the no-signal detection circuit 28 is supplied, and is connected to the other input terminals of the OR circuits 26 and 27, respectively.

FIGS. 5 and 6 are timing charts for explaining the operation of the circuit shown in FIG. 4, respectively. this house,
FIG. 5 shows the operation when the vertical synchronizing signal VSYNC, that is, the narrow pulse VP is missing in a state where the 60/525 system is detected from the no-signal state. That is, the vertical down counter 19 starts counting down only after the first narrow pulse VP arrives from the no-signal state, and the second narrow pulse VP
A little before the window signal W11 or W12 is generated. In FIG. 5, it is assumed that the window signal W11 is set to be generated. Then
When the window signal W11 and the narrow pulse VP are supplied to the AND circuit 22a, the coincidence between them is detected. If they match, a pulse equivalent to the narrow pulse VP is output from the AND circuit 22a.

The output of the AND circuit 22a is
Supplied to In the no-signal state, since the no-signal detection signal is at the H level, the output DATA1 of the continuity detection counter 23 is at the L level because both the FF circuits 23a and 23b constituting the continuity detection counter 23 have been reset. It has become. In such a state, the window signal W11 and the narrow pulse V
When P matches three times in succession, the continuity detection counter 2
The output DATA1 of 3 goes high. Then, S-RFF circuit 2
In 9a, since the set input terminal S is at the H level, an H level signal indicating the 60/525 system is generated from the output terminal Q.

Here, it is assumed that the sixth narrow pulse VP in FIG. 5 is missing. Then, since the vertical down counter 19 is not reset near the address 525, a window signal W11 is generated between addresses 488 to 576, and the addresses 576 to 66 are generated.
The window signal W12 is generated between the four. If the narrow pulse VP is not obtained for a certain period, the no-signal detection signal goes high as described above, so that the continuity detection counters 23 and 25 are reset at that point, and both outputs DATA1 and DATA2 are reset. , DATA2 are both at the L level. That is, since both the set input terminal S and the reset input terminal R of the S-RFF circuit 29a are at the L level, the output terminal Q holds the previous state (H level) and the discrimination signal of the 60/525 system continues. Is done.

It should be noted that even when the narrow pulse VP is missing during the discrimination of the 50/625 system, the discrimination signal is maintained by the same operation as described above.

Next, FIG. 6 shows an operation when noise is mixed in the narrow pulse VP. In this case, as shown in FIG. 4, the continuity detection counter 25 is reset by the output DATA1 of the continuity detection counter 23, and the continuity detection counter 23 is reset by the output DATA2 of the continuity detection counter 25. If it is configured not to take the form of crossing,
As shown in the timing chart of FIG. 7A, an error may occur in the determination result when the 50/625 system is determined.

That is, if the output of one of the continuity detection counters 23, 25 is configured not to reset the other continuity detection counters 25, 23, when noise is generated during the generation period of the window signal W11, the AND circuit 22a H indicating a match from
Since the signal of the level is output and the signal is not in a non-signal state at this time, the FF circuits 25a and 25b are not reset. As a result, the continuity detection counter 23 outputs the 60/525 system with the third noise. Is generated, and the S-RFF circuit 29a is set. Therefore, from the output terminal Q of the S-RFF circuit 29a, an L-level signal indicating the 50/625 system must be actually generated, but an H-level signal indicating the 60/525 system is generated. This causes a malfunction. Further, the outputs DATA1 and DATA2 of the continuity detection counters 23 and 25 may be at the H level at the same time, and a malfunction easily occurs.

On the other hand, as shown in FIG. 4, the output of one continuity detection counter 23, 25
FIG. 6 (B) shows a configuration in which reset is applied to 23.
As shown in the timing chart, during the period when the reset input terminal R of the S-RFF circuit 29a is at the H level, the continuity detection counter 23 for determining the 60/525 system is reset to stop its operation. At the same time, by initializing the FF circuits 23a and 23b, there is no period during which the set input terminal S of the S-RFF circuit 29a is at the H level, and malfunction can be prevented.

It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the scope of the invention.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide an extremely good vertical synchronization frequency discrimination circuit which is resistant to input television signal dropout or noise and hardly malfunctions.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a vertical synchronization frequency discriminating circuit according to the present invention. FIGS. 2 and 3 are timing charts for explaining the operation of the embodiment.
5 is a block diagram showing an example of a specific configuration of a part of the embodiment, FIGS. 5 and 6 are timing diagrams for explaining the operation of the circuit shown in FIG. 4, and FIG. FIG. 8 is a block diagram showing a conventional vertical synchronization frequency discrimination circuit.
FIG. 9 and FIG. 9 are timing charts for explaining the operation of the conventional circuit. 11 Input terminal, 12 Vertical down counter, 13 Clock terminal, 14 No signal detection circuit, 15 Continuous detection counter, 16 Match detection circuit, 17 Output terminal, 18
... input terminal, 19 ... vertical down counter, 20 ... clock terminal, 21 ... decoder circuit, 22 ... match detection circuit, 23
…… Continuity detection counter, 24… Match detection circuit, 25 ……
Continuity detection counter, 26, 27… OR circuit, 28… No-signal detection circuit, 29… Judgment result holding memory, 30… Output terminal, 31-34… Input terminal.

────────────────────────────────────────────────── ─── of the front page continued (72) inventor Akihiro Murayama Yokohama, Kanagawa Prefecture Isogo-ku, Shinsugita-cho, address 8 Toshiba Corporation Yokohama office appliances intra-technology research Institute (58) investigated the field (Int.Cl. ^7, DB name ) H04N 17/00-17/06

Claims (1)

(57) [Claims] A first and a second having different frequencies from each other.
Window generating means for generating first and second window signals having a period corresponding to the vertical synchronizing signal, and the first and second window signals generated by the window generating means and the input vertical synchronizing signal. First and second coincidence detecting means for respectively detecting substantial coincidence of the cycles, and first and second coincidence detection outputs of the first and second coincidence detecting means for counting a predetermined number of outputs respectively. Output means for setting one of the outputs of the first and second counting means, which is supplied first, and inverting the setting state only when the other output is supplied in the setting state A no-signal detecting means for detecting that the vertical synchronizing signal is not inputted; resetting the first and second counting means based on an output of the no-signal detecting means; Control means for resetting the second counting means at the output of the second counting means and resetting the first counting means at the output of the second counting means. circuit.