JPS628620Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention supplies a frequency signal of a predetermined frequency related to an input horizontal synchronizing signal separated from an input composite video signal to a frequency division counter with a predetermined frequency division ratio, and counts the input signal. A vertical synchronization circuit that outputs a signal related to the output from the frequency division counter as an output vertical synchronization signal by resetting the frequency division counter with an input vertical synchronization signal separated from a composite video signal. Involved in improvements.

If such a vertical synchronization circuit is installed in a television receiver, when receiving a standard television signal such as an NTSC television signal, a reproduced image with reliable interlacing can be obtained, and noise can be reduced. It is preferable because it is strong and can be easily made without adjustment.

However, in the case of a video signal from a video game device or a special playback mode of a VTR, such as still image, low speed, double speed playback, etc., the vertical synchronization signal of the video signal is the same as the vertical synchronization signal of the standard broadcast television signal mentioned above. Since the signals are different from each other, malfunctions occur, vertical synchronization becomes unstable, and the playback screen of the television receiver becomes difficult to see.

For example, in the case of a television game device, since there is no equalization pulse in the vertical synchronization signal, interlacing is not performed, and the vertical synchronization of the television receiver is disrupted, making the reproduced screen distorted and difficult to view.

In addition, in the special playback mode of a VTR, an abnormality occurs in the vertical synchronization signal of the reproduced video signal, so the vertical synchronization of the television receiver becomes unstable, causing the reproduction screen to become distorted and difficult to view. .

Also, some VTRs generate a pseudo sync signal following the vertical sync signal, but in such cases, the frequency dividing counter is used for both this vertical sync signal and the following pseudo sync signal. Since the reset is applied to the TV receiver, the vertical synchronization of the television receiver is disrupted, and the playback screen becomes distorted and difficult to view.

Therefore, when the vertical synchronization signal in the reproduced video signal in the special playback mode of the VTR is abnormal, the vertical synchronization circuit described above is not used, and the input vertical synchronization signal separated from the input composite video signal is used. If the signal is used as it is as an output vertical signal, the playback screen of the television receiver will be more stable.

In view of this, the present invention provides that, if the input vertical synchronization signal in the input composite video signal differs from the standard vertical synchronization signal, the signal related to the input vertical synchronization signal separated from the input composite video signal is automatically separated from the input vertical synchronization signal. It is an object of the present invention to provide a vertical synchronization circuit that can output vertical synchronization signals.

The vertical synchronization circuit of the present invention supplies a frequency signal of a predetermined frequency related to an input horizontal synchronization signal separated from an input composite video signal to a frequency division counter with a predetermined frequency division ratio for counting. In a vertical synchronization circuit that outputs a signal related to the output from the frequency division counter as an output vertical synchronization signal by resetting the frequency division counter with an input vertical synchronization signal separated by A time width discrimination circuit determines whether the time width of the input vertical synchronization signal is a normal value, and when the time width of the input vertical synchronization signal differs from the normal value, a frequency division counter is set based on the discrimination output of the time width discrimination circuit. The apparatus is provided with circuit means for automatically outputting a signal related to the input vertical synchronization signal as a direct output vertical synchronization signal instead of a signal related to the output of the input vertical synchronization signal.

An embodiment of the present invention will be described in detail below with reference to FIG.

Reference numeral 1 denotes an input terminal to which a frequency signal of a predetermined frequency related to the input horizontal synchronizing signal separated from the input composite video signal is supplied. This frequency signal is synchronized by an input horizontal synchronizing signal and is an oscillation signal from an oscillator having an oscillation frequency of twice the horizontal frequency, that is, 31.5 KHz. Reference numeral 2 denotes an input terminal to which an input vertical synchronization signal obtained by integrating a composite synchronization signal separated from the input composite video signal is supplied. 3 is an output terminal for the finally obtained output vertical synchronizing signal. Note that the output vertical synchronization signal obtained from this output terminal 3 serves as a trigger signal for the vertical oscillator. 4 is the frequency mentioned above.
This is a frequency division counter that divides a 31.5KHz frequency signal (pulse) by a predetermined frequency division ratio, in this case 1/525. A frequency signal (pulse) from the input terminal 1 is supplied to the input terminal IN of the counter 4, and when 525 pulses are counted, an output is obtained at the output terminal OUT. Further, R is a reset input terminal of the counter 4. In addition, counter 4 is actually 525.
Use a counter that is greater than or equal to
525, an output is generated and a reset signal is supplied to the reset signal input terminal R. In this case, for ease of explanation, the above-mentioned configuration is used. Reference numeral 5 designates a first changeover switch that switches between the output of the counter 4 and the input vertical synchronizing signal supplied from the input terminal 2 and supplies the same to the reset signal input terminal R of the counter 4. This has a movable contact m connected to the reset signal input terminal R, a fixed contact a connected to the output terminal OUT of the counter 4, and a fixed contact b connected to the input terminal 2. A second changeover switch 6 switches between the output of the counter 4 and the input vertical synchronization signal from the input terminal 2, and outputs the signal to the output terminal 3. This consists of a movable contact m connected to the output terminal 3 and a fixed contact a connected to the output terminal OUT of the counter 4.
and a fixed contact b supplied to the input terminal 2. 7 is a vertical synchronization signal discrimination circuit which has two functions. That is, when the output of the counter 4 and the input vertical synchronizing signal from the input terminal 2 are out of phase, the movable contact m is connected to the fixed contact a during normal operation.
The function of switching the movable contact m of the changeover switch 5 to the fixed contact b side and supplying the input vertical synchronization signal from the input terminal 2 to the reset input terminal R of the counter 4, and the function of switching the input vertical synchronization signal from the television game device to the reset input terminal R of the counter 4. In cases where the vertical synchronization signal does not have equalization pulses, such as the input composite video signal of It has a function of detecting this and switching the movable contact m of the changeover switch 5 to the fixed contact b.

8 is a time width determining circuit that determines whether the time width of the input vertical synchronizing signal separated from the input composite video signal is a normal value or not. Then, when the time width of the input vertical synchronization signal is different from the normal time, the above-mentioned second changeover switch 6 selects a signal related to the output from the frequency division counter 4 based on the discrimination output of the time width discrimination circuit 8. Instead, the signal related to the input vertical synchronization signal is automatically output to output terminal 3 as a direct output synchronization signal.
It is a circuit means for outputting more than one output signal.

Next, the time width discrimination circuit 8 will be explained. In the circuit 8, _Q1 to _Q6 are transistors, and + is a B power supply. The input vertical synchronizing signal from the input terminal 2 is supplied to the base of the preceding transistor Q ₁ of the transistors Q ₁ and Q ₂ forming the waveform shaping circuit 9 .
As a result, the waveform shaping circuit 9 outputs a rectangular wave signal having a time width corresponding to the input vertical synchronizing signal. This output is then supplied to the charging circuit 10.

The charging circuit 10 is a constant current charging circuit, and the transistor Q ₃ is turned on for a period corresponding to the time width of the rectangular wave pulse from the waveform shaping circuit 9, and the capacitor C ₁ is charged with a constant current. and,
The terminal voltage of the capacitor C ₁ is approximately proportional to the time width of the rectangular wave pulse from the waveform shaping circuit 9. Then, transistor Q ₃ is turned off and the charge on capacitor C ₁ is transferred to resistor R ₁ - level comparator circuit 1.
1 through the base of transistor _Q4 . In addition, resistor R ₂ and capacitor
_C2 constitutes a ripple removal circuit. resistor R ₁
(22KΩ) and _R2 (470KΩ) is supplied to the base of the transistor _Q4 of the level comparison circuit 11.

In the level comparison circuit 11, the emitter of the transistor _Q4 is connected to the base of the transistor _Q5 , and the voltage of the power supply +B in the transistor _Q5 is divided by the resistors _R3 and _R4 and applied to the emitter of the transistor Q5. The voltage and the base voltage of transistor Q ₅ are compared, and the comparison output is obtained from its collector and supplied to the base of transistor Q ₆ of discrimination output circuit 12 .

Then, when the time width of the input vertical synchronization signal is larger than a predetermined value, based on the output of the discrimination circuit 12,
The movable contact m of the switch 6 is switched to the fixed contact b side. Further, in this case, both the changeover switch 5 and its movable contact m are switched to the fixed contact b side.
Further, when the time width of the input vertical synchronizing signal is normal, the movable contact m of the switch 6 is switched to the fixed contact a.

Next, the above-mentioned charging circuit 10 will be further explained with reference to FIG. 2. FIG. 2 is a curve diagram showing the change in the terminal voltage V _c of the capacitor C ₁ with respect to time t. In Figure 2, V ₀ is V _c and V ₁ at t=0.
indicates V _c when t=τ _v (vertical synchronization period), and V′ ₀ indicates V _c when t=T _v (vertical period), respectively. Then, when I _c is a constant charging current, T is a discharging time constant, and C is a capacitance of a capacitor C ₁ , V ₁ and V' ₀ are expressed as in the following equation.

V ₁ =V ₀ +τ _v I _c /C…(1) Here, if V ₀ =V′ ₀ , V ₁ is expressed as the following equation.

Here, if T is larger than T _v , then Therefore, equation (3) can be expressed as the following equation.

V ₁ =τ _v I _c /C·T/T _v −τ _v (5) Therefore, it can be seen from equation (5) that V ₁ increases as τ _v increases.

Therefore, if, for example, a regular vertical synchronization signal and a subsequent pseudo synchronization signal (the order may be reversed) are input to input terminal 2 within a vertical period, τ _v will be approximately twice the normal value. It is equivalent to summer.

According to the present invention described above, even if the input vertical synchronization signal of the input composite video signal is different from the normal one, as in the special playback mode of a VTR, this is automatically detected and the input vertical synchronization signal related to the input vertical synchronization signal is automatically detected. The signal can be directly output as the vertical synchronizing signal, and if the input vertical synchronizing signal of the input composite video signal is a standard signal, the output from the frequency division counter 4 mentioned above becomes the output vertical synchronizing signal. , it is possible to obtain a vertical synchronization circuit that can always provide a reproduced screen without vertical disturbance depending on the nature of the input composite video signal.

Incidentally, in the above embodiment, the vertical synchronization signal determination circuit 7
In the case of a vertical synchronizing signal that does not have an equalization pulse, such as in a television game device, the counter 4 is reset by the vertical synchronizing signal, so that correct playback is possible even in this case. You will get a screen.

Note that a waveform shaping circuit may be provided on the output side of the counter 4 and the input terminal 2, respectively, to output a rectangular wave signal whose time width is set to a desired value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a curve diagram for explaining the same. 1 is an input terminal for a frequency signal, 2 is an input terminal for an input vertical synchronization signal, 3 is an output terminal for an output vertical synchronization signal, 4 is a frequency dividing counter, 5 is a first changeover switch, and 6 is a first switch as a circuit means. 2 is a changeover switch, 7 is an output synchronization signal discrimination circuit, 8 is a time width discrimination circuit, 9 is a waveform shaping circuit, 10 is a charging circuit,
11 is a level comparison circuit, and 12 is a discrimination output circuit.

Claims (1)

[Scope of utility model registration request] A frequency signal of a predetermined frequency related to the input horizontal synchronizing signal separated from the input composite video signal is supplied to a frequency division counter with a predetermined frequency division ratio for counting, and a frequency signal of a predetermined frequency related to the input horizontal synchronizing signal separated from the input composite video signal is In the vertical synchronization circuit, the input vertical synchronization circuit outputs a signal related to the output from the frequency division counter as an output vertical synchronization signal by resetting the frequency division counter with a synchronization signal. a time width discrimination circuit that discriminates whether the time width of the signal is a normal value; and when the time width of the input vertical synchronization signal differs from the normal value, the frequency division counter is operated based on the discrimination output of the time width discrimination circuit; circuit means for automatically outputting a signal related to the input vertical synchronization signal directly as the output vertical synchronization signal instead of a signal related to the output of the vertical synchronization circuit.