JPH0441659Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field The invention is used in television receivers to process a composite synchronization signal separated from a video signal.
The present invention relates to a vertical synchronization signal separation circuit for extracting a vertical synchronization signal.

(b) Prior art With the spread of VTRs (video tape recorders), the amount of soft tape used is increasing. In some cases, the vertical synchronization signal part is recorded with a different vertical synchronization signal part as shown in Fig. 1a, unlike that of a normal television video signal (Fig. 1a). For this reason, even if a reproduced video signal from such a tape is input to a television receiver, vertical synchronization may not be achieved properly, and the screen may not be able to stand still. That is, in the case of the video signal shown in Figure 1a, if this signal is synchronized and separated and then passed through an integrating circuit, it will become as shown in Figure 1b, and the reference level (L) of the level comparison circuit for vertical synchronization signal separation will be Therefore, this circuit can separate the vertical synchronization signal. However, in the case of the video signal in Figure 1a,
Since the width of each pulse p of the vertical synchronization signal part VP in this signal is narrower than normal, if it is processed in the same way as above, it will become as shown in b' in the same figure, and it will not leave the level L. Therefore, the vertical signal portion VP cannot be separated. In addition, in Figure 1,
EP is the equalization pulse part.

In order to solve this problem, it is possible to set the sensitivity (integral effect) of the above-mentioned integration circuit to the vertical synchronization signal section to be high, but this method does not allow special playback such as fast-forward playback or slow playback of a VTR. In this case, the playback noise near the vertical synchronization signal is integrated by the above integration circuit and reaches the reference level of the level comparison circuit, so the vertical synchronization signal obtained from this comparison circuit fluctuates, causing the reproduced image to vibrate up and down. It was hot.

(c) Purpose of the invention This invention was created in view of the above points,
It is an object of the present invention to make it possible to reliably separate and derive a stable vertical synchronization signal not only from a normal video signal but also from a video signal in which the vertical synchronization pulse is narrowed.

(d) Structure of the invention The invention provides a television receiver to which a reproduced video signal is input, in which the pulse width of each pulse of a vertical synchronizing signal section divided by incision pulses is set to be narrower than that of a broadcast signal. , the composite synchronization signal separated from the input video signal is input, and a first integrating circuit is configured to set a small time constant during charging and a large time constant during discharging; A first level comparison that introduces an integral output, compares the integral output with a predetermined reference level, and outputs a vertical synchronizing signal whose starting position is shifted from the starting position of the vertical synchronizing signal portion in the composite synchronizing signal. an addition circuit that adds the vertical synchronization signal from the first level comparison circuit to the vertical synchronization signal part of the composite synchronization signal to derive the added composite synchronization signal; and an addition circuit that derives the added composite synchronization signal; a second integrating circuit having a larger time constant during charging and a smaller time constant during discharging than the first integrating circuit;
This is a vertical synchronization signal separation circuit for a television receiver, which includes a second level comparison circuit that creates and outputs a vertical synchronization signal from an integral output signal from an integration circuit.

(E) Embodiments FIGS. 2a to 2c show schematic configurations of three embodiments of the vertical synchronization signal separation circuit according to the present invention. First, to explain the embodiment shown in FIG. , 3 is a first integration circuit that integrates the output signal, and 4 is a first level comparison circuit that compares the output with a constant reference level. Further, 5 is an adder circuit that adds the output signal of the comparison circuit 4 to the composite synchronization signal from the synchronization separation circuit 2 at a predetermined level, and 6 is a second integration circuit that integrates the output signal.
7 is a second level comparison circuit to which the output thereof is input;
8 is an output terminal from which a vertical synchronizing signal is obtained.

Here, even if the width of each pulse of the vertical synchronizing signal part is narrow, the first integrating circuit 3 has a sensitivity ( (the time constant of the charging group of the first integrating circuit 3 is set small and the time constant during discharging is set large), and the first level comparator circuit 4 is set vertically from the above integrated waveform. A reference level is set so that the synchronization signal can be separated. On the other hand, in order to prevent malfunctions due to noise in the vicinity of the vertical synchronizing signal of the VTR video signal during special playback as described above, the sensitivity of the second integrating circuit 6 to the vertical synchronizing signal section is set to the same level as that of the first integrating circuit 6. (the first integrator circuit
Set the time constant for charging larger and the time constant for discharging smaller than in (3). , second level comparison circuit 7
The standard level has been set accordingly.

Therefore, the input terminal 1 is now connected to the vertical synchronizing signal part VP (third
(see figure a), the output waveform of the first integrating circuit 3 becomes the figure b, and this output waveform is compared with the reference level _L1 in the first level comparator circuit 4, and the signal shown in figure c is obtained. It will be done. This signal corresponds to the vertical synchronization signal part VP in the original composite synchronization signal a.
There is a delay of about 0.5H (H: 1 horizontal period),
This is added to the synchronization signal a in the adder circuit 5. Therefore, the output signal of this adder circuit 5 becomes as shown in FIG. Even in this case, an integrated waveform exceeding the reference level _L2 of the second level comparison circuit 7 can be obtained as shown in FIG. As a result, output terminal 8
This means that the vertical synchronization signal can be separated and derived.

Note that the above operation is performed when a vertical synchronization signal section with a narrow pulse width is input, but the third
Signals similar to those shown in Figures b to e are obtained, but in this case, since each pulse width of the vertical synchronization signal section is wide, the reference level is reached near the beginning of the vertical synchronization signal section as shown in Figure 1b. It will exceed L ₂ .
Therefore, in this case, the leading edge of the vertical synchronizing signal obtained at the output terminal 8 is as shown by the broken line in FIG. It's just that there's a delay. At this time, the position of the trailing edge of the vertical synchronizing signal also changes, but this does not pose any problem since the leading edge is necessary as the vertical synchronizing signal.

Next, in the embodiment shown in FIG. 2b, parts corresponding to those in FIG. This is a preferred embodiment when a synchronous separation IC 9 is used in which an external terminal is connected to the connection path between the two. That is, in this embodiment, another synchronous separation circuit 2' is provided separately from the synchronous separation circuit 2 in the IC 9, and the output signal of the first level comparison circuit 4 is added to the input video signal by the addition circuit 5. The synchronous separator circuit 2 in the IC 9 is designed to include the synchronous separator circuit 2 in the above-mentioned IC 9. It is also possible to construct it as in the embodiment shown in FIG. 2c. The operation of each embodiment is as follows:
Both are basically the same as those shown in FIG. 2a described above.

FIG. 4 shows a specific example of the circuit configuration in the case of FIG. 2b, and parts corresponding to those in FIG. 2b are given the same figure numbers. In the figure, TR ₁ is an emitter follower transistor for impedance conversion for an input video signal, and a positive video signal derived from the emitter of this transistor is used as a first and second time constant that determines the synchronization separation level. Circuit TC ₁ TC ₂
The signal is inputted to the first synchronous separation circuit 2' outside the IC 9 and the second synchronous separation circuit 2 inside the IC via the .

The IC9 is a one-chip IC for video, chroma, and deflection manufactured by NEC Corporation: μPC1401C, and this IC is connected to each of the circuits 2, 6, and
7 is built-in, but it should be noted here that the capacitors etc. that make up the second integrating circuit 6 are also integrated into an IC. The first synchronous separation circuit 2' is mainly composed of a separation transistor TR ₂ operating as a common base type and a transistor TR ₃ for inverting the polarity of the output signal obtained at its collector. The configuration is similar to that of the 2-sync separation circuit 2. In addition, D ₂ of diode D ₁
is for limiting the collector current of the isolation transistor _TR2 .

Next, the first integrator circuit 3 is composed of resistors R ₁ to R ₃ and capacitors C ₁ and C ₂ , but here, the sensitivity of the circuit 3 to the vertical synchronization signal section is sufficiently high as described above. It should be noted that the time constant during charging is set small and the time constant during discharging is set large. Further, the first level comparison circuit 4 is composed of a switching transistor _TR4 to which the above-mentioned integral output is applied to the base.
The adder circuit 5 passes the pulse signal obtained from the transistor TR ₄ through the diode D ₃ to a second time constant circuit.
The configuration is connected to point A in TC ₂ . Here, the anode side of diode _D3 is connected to the above point A by the capacitor in the second time constant circuit _TC2 .
This is because the 4.7 μF is also used as a coupling capacitor for the above pulse signal.

(f) Effects of the invention According to the vertical synchronization signal separation circuit of the invention, it is possible to remove video signals reproduced from a VTR, etc. whose pulse width has been narrowed in the vertical synchronization signal section for the purpose of preventing dubbing, etc.
A stable vertical synchronization signal can be reliably separated and derived.
Then, wide and negative noise (for example, fast-forward playback of a VTR,
Even if noise (during special playback such as slow playback) is mixed in, after the noise has been separated and derived by the first integration circuit, the second integration circuit is further configured to prevent the noise from being separated and derived by the second integration circuit. Since the integral effect of is reduced, malfunctions due to noise can be prevented. Furthermore, the vertical synchronization signal does not have any adverse effect on a normal video signal, and it is possible to obtain a logical vertical synchronization signal that is extremely slightly delayed from the vertical synchronization signal portion of the video signal. Therefore, it is suitable for implementation in a television receiver used in combination with a VTR or the like.

[Brief explanation of drawings]

FIG. 1 is a signal waveform diagram for explaining the drawbacks of the conventional vertical synchronization signal separation circuit, and FIG. 2 is a block diagram showing the schematic configuration of three different embodiments of the present invention.
Figure 3 is a signal waveform diagram for explaining its operation, and Figure 4 is a signal waveform diagram for explaining its operation.
The figure is a circuit diagram showing a specific circuit configuration example of one of the above embodiments. VP...Vertical synchronization signal section, EP...Equalization pulse section.

Claims (1)

[Claims for Utility Model Registration] In a television receiver to which a reproduced video signal is input, in which the pulse width of each pulse of a vertical synchronizing signal section divided by incision pulses is set to be narrower than that of a broadcast signal, a first integrating circuit into which a composite synchronizing signal separated from the input video signal is input, a time constant for charging is set small and a time constant for discharging is set large; and an integral output from the first integrating circuit. , compares the integral output with a predetermined reference level, and outputs a vertical synchronization signal whose starting position is shifted from the start position of the vertical synchronization signal portion in the composite synchronization signal.
a level comparison circuit; an addition circuit that adds the vertical synchronization signal from the first level comparison circuit to the vertical synchronization signal portion of the composite synchronization signal to derive the added composite synchronization signal; and composite synchronization after the addition. the first to which the signal is input;
A second integrating circuit whose time constant during charging is set to be larger than that of the integrating circuit and time constant during discharging is set smaller than that of the integrating circuit, and a second level that creates and outputs a vertical synchronization signal from the integrated output signal from the second integrating circuit. A vertical synchronization signal separation circuit for a television receiver consisting of a comparison circuit.