JPH0681241B2 - DC regeneration circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for processing a copy image signal having a line sync frequency of a relatively low frequency such as a facsimile signal.

2. Description of the Related Art Conventionally, when handling a video signal of a television receiver, a VTR, or the like, AC coupling is often used as the coupling between circuits due to the type of the amplifier and the power supply voltage. However, when displaying on the display or when performing modulation, in order to prevent the white and black reference levels from changing with time or due to the signal waveform, the direct current reproduction circuit (clamp circuit) reproduces the direct current component. Process. FIG. 3 is a circuit diagram showing a conventional example. In FIG. 3, reference numerals 34 and 35 denote transistors, the inputs and outputs of which enter the respective bases and are output from the various emitters. 30,32 is resistance, 3
1 is a variable resistor, and 33 and 36 are capacitors. 37
Represents a diode. Each transistor
The operation of 34 and 35 is an emitter follower circuit, and the collectors are both connected to the power supply (for example, refer to "Video Tape Recorder" P77-78 Nikkan Kogyo Shimbun
Nobutoshi Kihara (1965).

Problems to be Solved by the Invention However, the circuit described above causes almost no problem when the horizontal synchronizing signal is as high as 15.73 KHz like the standard television signal, but the horizontal synchronizing signal becomes a dozen Hz G When it comes to II standard facsimile signals, the problem becomes more serious.

This problem will be described below. FIG. 4 is a signal waveform diagram for explaining the above problems, where A is a white peak signal, B is a black signal, and C is a waveform diagram in which both are combined with reference to the DC voltage OV.

In FIG. 4, 20 is a horizontal synchronizing signal, 21 includes a white peak, 22 is a black signal portion, and 23 is a black signal surrounded by white peak signals. A'and B'in C represent the waveforms corresponding to A and B in FIG. Generally, in the AC coupling circuit, since the circuit connection is made via a capacitor, only the signal needs to be focused without changing the DC operating point of each transistor. However, as mentioned above, the DC must be regenerated when absolute levels are required. That is, assuming that the DC voltage OV is always fixed, the DC component of the white peak signal shown in FIG. 4A and the DC component of the black signal shown in FIG. 4B operates so as to become OV. The level shown by the dotted line in FIG. 4A is the DC component, and when the black signal, that is, the amplitude becomes small as shown in FIG. 4B, the level shown by the dotted line in FIG. 4B becomes the DC component. As the circuit, the white peak signal and the black signal are handled in the same way, and as a result, the signal goes up and down as shown in FIG. 4C. As a result, a difference occurs between the level of the black signal portion 23 shown in FIG. 4A and the level of the original black signal. The error of ΔV represented by ΔV in FIG. 4C is a principle error due to AC coupling, and in addition to this, usually, the voltage at which the DC regeneration holding level changes due to the discharge of the charge charged in the capacitor Is added. This is because the charge charged in the capacitor 33 shown in FIG. 3 is discharged because the input impedance of the emitter follower circuit by the transistor 35 is not infinite.
This development causes almost no problem at horizontal sync frequencies such as standard television signals, but as mentioned earlier,
In a facsimile signal such as Hz, since the horizontal synchronization period is long in time, the holding level changes even if the impedance is large, resulting in a brightness difference.

Means for Solving the Problems In order to solve the above problems, the present invention uses a sample hold circuit as a function means for holding a direct current, thereby preventing the discharge of the problem and at the same time, a black signal immediately after a sync signal. A differential amplifier for sampling a region (pedestal level), holding the voltage, and taking a difference signal between the input signal and the sampled and held voltage is used.

Operation The present invention has the above-mentioned configuration and reproduces a DC signal in which the fluctuation of the DC level in principle due to AC coupling is eliminated.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, 1 is a synchronization detection circuit, 2 is a pulse shaping circuit, 3 is a sample hold circuit, 4 is a differential amplifier, and 5
Is an input terminal, and 6 is an output terminal. Figure 2 shows the first
It is a signal waveform diagram which shows operation | movement of each part of the direct current reproduction circuit shown in FIG. In FIG. 2, a is an input signal, b is an output signal of the synchronization detection circuit, c is an output signal of the pulse shaping circuit 2, d is an input signal with many white levels, and d is an input signal with many black levels.

The operation of this embodiment will be described below with reference to FIGS. 1 and 2. First, the AC-coupled input signal a is input from the input terminal 5. The input signal a is input to the sync signal detection circuit 1, the sample hold circuit 3, and the positive phase input of the differential amplifier 4. The synchronization detection circuit 1 is usually composed of a television receiver, a VTR, and the like. As the output of the sync detection circuit 1, only the horizontal sync signal shown in FIG. 2b is output. The output of the sync detection circuit 1 is input to the pulse shaping circuit 2, where a pulse having a pulse width used as a sample pulse of the sample hold circuit 3 is delayed by Δt from this sync signal based on the detected sync signal. To create. In this implementation method, one-shot (mono-multi) circuits that are normally used may be connected in two stages, or a delay time width and a pulse width may be configured by a logic circuit from a clock signal having a sufficiently high frequency. The output sample pulse enters the sample hold circuit 3. On the other hand, the sample-hold circuit 3 takes in the voltage at the sample pulse position shown in FIG. 2c by the input signal a input at each pulse arrival and holds it. The held voltage is a DC voltage, and the voltage is held until the next sample pulse arrives. The held voltage signal is input to the negative phase input terminal of the differential amplifier 4. Since the differential amplifier 4 generates an output by subtracting the positive phase input from the negative phase input, an output signal whose voltage at the sample pulse position is always OV is obtained as a result. For example,
Consider a case where a signal with a large white level as shown in FIG. 2d is used as an input signal. In FIG. 2d, the dotted line indicates the DC component of the signal, and the alternate long and short dash line indicates the sampled and held voltage (the same applies to FIG. 2e). Although there is a difference H ₁ between the DC component and the sample hold voltage in FIG. 2D, the output can be obtained as the sample hold voltage, that is, the black level reference voltage is OV, by the action of the differential amplifier. Further, even if a signal with many black signals shown in FIG. 2e is input, an output voltage whose sample position is OV is obtained, and direct current reproduction can be completed. Basically, there is a sample-hold circuit in which a capacitor is charged with a holding voltage and a high-impedance element such as a FET is received, and the sample-hold circuit is also available as an IC element. It is also possible that it can be performed purely digitally.
That is, the input signal is sampled and held, the hold voltage is A / D converted, stored in a memory by a logic circuit, and the output is D / A converted, so that the held voltage is permanently held until the power is turned off. It is possible to keep holding.

EFFECTS OF THE INVENTION As described above, in the present invention, there is no change in luminance that occurs in principle by AC coupling, and since the sample hold circuit is used, there is no change in the holding level due to discharge of the capacitor.
It is essentially possible to reproduce direct current, and it is possible to eliminate the phenomenon that the brightness differs at the beginning and end of horizontal synchronization when displayed on a display.

[Brief description of drawings]

FIG. 1 is a block diagram of a DC regenerating circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the respective parts, FIG. 3 is a circuit diagram showing a conventional example, and FIG. It is a signal waveform diagram for explaining the operation of each part. 1 ... Synchronous detection circuit, 2 ... Pulse shaping circuit, 3 ... Sample hold circuit, 4 ... Differential amplifier.

Claims (1)

[Claims] 1. A synchronization detection circuit for detecting a synchronization signal of an image signal, a pulse shaping circuit for generating a sample pulse delayed by a predetermined minute time from a horizontal synchronization signal detected by the synchronization detection circuit, and a sampling pulse of the sample pulse. A direct current reproduction circuit comprising a sample hold circuit for holding the voltage of the image signal at the time of input, and a differential amplifier having the hold voltage of the sample hold circuit as the negative phase input and the image signal as the positive phase input. .