JPS60197075A - Synchronizing signal eliminating device - Google Patents

Abstract

PURPOSE:To attain the reproduction of a luminance level with fidelity by using a pedestal level with sample-hold by a back porch pulse to eliminate a detected error of the pedestal level even if the average luminance level of a video signal is fluctuated. CONSTITUTION:The input video signal 10 including a synchronizing signal is inputted to a sample hold circuit 12, a switch circuit 14 and a synchronizing separator circuit 16. A horizontal synchronizing signal 20 is extracted from the synchronizing separator circuit 16, the back porch pulse is formed by monostable multivibrators 18, 19 and a blanking pulse 40 is formed by monostable multivibrators 22, 24 based on the synchronizing signal 20. The sample hold circuit 12 samples and holds a signal level of the back porch by using a back porch pulse 30 and the result is outputted to a switch circuit 14. The switch circuit 14 selects the output of the circuit 12 when the pulse 40 is at a high level and the input video signal 10 is selected at a low level and an output video signal 50 from which the synchronizing signal is eliminated is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a synchronization signal removing device that removes horizontal and vertical synchronization signals, or burst signals that are 2-synchronization signals, etc. contained in a video signal from the video signal.

<Description of Prior Art> A conventional synchronization signal removal circuit is shown in FIG. 1, and its waveform is shown in FIG.

The video signal 1 including the input synchronizing signal is kept at the pedestal level by the back porch noise 6 generated at the back porch of the video signal by the pedestal clamp circuit.

set to a constant DC level. The output of the pedestal clamp circuit 2 is input to a blanking removal circuit 4, and under the control of a blanking pulse 5, the same zero level as the pedestal level of the pedestal clamp circuit 2 is output during the blanking period, and the blanking removal circuit 4 outputs the same zero level as the pedestal level of the pedestal clamp circuit 2. Outside of the ranking period,
A video signal output from the pedestal clamp circuit 2 is output. Therefore, from the blanking removal circuit 4,
The pedestal level of the video signal is output during the blanking period, and the video signal is output during the other periods, making it possible to remove the synchronization signal from the video signal including the input synchronization signal.

However, when performing flagging to reproduce the DC component of a video signal, the AFL (average brightness level of the video signal) changes, so it is difficult to accurately reproduce the DC component from the input video signal. The circuit configuration becomes complicated.

Furthermore, if clamping is not performed accurately, the clamp output signal changes the level of the pedestal as the APL changes, and the brightness level of the output signal from which the synchronization signal has been removed will eventually fluctuate.

In other words, the circuit characteristics of the clamp circuit greatly affect the output signal. For example, by using a clamp circuit that suppresses fluctuations in clamp output, such as a feedback clamp circuit, it is possible to suppress the effect of fluctuations in APL to some extent, but this increases the circuit scale and causes an increase in cost.

<Object of the Invention> In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a synchronization signal removal device in which fluctuations in the DC component of the signal do not affect the synchronization signal removal output, regardless of the characteristics of the circuit. There is.

<Description of Embodiment> A synchronization signal removal circuit according to an embodiment of the present invention is shown in FIG.
FIG. 4 shows signal waveforms at each part.

An input video signal 10 containing a synchronization signal is input to a sample hold circuit (hereinafter referred to as S/H circuit) 12, a switch circuit 14, and a synchronization separation circuit 16. A horizontal synchronization signal 20 is extracted from the zero synchronization separation circuit 16. Based on the synchronization signal 20, a vacuum pouch pulse 60 is formed by the mono multi-vibrator 18, 19, and a blanking pulse 40 is formed by the mono-multi vibrator 25, 24. The S/H circuit 12 samples and holds the back porch signal level based on the back porch pulse 301C, and outputs it to the switch circuit 14.

The switch circuit 14 selects the output of the 8/H circuit 12 when the blanking pulse 40 is at a high level, and selects the input video signal 10 when it is at a low level to obtain an output video signal 50 from which the synchronizing signal has been removed.

In this way, set the pedestal level to back porch pulse 60
Since the pedestal level is obtained by sample and hold, there is no detection error in the pedestal level even if the AFL changes, making it possible to faithfully reproduce the brightness level.

Figure 5 was obtained by decoding the NT8C video signal (B-Y)
FIG. 6 is a signal waveform diagram when removing a color burst signal from a signal. The circuit diagram can be realized with almost the same circuit configuration as in Fig. 6, so the details are omitted. 20' is not included. Synchronization signal 20
' is obtained from the synchronization separation circuit 16 in FIG.
A synchronization timing signal 60/and a blanking signal 40' which becomes high level during the burst period are formed based on '. Then, the (B-Y) signal 10' is sampled and held at the timing of the synchronization timing signal 60/, and the color difference is zero.
(2) Take out the signal and replace the input (B-Y) signal during the period in which the blanking pulse 40' is at a high level with a color difference Ov times signal.

With this configuration, the color burst signal 65
A (B-Y) signal 50' can be obtained by removing the (B-Y) signal.

In this embodiment as well, even if the average level of the input (B-Y) signal fluctuates, the color difference 0 level can be accurately extracted, so that the input (B-Y) signal can be faithfully transmitted.

FIG. 6 shows the 8/H circuit 12 and switch circuit 14 of FIG.
〇Capacitor 110, resistor 111.112. tlt14 transistor 116ti constitutes a buffer, and the input video signal 10 is converted into a low impedance signal from the emitter of transistor 116.0 resistor 115. Inverter 117. analog switch 11
6. Capacitor 118 constitutes S/H circuit 12. Inverter 117. Analog switch 116 is C-M
It constitutes an O8 type analog switch. When the bank porch pulse 60 is at a high level, the analog switch 116 is turned on, and the emitter output signal of the transistor 113 passes through the resistor 115 and the analog switch 116 and is held in the capacitor 118. back porch pulse 30
When is at p-level, analog switch 116 is turned off and capacitor 118 holds the previous voltage.

Analog switches 119, 120. Inverter 121 constitutes switch circuit 14 . This turns on the analog switch 120 and turns off the analog switch 119.

Also, when the blanking pulse 40 is at a low level, the analog switch 119 is turned on and the analog switch 120 is turned off. Therefore, the pedestal level accumulated in the capacitor 118 is
During the blanking period, the output video signal 50 is output, and during other periods, the emitter output of the transistor 116 is output. In the end, an output video signal 50 from which the synchronization signal has been removed can be obtained from the human-powered video signal 1o.

Of course, other types of circuits can be used as the S/H circuit 12 and the switch circuit 14.

<Description of Effects> As described above, according to the present invention, a synchronization signal removal circuit in which the reference level faithfully follows fluctuations in the average level of the input video signal can be realized with an extremely simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional synchronous signal removal circuit, FIG. 2 is a signal waveform diagram of each part of FIG. 1, FIG. 6 is a circuit diagram of a synchronous signal removal circuit of this embodiment, and FIG. FIG. 5 is a signal waveform diagram of another embodiment, and FIG. 6 is a detailed circuit diagram of a part of the circuit shown in FIG. In the figure, 10 is an input periodic signal, 12 is a sample hold circuit, 14 is a switch circuit, 16 is a synchronous separation circuit, and 2
0 indicates a horizontal synchronizing signal, 60 indicates a back porch pulse, 40 indicates a blanking pulse, and 50 indicates an output video signal.

Claims (1)

[Claims] A holding means for sampling a video signal at a predetermined timing and holding the sampled value, a selection means 1 for selecting one of the holding output of the holding means and the video signal, and the selection means generates a synchronization signal included in the video signal. A synchronization signal removal device comprising timing signal generation means for generating a timing signal for selecting the holding output at a timing.