JPH05292342A - Synchronizing signal separator circuit - Google Patents

Abstract

PURPOSE:To keep the rise and fall of a synchronizing signal steep by sampling a pedestal portion of a video signal and holding the sampled signal for a burst period and implementing synchronizing separation with a video signal whose burst portion is clamped. CONSTITUTION:A synchronizing signal separated by a sub synchronizing separator circuit 5 is given to a pedestal sample-and-hold pulse generating circuit 6, in which a pulse for burst signal elimination included in a video signal is generated and it is fed to a pedestal sample-and-hold circuit 8. The circuit 8 samples a signal of the pedestal portion and holds the signal to a pedestal level for a burst signal period. As a result, a video signal (b) from which the burst signal is eliminated is introduced. Then a signal c1 is fed to a synchronization tip sample-and-hold circuit 10 and a comparator circuit 11 via a pedestal clamp circuit G. The circuit 10 gives a signal c2 at a sample hold level of the SYNC tip to the circuit 11, the signal c1, c2 are compared and a synchronizing signal subject to synchronization separation is outputted to an output terminal 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal separation circuit for separating a sync signal from a video signal including a sync signal and a burst signal.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional sync signal separation circuit. In FIG. 3, a video input signal a (see FIG. 4A) supplied from an input terminal 1 is amplified by an amplifier 2 and then led to a low-pass filter (hereinafter referred to as LPF) 3 for a retrace period of the video signal. The superimposed burst signal is sufficiently attenuated and is substantially removed.

Video signal b from which burst signal is removed
₁ (see FIG. 4 (b)) is clamped by the clamp circuit 4 and then guided to the sub-synchronization separation circuit 5.
Thus, the sync signal is separated from the video signal. The separated synchronizing signal is supplied to the clamp pulse generating circuit 7, and the clamp pulse generating circuit 7 clamps the video signal at the pedestal level based on the synchronizing signal by using the clamp pulse b ₃ (FIG. 4B). (See).

The clamp pulse derived from the clamp pulse generation circuit 7 is supplied to the pedestal clamp circuit 13, and the video signal from which the burst signal supplied from the LPF 3 has been removed is clamped at the pedestal level.
Then, the video signal clamped at the pedestal level is guided to the sync chip sample and hold circuit 10 and sync chip sample and hold is performed by the sync chip sample and hold circuit 10 (b _{2 in} FIG. 4B).

The video signal clamped at the pedestal level from the pedestal clamp circuit 13 is supplied to the comparison circuit 11 together with the signal from the sync chip sample and hold circuit 10 sampled and held by the sync chip, and is synchronized by the comparison circuit 11. Output the separated signal.

[0006]

In the above conventional apparatus, the video signal is passed through the LPF to remove the burst signal superimposed in the blanking period, and the video signal from which the burst signal is removed is clamped at the pedestal level. Since the synchronization signal is separated by comparing the signal with the signal obtained by sampling and holding the sync chip of the signal, the rise and fall of the synchronization signal waveform is blunted by the video signal passing through the LPF, and synchronization of a wide frequency band is performed. There was a problem that the signals could not be separated.

[0007]

In order to solve the above problems, the present invention provides a sync signal separating circuit for separating a sync signal from a video signal including a sync signal and a burst signal,
A pedestal sample and hold pulse generating means for generating a pedestal level sample and hold signal whose phase is advanced from the burst signal superposed on the video signal, and the sample and hold signal are used to hold the burst period of the video signal to generate a burst signal. The burst signal removing means for removing the burst signal and the sync signal separating means for separating the sync signal from the video signal from which the burst signal obtained by the burst signal removing means is removed are provided.

[0008]

With the above-described structure, the pedestal sample-and-hold pulse generating means derives a pedestal-level sample-and-hold signal whose phase is advanced from the burst signal, and the sample-and-hold signal causes the burst-signal removing means to convert the burst signal of the video signal. To be removed. Then, the sync signal separating means compares the video signal from which the burst signal has been removed with the sync chip sample-and-hold signal of the video signal to separate and output the sync signal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of the present invention. Parts corresponding to those of the conventional example shown in FIG. In FIG. 1, reference numeral 6 is a pedestal sample and hold that generates a pedestal sample and hold pulse at a pedestal level for removing a burst signal superimposed in a blanking period of a video signal based on the sync signal separated by the sub sync separation circuit 5. It is a pulse generation circuit.

Reference numeral 8 is a pedestal sample and hold circuit for holding and removing the burst signal superimposed in the retrace period of the video signal at the pedestal level by the pedestal sample and hold pulse from the pedestal sample and hold pulse generating circuit 6. , 9 are pedestal clamp circuits that clamp the video signal from which the burst signal from the pedestal sample and hold circuit 8 has been removed by the clamp pulse from the clamp pulse generation circuit 7 at the pedestal level.

Since the embodiment of the present invention has the above-mentioned structure, the video input signal as shown in FIG. 2A including the negative synchronizing signal and the burst signal supplied to the input terminal 1 is amplified by the amplifier 2. After that, the burst signal passes through the LPF 3 and is further clamped by the clamp circuit 4 and guided to the sub-sync separation circuit 5, where the sync signal is separated.

The synchronization signal separated by the sub-synchronization separation circuit 5 is applied to a pedestal sample hold pulse generation circuit 6 for removing a burst signal included in a video signal based on the synchronization signal. The pedestal sample hold pulse is generated, and this pulse is supplied to the pedestal sample hold circuit 8.

In the pedestal sample and hold circuit 8,
The signal of the pedestal portion of the video signal input based on the pedestal sample hold pulse is sampled and held at the pedestal level during the burst signal. As a result, the burst portion is replaced with the pedestal level, and the video signal from which the burst signal is removed as shown in FIG. 2B is derived.

The sync signal separated by the sub sync separation circuit 5 is applied to the clamp pulse generation circuit 7 and the pedestal clamp circuit 9 receives the clamp pulse C ₃ (see FIG. 2).
(See (c)). In the pedestal clamp circuit 9, the video signal from which the burst signal as shown in FIG. 2 (b) output from the pedestal sample and hold circuit 8 is clamped at the pedestal level by the clamp pulse and the synchronous chip sample and hold circuit 10 is provided. And to the comparison circuit 11.

The sync chip sample and hold circuit 10 samples and holds the sync chip, and supplies the sample and hold level signal C ₂ (see FIG. 2C) of the sync chip to the comparison circuit 11. The comparator circuit 11 compares the signal from the synchronous chip sample and hold circuit 10 with the clamped video signal from the pedestal clamp circuit 9 and outputs the synchronously separated sync signal to the output terminal 12.

[0016]

Since the present invention has the above-mentioned structure, the pedestal portion of the video signal is sampled and held for the burst period, and the sync signal is separated from the video signal with the burst portion clamped. Since the sync signal is separated as it is, the rising and falling edges of the separated sync signal can be maintained in a steep state, and highly accurate sync separation can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of FIG.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is an operation explanatory diagram of FIG. 3.

[Explanation of symbols]

 6 Pedestal sample hold pulse generation circuit 8 Pedestal sample hold circuit 9 Pedestal clamp circuit 10 Sync tip sample hold circuit 11 Comparison circuit

Claims (1)

[Claims] 1. A sync signal separation circuit for separating a sync signal from a video signal including a sync signal and a burst signal, wherein a pedestal level sample hold signal with a phase advanced from the burst signal superimposed on the video signal is generated. Pedestal sample and hold pulse generation means,
Burst signal removing means for holding the burst period of the video signal by the sample hold signal to remove the burst signal, and a sync signal for separating the sync signal from the video signal from which the burst signal obtained by the burst signal removing means is removed. A synchronizing signal separating circuit, characterized in that it is provided with a separating means.