JP2001275014A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a video signal processor, equipped with a clamp circuit 12 and an A/D converting circuit 14, to output a digital video signal DV which always has its pedestal level PL controlled to a previously set black level BL even if an input analog video signal AV varies in pedestal level PL. SOLUTION: This processor is equipped with a detection period generating circuit 24 which generates a pedestal level detection period signal PKK according to a horizontal synchronizing signal HD synchronized with a signal AV, an error detecting circuit 26 which compares the pedestal level PL of the video signal outputted from an A/D converting circuit 14 for the period set with the signal PKK and detects an error quantity corresponding to the difference, and a level correcting circuit 28 which corrects the pedestal level PL of the video signal after A/D conversion to the black level BL according to the detected error quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit for clamping a pedestal level of an input analog video signal to a reference level, and an A / D converter for converting a video signal output from the clamp circuit into a digital video signal. The present invention relates to a video signal processing device provided with a circuit.

[0002]

2. Description of the Related Art Conventionally, a video signal processing apparatus of this type has a clamp circuit 12 and an A / D conversion circuit 14 as shown in FIG.
It was composed of The clamp circuit 12 is connected to the input terminal 10.
Pedestal level PL of analog video signal input to
Is compared with the reference level, and the operation of correcting the pedestal level PL of the input analog video signal is repeated according to the comparison result, thereby clamping the pedestal level PL of the input analog video signal to the reference level, and the A / D conversion circuit Reference numeral 14 converts the video signal output from the clamp circuit 12 into a digital video signal and outputs the digital video signal to the output terminal 16.

[0003]

However, in the conventional example shown in FIG. 4, when the pedestal level PL of the analog video signal input to the input terminal 10 fluctuates, the pedestal level of the clamped video signal is correspondingly changed. The PL also fluctuates as shown in FIG. 5A, and the pedestal level PD of the video signal after A / D conversion output from the output terminal 16 fluctuates as shown in FIG. 5B. .
Further, if the response of the clamp control in the clamp circuit 12 is delayed in order to reduce the control vibration due to the clamp control, there is a problem that it is impossible to follow the fluctuation of the pedestal level PL of the input analog video signal. On the other hand, if the response of the clamp control in the clamp circuit 12 is increased in order to reduce the control vibration due to the clamp control, there is a problem that the pedestal level PL of the output video signal is likely to vibrate due to the clamp control. FIG. 5 (a)
In (b), BL represents a desired black level.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and in a video signal processing apparatus having a clamp circuit and an A / D conversion circuit, even if the pedestal level of an input analog video signal fluctuates. It is an object of the present invention to provide a video signal processing device capable of outputting a digital video signal whose pedestal level is controlled to a preset black level.

[0005]

According to a first aspect of the present invention, there is provided a clamp circuit for clamping a pedestal level of an input analog video signal to a reference level, and converting a video signal output from the clamp circuit into a digital video signal. A video signal processing device having an A / D conversion circuit for generating a pedestal level detection period signal based on a synchronization signal synchronized with an input analog video signal; and a pedestal level of the detection period generation circuit. A during the pedestal level detection period set by the detection period signal
An error detection circuit that compares the pedestal level of the video signal output from the / D conversion circuit with a preset black level, and detects an error amount corresponding to the difference; and an error detection circuit that detects the error amount. A level correction circuit for correcting a pedestal level of a video signal output from the A / D conversion circuit and outputting the corrected video signal as an output video signal.

In the above configuration, if the pedestal level of the video signal output from the A / D conversion circuit fluctuates due to the pedestal level fluctuation of the input analog video signal, an error occurs in the pedestal level detection period set by the detection period generation circuit. A detection circuit detects an error amount corresponding to a difference between the pedestal level of the video signal after the A / D conversion and the set black level. The level correction circuit corrects the pedestal level of the video signal after the A / D conversion in accordance with the error amount, and outputs a video signal in which the video signal matches the set black level. In this manner, the pedestal level of the video signal after A / D conversion can be controlled to the set black level by digital processing, so that the response of the clamp control in the clamp circuit is made faster in order to reduce the control vibration due to the clamp control. Therefore, even when the pedestal level of the video signal after the A / D conversion varies, the pedestal level of the output video signal can be made to coincide with the set black level following this variation.

According to a second aspect of the present invention, in order to prevent the pedestal level from fluctuating due to a noise component superimposed on the video signal after the A / D conversion,
A low-pass filter for removing noise is inserted in a line for transmitting the video signal output from the / D conversion circuit to the error detection circuit.

According to a third aspect of the present invention, in the first or second aspect of the present invention, when the input analog video signal is a composite video signal, the input analog video signal is separated from the composite video signal to enable black level correction for each line. The horizontal synchronization signal is used as a synchronization signal for generating a pedestal level detection period signal by the detection period generation circuit.

According to a fourth or fifth aspect of the present invention, in the first, second or third aspect of the present invention, the pedestal level of the detection period generation circuit can be easily generated by the detection period generation circuit. The pedestal level detection period set by the detection period signal is a period of one clock of the sampling pulse of the A / D conversion circuit.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a video signal processing apparatus according to the present invention, and the same parts as those in FIG. In FIG. 1, reference numeral 10 denotes an input terminal for inputting an analog video signal AV (hereinafter, simply referred to as signal AV); 12, a clamp circuit; 14, an A / D conversion circuit;
Reference numeral 16 denotes an output terminal for outputting a digital video signal DV (hereinafter, simply referred to as signal DV). Reference numeral 20 denotes a digital circuit unique to the present invention. This digital circuit 20 includes the A / D conversion circuit 14 and the output terminal 16. Is inserted between.

The digital circuit 20 includes an LPF (low-pass filter) 22, a detection period generation circuit 24, an error detection circuit 26, and a level correction circuit 28. The LPF 22 removes a noise component superimposed on a digital video signal output from the A / D conversion circuit 14. The detection period generation circuit 24 generates a pedestal level detection period signal PKK (hereinafter simply referred to as a signal PKK) based on a horizontal synchronization signal HD (hereinafter simply referred to as a signal HD) as an example of a synchronization signal input to the terminal 30. I do. The signal HD is a signal synchronized with the signal AV. For example, when the signal AV is a composite video signal (composite video signal), it can be obtained by being separated from the signal AV by a sync separation circuit. The error detection circuit 26 compares the pedestal level PL of the video signal output from the LPF 22 with a preset black level BL during a pedestal level detection period set by the signal PKK of the detection period generation circuit 24, and compares the difference. Is detected. The black level BL is externally set via the terminal 32.
The level correction circuit 28 corrects the pedestal level PL of the video signal output from the A / D conversion circuit 14 in accordance with the detection error amount of the error detection circuit 26, and makes the pedestal level PL coincide with the black level BL. The output signal DV is output to the output terminal 16.

Next, the operation of FIG. 1 will be described with reference to FIGS. 2 and 3. For convenience of description, a case where the signal AV is a composite video signal will be described. A: First, a schematic operation will be described with reference to FIG. (1) The pedestal level PL of the signal AV input to the input terminal 10 is clamped to a reference level by the clamp circuit 12 and is converted to a digital video signal by the A / D conversion circuit 14. The output of the signal as shown in FIG. 2A from the output side is the same as in the conventional example.

(2) When a signal HD separated from the signal AV by a synchronization separation circuit (not shown) is input to a detection period generation circuit 24 via a terminal 30, the detection period generation circuit 24 generates a pedestal based on the signal HD. A signal PKK for setting the level detection period T is generated.

(3) The signal PKK generated by the detection period generation circuit 24, the A / D converted video signal from which noise has been removed by the LPF 22, and the black level BL input via the terminal 32 are used as an error detection circuit. 26, the error detection circuit 26 outputs a signal PK every line (each 1H in the figure).
A / D during the pedestal level detection period T set by K
The converted video signal is compared with the black level BL, and an error amount corresponding to the difference is detected. Specifically, as shown in FIG. 2B, when the pedestal level PL of the video signal is equal to the black level BL, a detection error amount “0” is output, and the pedestal level PL is one step lower than the black level BL. Sometimes, a detection error amount “−1” is output, and the pedestal level PL is output.
Is one level higher than the black level BL, the detection error amount “+
1 "is output. Although not shown, when the pedestal level PL is lower than the black level BL by two steps, the detection error amount “−2” is output, and the pedestal level PL is changed to the black level B.
When the level is higher than L by two steps, the detection error amount “+2” is output. Similarly, when three or more steps are low or high, the corresponding detection error amount is output.

(4) When the video signal after A / D conversion and the detection error amount from the error detection circuit 26 are input to the level correction circuit 28, the level correction circuit 28 performs A / D conversion in accordance with the detection error amount. Pedestal level PL of video signal after D conversion
Pedestal level P as shown in FIG.
The signal DV whose L is matched with the black level BL is output to the output terminal 16.
Output to As described above, the pedestal level PL of the video signal after A / D conversion is controlled by the digital processing of the digital circuit 20 so as to match the black level BL, so that the response of the clamp control in the clamp circuit 12 is made faster. Pedestal level PL of video signal after A / D conversion
Is changed, the pedestal level PL of the signal DV can be made to coincide with the black level BL by following this change.

B: Next, referring to FIG. 3, the operation of the video signal after A / D conversion when the pedestal level PL is one step lower than the black level BL as shown in FIG. 3A will be described in detail. I do. (1) When the horizontal synchronization signal of the video signal after A / D conversion and the signal in which the vicinity of the back porch is emphasized are represented as signals as shown in FIG. 3A, the signal separated by a synchronization separation circuit (not shown) HD becomes a signal as shown in FIG.
This signal is input to the detection period generation circuit 24 via the terminal 30. Then, the detection period generation circuit 24 generates a signal PKK as shown in FIG. 3C based on the signal HD.
The signal PKK is generated by the detection period generation circuit 24 so as to be a signal in which the period T in the back porch of the video signal in FIG. That is, assuming that the horizontal synchronizing signal of the video signal after A / D conversion falls at time t1 and rises at time t2, the level changes from L level to H at time t3 in the back porch after a set time Ts has elapsed from time t1.
A signal PKK that changes from the H level to the L level at time t4 when the pedestal level detection period T has elapsed from time t3. The pedestal level detection period T is set to a period of one clock of the sampling pulse of the A / D conversion circuit 14. Specifically, the period is set to one clock period of the sampling pulse or a period obtained by averaging a plurality of clock periods.

(2) During the pedestal level detection period T from the time t3 to the time t4 (that is, the period when the signal PKK is at the H level), the error detection circuit 26 performs the A / D-converted video signal removal of noise by the LPF 22. And the black level BL, and an error amount corresponding to the difference is detected. Specifically, as shown in FIG. 3D, since the pedestal level PL of the video signal is lower than the black level BL by one step, the detection error amount “−1” is output.

(3) When the video signal after A / D conversion and the detection error amount “−1” from the error detection circuit 26 are input to the level correction circuit 28, the level correction circuit 28 -1 ", the pedestal level PL of the video signal after the A / D conversion is corrected to a predetermined value, and FIG.
(D) As shown after t4, the pedestal level PL
With the black level BL. For this reason, after t4, a video signal whose pedestal level PL matches the black level BL is output from the output terminal 16 as the signal DV. That is, control is performed so that the pedestal level PL of the video signal coincides with the black level BL immediately before the start of the corresponding one-line video signal body Vm (data of the video portion).

(4) Although not shown, the pedestal level PL of the video signal after A / D conversion is one more than the black level BL.
If the level is higher, the error detection circuit 26 outputs a detection error amount “+1”, and the level correction circuit 28 lowers the pedestal level PL of the video signal after A / D conversion by a predetermined value according to the detection error amount “+1”. The pedestal level PL is made to match the black level BL. Therefore, even when the pedestal level PL is higher than the black level BL by one step, the pedestal level PL of the video signal is controlled to match the black level BL immediately before the start of the corresponding one-line video signal body Vm.

(5) If the pedestal level PL of the video signal after A / D conversion is lower than the black level BL by two or more steps,
Alternatively, even when the level is higher by two or more steps, the detection error amount output from the error detection circuit 26 has a corresponding value, and the correction amount by the level correction circuit 28 has a corresponding value. Immediately before the start of the main body Vm, the pedestal level PL of the video signal is controlled to match the black level BL.

In the above embodiment, in order to facilitate the generation of the pedestal level detection period signal by the detection period generation circuit, the pedestal level detection period set by the pedestal level detection period signal of the detection period generation circuit is A / A. D
Although the period is one clock of the sampling pulse of the conversion circuit, the present invention is not limited to this. The error detection circuit compares the pedestal level PL with the black level BL and detects an error amount corresponding to the difference. Any period is acceptable. For example, the present invention can also be used when the pedestal level detection period is a period for a plurality of clocks of a sampling pulse.

In the embodiment, when the input analog video signal is a composite video signal, it is possible to perform a correction (black level correction) for matching the pedestal level PL to the black level BL for each line. The horizontal synchronizing signal separated from the input analog video signal is used as a synchronizing signal for generating a pedestal level detection period signal in the detection period generation circuit. However, the present invention is not limited to this. It can be used for signals other than video signals, and can also be used for cases where black level correction is performed for each of a plurality of lines. The detection period generation circuit generates a pedestal level detection period signal. Can be used also when the synchronization signal is other than the horizontal synchronization signal. For example, even if the input analog video signal is a composite video signal and the synchronization signal is a horizontal synchronization signal, the detection period generation circuit generates a pedestal level detection period signal for each of a plurality of lines (for example, every two lines) based on the horizontal synchronization signal. If the input analog video signal is a composite video signal, the pedestal level PL is made to match the black level BL for each of a plurality of lines (black level correction). Can be.

In the embodiment, in order to prevent the pedestal level from fluctuating due to a noise component superimposed on the video signal after A / D conversion, the video signal output from the A / D conversion circuit is subjected to error detection. Although the case where the LPF for noise removal is inserted into the line for transmission to the circuit has been described, the present invention is not limited to this, and the present invention can also be used when the LPF for noise removal is omitted.

[0024]

According to the first aspect of the present invention, a clamp circuit and an A /
In a video signal processing apparatus having a D conversion circuit, a detection period generation circuit, an error detection circuit, and a level correction circuit are provided.
When the pedestal level of the video signal after the / D conversion varies, the error detection circuit performs the A / D conversion during the pedestal level detection period.
Pedestal level PL and black level B of video signal after conversion
An error amount corresponding to the difference of L is detected, and a level correction circuit corrects the pedestal level PL of the video signal after A / D conversion in accordance with the error amount, and outputs a video signal matched with the black level BL. With such a configuration, the pedestal level PL of the video signal after A / D conversion can be made to match the black level BL by digital processing. For this reason,
Even if the pedestal level of the A / D-converted video signal fluctuates by increasing the response of the clamp control in the clamp circuit in order to reduce the control vibration due to the clamp control, the pedestal of the output video signal follows the fluctuation. Level PL
Can be matched with a preset black level BL.

According to a second aspect of the present invention, in the first aspect of the present invention, an LPF for noise removal is inserted in a line for transmitting a video signal output from an A / D conversion circuit to an error detection circuit. It is possible to prevent the pedestal level from fluctuating due to a noise component superimposed on a subsequent video signal.

According to a third aspect of the present invention, in the first or second aspect, the input analog video signal is a composite video signal,
Since the horizontal synchronizing signal separated from the composite video signal is used as a synchronizing signal for generating a pedestal level detection period signal in the detection period generation circuit, when the input analog video signal is a composite video signal, the black level is changed for each line. Corrections can be made.

According to a fourth or fifth aspect of the present invention, in the first, second or third aspect of the present invention, the pedestal level detection period set by the pedestal level detection period signal of the detection period generation circuit is used as a sample of the A / D conversion circuit. Since the period corresponds to one clock of the activation pulse, it is possible to easily generate the pedestal level detection period signal in the detection period generation circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a video signal processing device according to the present invention.

FIG. 2 is a timing chart illustrating a schematic operation of FIG. 1;

FIG. 3 is a timing chart illustrating a detailed operation of FIG. 1;

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a timing chart for explaining the operation of FIG. 4;

[Explanation of symbols]

10 input terminal, 12 clamp circuit, 14 A /
D conversion circuit, 16 output terminal, 20 digital circuit, 22 LPF (low-pass filter), 24 detection period generation circuit, 26 error detection circuit, 28 level correction circuit, 30, 32 terminal, 1H 1 Horizontal line,
AV: analog video signal, BL: preset black level, DV: digital video signal, HD: horizontal synchronization signal, PKK: pedestal level detection period signal, PL: pedestal level, Vm: video signal body.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Makoto Ikeda 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu General Limited (reference) 5C021 PA13 PA32 PA34 PA52 PA58 PA85 SA17 XA43 XA48 XA61 YA01 YC01

Claims (5)

[Claims] An image comprising a clamp circuit for clamping a pedestal level of an input analog video signal to a reference level, and an A / D conversion circuit for converting a video signal output from the clamp circuit into a digital video signal. In the signal processing device, a detection period generation circuit for generating a pedestal level detection period signal based on a synchronization signal synchronized with the input analog video signal, and a pedestal level detection set by the pedestal level detection period signal of the detection period generation circuit An error detection circuit that compares a pedestal level of a video signal output from the A / D conversion circuit with a preset black level during a period, and detects an error amount corresponding to the difference; and an error detected by the error detection circuit. The pedestal level of the video signal output from the A / D conversion circuit is corrected according to the amount and output. A video signal processing apparatus characterized by comprising; and a level correction circuit of the image signal. 2. The video signal processing apparatus according to claim 1, wherein a low-pass filter for removing noise is inserted into a line for transmitting the video signal output from the A / D conversion circuit to the error detection circuit. 3. An input analog video signal is a composite video signal, and a horizontal synchronization signal separated from the composite video signal is used as a synchronization signal for generating a pedestal level detection period signal by a detection period generation circuit. 3. The video signal processing device according to 2. 4. A pedestal level detection period set by a pedestal level detection period signal of a detection period generation circuit,
3. The video signal processing device according to claim 1, wherein the period is one clock period of a sampling pulse of the / D conversion circuit. 5. A pedestal level detection period set by a pedestal level detection period signal of a detection period generation circuit,
4. The video signal processing device according to claim 3, wherein the period is one clock period of the sampling pulse of the / D conversion circuit.