JP2000013636A - Phase detection circuit, phase correction circuit and digital image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of power consumption due to a large sized circuit scale and the acceleration of a circuit operation which accompany because a sampling frequency becomes high in the case of using an over-sampling method. SOLUTION: Average value arithmetic circuits 40 and 41 preliminarily calculate the average value of digital video data of about a trailing edge timing of a horizontal synchronizing signal at the time of detecting the phase of digital video data including the horizontal synchronizing signal and also, position level arithmetic circuits (1) 42-1 to (7) 42-7 calculate seven pieces of position level data based on the average value, for instance, in eight position modes. And, comparators (1) 43-1 to (7) 43-7 compare the digital video data at the time of the trailing edge of the horizontal synchronizing signal with the seven pieces of position level data and a position encoder 44 encodes the comparison results DATA1 to DATA7 and makes them position data (phase information).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase detection circuit for detecting the phase of digital data including a synchronization signal, a phase correction circuit for correcting the phase, and a digital image processing apparatus using the same. The present invention relates to a phase detection circuit for detecting a fall position on an axis, a phase correction circuit for correcting the phase of digital data based on the detection information, and a digital image processing apparatus using the same.

[0002]

2. Description of the Related Art In a digital image processing apparatus which performs A / D conversion of an analog video signal of an NTSC system, a PAL system or the like and digitally processes the analog video signal, the analog video signal is A / D converted.
At the time of conversion, if the sampling frequency is an integral multiple of the frequency of the horizontal synchronization signal included in the analog video signal (hereinafter, referred to as horizontal synchronization frequency), the horizontal arrangement of digital data obtained by A / D conversion is as follows. 14 can be obtained correctly.

However, the horizontal synchronizing signal of an analog video signal obtained from a video reproducing system or the like has a slight frequency shift. When the analog video signal is A / D-converted, the original time axis is shifted as shown in FIG. Since the position is slightly deviated from the upper position, image distortion such as a vertical line being an oblique line appears. Therefore, signal processing within one clock, such as detecting the falling position on the time axis of the horizontal synchronization signal and using the position information to shift the apparent time axis position of the digital video signal (phase correction), is performed. Thus, the image distortion is corrected as shown in FIG.

That is, as shown in FIG. 17, the falling position (phase) on the time axis of the horizontal synchronizing signal separated in synchronization by the analog synchronization separating circuit 101 is determined by the phase detecting circuit 102.
In the time axis correction circuit 104, the time axis of the video signal is detected using the phase information detected by the phase detection circuit 102. The above position correction, that is, the phase correction is performed.

The phase detection circuit 102 uses the oversampling method of sampling the horizontal synchronizing signal with a sampling clock having, for example, twice the frequency of the master clock, as shown in FIG. The fall position on the axis is detected. In this way, by increasing the frequency of the sampling clock (sampling frequency) with respect to the master clock and performing oversampling, more detailed information on the falling position of the horizontal synchronization signal can be obtained.

[0006]

However, in the conventional phase detection circuit 102 using the oversampling method, since the sampling frequency is increased, the power consumption is increased due to the accompanying increase in the circuit size and the speeding up of the circuit operation. In order to increase the oversampling and to realize oversampling, an analog sync separation circuit 101 for separating a horizontal sync signal from an analog video signal is connected to a phase detection circuit
There is a problem that it needs to be provided in the former stage of 2.

Further, since the phase information obtained by sampling can be obtained only by a digital amount instead of an analog amount, if more detailed information of the falling position is to be obtained, the sampling frequency must be set higher. There was no way. However, when the present invention is applied to a video signal having a high horizontal synchronization frequency such as a high definition signal (horizontal synchronization frequency = 33.75 kHz), it is expected that the frequency of the master clock will be high, so that the sampling frequency cannot be set high. And so on.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to accurately detect the phase of digital data including a synchronization signal without using an oversampling method. It is an object of the present invention to provide a phase detection circuit, a phase correction circuit capable of accurately correcting the phase of digital data based on the detection information, and a digital image processing device using the same.

[0009]

A phase detection circuit according to the present invention is a phase detection circuit for detecting the phase of digital data including a synchronization signal, wherein the phase detection circuit detects a phase of digital data before and after a fall timing of the synchronization signal. Average value calculating means for obtaining an average value, position level calculating means for obtaining a plurality of position level data based on the average value obtained by the average value calculating means, and a plurality of positions obtained by the position level calculating means. A phase information generating means for comparing the level data with the digital data at the falling timing of the synchronization signal and outputting the result of the comparison as phase information is provided.

A phase correction circuit according to the present invention comprises: a phase detection circuit for detecting a phase of digital data including a synchronization signal;
A time axis correction circuit for correcting the time axis of the digital data based on the detection information of the phase detection circuit, wherein the phase detection circuit having the above configuration is used as the phase detection circuit.

A digital image processing apparatus according to the present invention comprises a phase detection circuit for detecting the phase of digital video data including a horizontal synchronizing signal, and a phase correction for correcting the phase of digital video data based on information detected by the phase detection circuit. And a circuit using the phase detection circuit having the above configuration as the phase detection circuit.

In the phase detection circuit, the phase correction circuit or the digital image processing apparatus using them, when detecting the phase of the digital data including the synchronization signal serving as a reference on the time axis, the rising edge of the synchronization signal is determined in advance. An average value of the digital data before and after the falling timing is obtained for a predetermined period, and a plurality of position level data are obtained based on the average value. Then, the plurality of position level data is compared with the digital data at the time when the synchronization signal falls, and the comparison result is used as phase information. That is,
By detecting the phase from the digital data, the falling position on the time axis of the synchronization signal, that is, the phase, is detected without performing oversampling.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an input stage of a digital image processing apparatus according to the present invention. The digital image processing device according to the present invention may be a digital television or a digital printer.

In FIG. 1, a luminance signal of an analog composite video signal input to an input terminal 11 or a luminance signal of a separate video signal input to an input terminal 12 is selectively taken in by a selector 13, and an AGC (Automatic Video Signal).
Gain Control) circuit 14. Here, the composite video signal refers to a signal in which all of the luminance (Y) signal, the color (C) signal, and the synchronization signal are combined.

The AGC circuit 14 outputs a luminance signal of an analog composite video signal or a separate video signal,
After the signal is amplified to a signal level suitable for A / D conversion by the A / D converter 17 at the subsequent stage, the signal is supplied to the clamp circuit 16 via the low-pass filter (LPF) 15. Clamp circuit 16
Supplies a signal to the A / D converter 17 after performing a clamp process on a sync tip (or pedestal) portion.

Here, the clamp processing of the sync tip means a processing of clamping the tip voltage of the synchronization signal to a certain constant voltage. In addition, the pedestal clamping process means that the pedestal level in the video signal is a reference level indicating the brightness. It refers to the process of clamping so that

The digital data A / D converted by the A / D converter 17 is supplied to a sync separation circuit 19 and a phase detection circuit 20 via a low-pass filter 18 and
It is also supplied directly to the Y / C separation circuit 21. The low-pass filter 18 is provided to prevent erroneous detection of a synchronization signal due to a burst signal portion, and is 1 MHz, -6d
It has about B characteristics. The synchronization separation circuit 19 separates a horizontal synchronization signal and a vertical synchronization signal from a luminance signal of the composite video signal or the separate video signal and supplies the horizontal synchronization signal and the vertical synchronization signal to a subsequent signal processing system (not shown). It is also supplied to the circuit 20.

The phase detecting circuit 20 detects a falling position (phase) on the time axis of the horizontal synchronizing signal, and a specific configuration thereof will be described later in detail.
The Y / C separation circuit 21 separates the luminance signal and the chrominance signal from the composite video signal, supplies the luminance signal to the time axis correction circuit 22, and supplies the chrominance signal to the selector 23 as one input. The luminance signal of the separate video signal is supplied to the time axis correction circuit 22 via the Y / C separation circuit 21 as it is. The time axis correction circuit 22 corrects the time axis of the luminance signal based on the position information (phase information) given from the phase detection circuit 20.

On the other hand, the color signal of the separate video signal input to the input terminal 12 passes through the low-pass filter 24, is A / D-converted by the A / D converter 25, and becomes the other input of the selector 23. The selector 23 is the selector 1
3 in conjunction with the Y / C separation circuit 21
Either the color signal separated by the above or the color signal of the separate video signal is supplied to the color demodulation circuit 26. The color demodulation circuit 26 demodulates the color signal and outputs the two color difference signals Cr and C.
It is supplied to the subsequent signal processing system as b.

Next, the principle of phase detection by the phase detection circuit 20 will be described. FIG. 2A shows the digital video signal LPFou that has passed through the low-pass filter 18 of FIG.
t, master clock MCK and horizontal synchronizing signal Hsy
nc, and FIG. 7B shows a waveform obtained by enlarging the horizontal synchronizing signal portion. As is clear from FIG. 3B, the falling portion of the horizontal synchronization signal Hsync has a sufficiently reduced waveform by passing through the low-pass filter 18.

In the sync separation circuit 19 shown in FIG. 1, the sync separation is performed at a level of a pedestal of a video signal and a half of a sync chip. As a result, a horizontal synchronization signal Hsync as shown in the waveform diagram of FIG. 2 is obtained. Horizontal synchronization signal Hsyn
Since c changes when it becomes less than half of the pedestal and the sync chip, as shown in FIG. 3, if the clock synchronization signal system is used, even if the same horizontal synchronization signal falls, the video signal and Has a difference (shift) on the time axis.

Now, focusing on the output waveform of the low-pass filter 18, as shown in FIG. 4, if the digital data at the falling timing of the horizontal synchronization signal Hsync when there is a jitter within one clock is b, The data b takes a value within a range from the minimum value b _min to the maximum value b _max . The slope of the output waveform of the low-pass filter 18 is constant,
Further, if the video signal is a slight shift with respect to the master clock MCK and is not a random shift, the value of the point b is
It approaches the center value b _cen . Similarly, the points a and c also approach the center values a _cen and c _cen .

As shown in FIG. 5, the horizontal synchronizing signal Hsyn
Since the value at point b when c falls is in the range from the minimum value b _min to the maximum value b _max , the maximum value b _max and the minimum value b
For example, the interval between _min is divided into eight (8 position mode), and the value of the point b when the horizontal synchronization signal Hsync falls, is the phase shift between the video signal and the horizontal synchronization signal, that is, the time axis of the horizontal synchronization signal with respect to the video signal. The shift of the upper falling position can be detected.

However, since the minimum value b _min and the maximum value b _max when the horizontal synchronizing signal Hsync falls are hard to be obtained, as shown in FIG. 6, b is calculated by using the center values a _cen and c _cen. Try to find the range that a point can take. Note that the center values a _cen and c _cen can be obtained by averaging long time values at the points a and c. A specific example thereof will be described later.

FIG. 7 is a block diagram showing one embodiment of the phase detection circuit 20 according to the present invention, which is constructed based on the above-described principle of phase detection. FIG. 8 is a timing chart of signals (a) to (h) of each part of the circuit of FIG. The phase detection circuit 20 receives the digital video data that has passed through the low-pass filter 18 of FIG. 1 and a digital horizontal synchronizing signal that is correctly synchronized and separated at a half level of the horizontal synchronizing signal.

First, the input digital video data (a) is sequentially delayed by two cascade-connected delay elements 31 and 32. The delay elements 31 and 32 delay the digital video data (a) by one system clock. As a result, as the output data (d) of the delay element 32 and the output data (c) of the delay element 31, that is, the input data of the delay element 32 and the input data (a) of the delay element 31, as shown in the timing chart of FIG. Then, data having different timings for each clock is generated.

The output data (d) of the delay element 32
Is the output data (c) of the delay element 31 that is delayed by one clock from the flip-flop (FF) 33, and the input data of the delay element 31 that is further delayed by one clock from the flip-flop 34 (A) is supplied to each flip-flop 35.

On the other hand, the falling edge of the digital horizontal synchronizing signal (b) is detected by the falling edge detecting circuit 36.
The falling detection circuit 36 includes an inverter 37 for inverting the digital horizontal synchronization signal (b), a delay element 38 for delaying the digital horizontal synchronization signal (b) by one system clock, an inverter 37 and the delay element 3
And an AND gate 39 having each of eight outputs as two inputs, and generates a pulse (h) as an output of the AND gate 36 at the falling timing of the digital horizontal synchronizing signal.

This timing pulse (h) is applied to flip-flops 33, 34 and 35 as a latch pulse. In response to the timing pulse (h), the flip-flops 33, 34, and 35 output the output data (d) of the delay element 32, the output data (c) of the delay element 31, and the input data (a) of the delay element 31, That is, digital video data having different timings for each clock is latched. As a result, the digital video data (e) before and after the synchronous separation of the line is stored in the flip-flops 33, 34, and 35.
(F) and (g) can be retained.

The digital video data (e) latched by the flip-flop 33 is supplied to the average value calculation circuit 40, and the digital video data (g) latched by the flip-flop 35 is supplied to the average value calculation circuit 41. The average value calculation circuits 40 and 41 are circuits for calculating an average value of digital video data for a long time, for example, an average value for a period corresponding to 256 lines. FIG. 9 shows an example of the configuration of the average value calculation circuits 40 and 41.

Each of these average value calculation circuits 40 and 41 has an adder 51, a flip-flop 52, a multiplier 53 and a flip-flop 54. In such a configuration, the adder 51 adds the input video data and the output data of the flip-flop 52 and provides the result to the flip-flop 52. The flip-flop 52 accumulates data for 256 lines in response to the enable 1 signal generated once for each line, and is reset by the enable 2 signal generated once for each field.

In this way, the digital video data integrated in the flip-flop 52 over 256 lines is multiplied by 1/256 in the multiplier 53 in the next stage, and is further vertically synchronized in the flip-flop 54 based on the enable 2 signal. By latching at the timing of the falling of the signal, the average value of one field is obtained. FIG. 10 shows a timing relationship between the signals of the enable signals 1 and 2.

Each of the average values obtained by the average value arithmetic circuits 40 and 41 is, for example, in the 8-position mode, the above-mentioned central values a _cen and c _cen as the seven position level arithmetic circuits 42-1 to 4c. It is supplied to each of the circuits 42-7. The position level calculation circuit 42-1 to the position level calculation circuit 42-7 are provided at a subsequent stage for comparing with the output data (f) of the flip-flop 34, that is, the position data of the falling position on the time axis of the horizontal synchronization signal. This is a circuit for obtaining seven position level data.

Here, the position level calculation circuit 42-1 will be described as an example.
In FIG. 6, the position level data on the maximum value side when the area between the maximum value b _max and the minimum value b _min is divided into, for example, eight, ie, (11a _cen + 5c _cen ) / 16 = ((8+
An arithmetic process for calculating 2 + 1) a _cen + (4 + 1) c _cen ) / 16 is performed. FIG. 11 shows an example of the configuration of the position level calculation circuit 42-1.

As is apparent from FIG. 11, the position level calculation circuit 42-1 includes a 3-bit shifter 61 for _obtaining 8 (= 2 ³ ) a _cen and a 1-bit shifter 62 for _obtaining 2 (= 2 ¹ ) a _cen. , A 2-bit shifter 63 for obtaining 4 (= 2 ² ) c _cen , an adder 64 for adding the outputs of the bit shifters 61 to 63 and the data a _cen and c _cen, and an addition output of the adder 64 by 1 / And a multiplier 65 for multiplying by 16.

Similarly, each of the other position level calculation circuits 42-2 to 42-7 has a circuit configuration including a combination of a bit shifter and an adder. According to this, the position level calculation circuits 42-1 to 42-7 can be configured very easily by hardware.

The seven position level data obtained by the position level calculation circuits 42-1 to 42-7 are supplied to the seven comparators 43-1 to 43-7 as comparison reference inputs. Given. The comparators 43-1 to 43-7 output data (f) of the flip-flop 34,
That is, the position data at the falling position on the time axis of the horizontal synchronizing signal is used as a common comparison input, and when the position data is smaller than the position level data, the output becomes “H” level.

Each of the comparison data DATA1 to DATA7 of the comparators 43-1 to 43-7 is transmitted to the position encoder 44.
Supplied to The position encoder 44 includes a comparator 43-1.
~ Each comparison data DATA1 to DATA of the comparator 43-7
7 is a circuit for encoding information (position data) of the falling position on the time axis of the horizontal synchronization signal. The input data DATA of this position encoder 44
FIG. 12 shows the relationship between the combination of 1 to DATA7 and the encode output. FIG. 13 shows the output of the position encoder 44.

As described above, when detecting the phase of the digital video data including the horizontal synchronizing signal, the average values of the digital video data before and after the fall timing of the horizontal synchronizing signal are previously calculated by the average value calculation circuits 40 and 41. At the same time, in the 8-position mode, for example, seven position level data are obtained by the position level calculation circuits 42-1 to 42-7 based on the average value.

Then, the digital video data at the time of the falling edge of the horizontal synchronizing signal is compared with these seven position level data in comparators 43-1 to 43-7, and these comparison results DATA1 to DATA7 are compared with the position encoder. Since the position data (phase information) is encoded by 44, the falling position (phase) on the time axis of the horizontal synchronization signal can be obtained without using the oversampling method.
Can be accurately detected.

As described above, since oversampling becomes unnecessary, power consumption can be reduced as compared with the prior art using the oversampling method, and at the same time, a baseband system having a higher frequency such as a high-definition signal can be used. Response is possible. Further, since the phase detection by the analog horizontal synchronizing signal is unnecessary, the analog synchronizing separation circuit used in the prior art is unnecessary, and the power consumption can be further reduced accordingly.

In the above embodiment, the case where the present invention is applied to the input stage of a digital image processing device such as a digital television or a digital printer has been described. However, the present invention is not limited to this, and is not limited to this. It can handle digital data including a synchronization signal (reference signal) serving as a reference and can be applied to all devices.

[0044]

As described above, according to the present invention,
By detecting the phase from the digital data, the falling position on the time axis of the synchronization signal can be accurately detected without using the oversampling method. It is also possible to support baseband systems with high performance.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of an input stage of a digital image processing device according to the present invention.

FIGS. 2A and 2B are waveform diagrams of signals. FIG. 2A shows waveforms of digital video data LPFout, a master clock MCK and a horizontal synchronization signal Hsync that have passed through a low-pass filter, and FIG. 2B shows an enlarged waveform of a horizontal synchronization signal portion. Are respectively shown.

FIG. 3 is a waveform diagram showing a shift between a horizontal synchronization signal and a video signal.

FIG. 4 is a diagram for explaining the principle of phase detection.

FIG. 5 is an explanatory diagram for detecting a phase shift based on a value of a point b.

FIG. 6 is an explanatory diagram for obtaining a value at point b from points a and c.

FIG. 7 is a block diagram illustrating an embodiment of a phase detection circuit according to the present invention.

FIG. 8 is a timing chart of signals of each unit of the phase detection circuit.

FIG. 9 is a block diagram illustrating an example of a configuration of an average value calculation circuit.

FIG. 10 is a timing chart of each signal of enable 1 and 2;

FIG. 11 is a block diagram illustrating an example of a configuration of a position level operation circuit.

FIG. 12 is a diagram illustrating a relationship between a combination of input data of a position encoder and an encoded output.

FIG. 13 is a waveform chart showing an output of the position encoder.

FIG. 14 is a diagram showing the horizontal arrangement of digital data when the sampling frequency is an integral multiple of the horizontal synchronization frequency.

FIG. 15 is a diagram showing the horizontal arrangement of digital data when the sampling frequency is not an integral multiple of the horizontal synchronization frequency.

FIG. 16 is a diagram showing image outputs when horizontal jitter is included (A) and when phase correction is performed (B).

FIG. 17 is a block diagram showing a conventional example.

FIG. 18 is a timing chart of phase detection by the oversampling method.

[Explanation of symbols]

13, 23 ... selector, 15, 18, 24 ... low-pass filter (LPF), 17, 25 ... A / D converter, 19 ...
Synchronization separation circuit, 20: phase detection circuit, 21: Y / C separation circuit, 22: time axis correction circuit, 26: color demodulation circuit, 3
1, 32, 38 ... delay elements, 33 to 35, 52, 54 ...
Flip-flops (FF), 40, 41: average value calculation circuit, 42-1 to 42-7: position level calculation circuit, 43-1 to 4-4
3-7: comparator, 44: position encoder, 51: adder,
53, 65: multipliers, 61 to 63: bit shifters, 6
4 ... Adder

Claims (11)

[Claims] 1. A phase detection circuit for detecting a phase of digital data including a synchronization signal, comprising: an average value calculating means for calculating an average value of the digital data for a predetermined period before and after a fall timing of the synchronization signal; Position level calculating means for obtaining a plurality of position level data based on the average value obtained by the average value calculating means; and a plurality of position level data obtained by the position level calculating means and a fall timing of the synchronization signal. And phase information generating means for comparing the digital data with the digital data and outputting the comparison result as phase information. 2. The digital data including the synchronization signal,
2. The phase detection circuit according to claim 1, wherein the phase detection circuit is digital video data including a horizontal synchronization signal. 3. The average value calculating means includes means for integrating the digital video data for n (n is a natural number) lines for each field, and means for multiplying the integrated result by 1 / n to obtain an average value. 3. The phase detection circuit according to claim 2, wherein each of the digital video data before and after the falling timing of the synchronization signal is provided. 4. The plurality of position level data is obtained by dividing m (m is a natural number) between a maximum value and a minimum value of a value of the digital video data at a fall timing of the horizontal synchronization signal. -1 position level data, wherein the position level calculating means comprises m-1 means for obtaining the m-1 position level data based on the average value obtained by the average value calculating means. The phase detection circuit according to claim 3, wherein: 5. The phase detection circuit according to claim 4, wherein said m-1 means comprise a combination of a bit shifter and an adder. 6. The phase information generating means includes: m-1 comparing means for comparing each of the m-1 position level data with the digital video data at the falling timing of the horizontal synchronization signal; 5. The phase detection circuit according to claim 4, further comprising encoding means for encoding each comparison result of said m-1 comparison means and outputting the result as said phase information. 7. A phase comprising: a phase detection circuit for detecting a phase of digital data including a synchronization signal; and a time axis correction circuit for correcting a time axis of the digital data based on detection information of the phase detection circuit. A correction circuit, wherein the phase detection circuit includes: an average value calculation unit that calculates an average value of the digital data for a predetermined period before and after a fall timing of the synchronization signal; and an average value obtained by the average value calculation unit. Position level calculating means for obtaining a plurality of position level data based on the plurality of position level data, and comparing the plurality of position level data obtained by the position level calculating means with the digital data at the falling timing of the synchronization signal, A phase correction circuit comprising: a phase information generating unit that outputs a result as phase information. 8. The digital data including the synchronization signal,
8. The phase correction circuit according to claim 7, wherein the phase correction circuit is digital video data including a horizontal synchronization signal. 9. The apparatus according to claim 8, further comprising: means for separating a luminance signal component and a color signal component from the digital video data, wherein the time axis correction circuit corrects a time axis of the luminance signal component. The described phase correction circuit. 10. A digital device comprising: a phase detection circuit for detecting a phase of digital video data including a horizontal synchronization signal; and a phase correction circuit for correcting the phase of the digital video data based on detection information of the phase detection circuit. In the image processing apparatus, the phase detection circuit is obtained by an average value calculation unit that obtains an average value of the digital video data for a predetermined period before and after a fall timing of the horizontal synchronization signal, and is obtained by the average value calculation unit. Position level calculating means for obtaining a plurality of position level data based on the average value obtained, and the plurality of position level data obtained by the position level calculating means and the digital video data at the falling timing of the horizontal synchronization signal. Phase information generating means for comparing and outputting the comparison result as phase information Digital image processing apparatus. 11. The apparatus according to claim 10, further comprising means for separating a luminance signal component and a chrominance signal component from the digital video data, wherein the phase correction circuit corrects the phase of the luminance signal component. Digital image processing device.