JP3384693B2 - Image data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus for separating an image signal including a sync signal into a luminance component and a color component and generating luminance data and color data by digital signal processing.

[0002]

2. Description of the Related Art An image signal for reproducing a color image on a monitor screen includes a brightness component representing the shade of the image, a color component representing the color, and a synchronization component determining various timings. These respective components are separated from each other by utilizing the difference in amplitude, the shift in phase, etc., and are individually processed as a luminance signal, a color signal and various synchronization signals. In each signal processing, in recent years, there is a tendency to be digitalized in order to make adjustments easy by making it less susceptible to temperature changes and noise.

FIG. 9 is a block diagram showing the configuration of an image data processing device that employs digital signal processing, and FIG.
It is a wave form diagram of the signal handled by each part. The Y / C separation circuit 1 takes in an image signal i including a luminance component and a color component, separates the image signal i into each component by utilizing the phase difference of the color components, and generates a luminance signal y and a color signal c. For example, in the case of the NTSC system, the image signal i is shifted by one horizontal scanning period and added to each other to extract the luminance component, and the color component is extracted from the difference between them. The amplifier 2 is a 2-channel high frequency amplifier that operates in the video frequency band, and amplifies the luminance signal y and the color signal c to predetermined amplitudes. The A / D conversion circuit 3 uses the amplified luminance signal y and color signal c output from the amplifier 2 as a reference clock C.
Quantization in response to K, luminance data Y0 and color data C0
To generate.

The synchronous detection circuit 4 takes out the synchronous component of the image signal i and generates a horizontal synchronous signal HS and a vertical synchronous signal VS. In this synchronous detection, the mixed component of horizontal synchronization and vertical synchronization is first extracted by using the difference in amplitude between the synchronization component and other signal components, and then the horizontal synchronization component and vertical synchronization are utilized by using the difference in frequency. Separated into components. The burst detection circuit 5 selectively extracts the color synchronization signal (burst signal) CB that determines the phase of the color component from the image signal i. That is, the burst signal CB is a fixed pattern signal having a predetermined frequency (for example, 3.58 MHz),
It is superimposed at a predetermined position of the image signal i, for example, at the beginning of each horizontal scanning period. Therefore, the burst signal CB can be obtained by selectively extracting the specific period at the beginning of each horizontal scanning period of the image signal i. The phase locked loop (PLL) 9 generates a reference clock CK with the burst signal CB as a reference. For example, in the NTSC system, the PLL 6 is configured such that a clock obtained by dividing the reference clock CK by 4 is synchronized with the burst signal CB,
14.32 for a burst signal CB of 3.58 MHz
A MHz reference clock CK is generated. Usually this one
The 4.32 MHz reference clock CK serves as a color subcarrier used for modulation of color components.

The timing signal generating circuit 7 is composed of a counter which operates by a reference clock CK, and divides the reference clock CK based on a horizontal synchronizing signal HS and a vertical synchronizing signal VS to obtain a horizontal scanning period and a vertical scanning period. Generates various timing signals. For example, in the case of the NTSC system, the horizontal timing signal HD is taken out every time the counter reset by the horizontal synchronization signal HS counts 910 the reference clock CK, and the counter reset by the vertical synchronization signal VS outputs the horizontal timing signal HD by 525.
It is configured such that the vertical timing signal VD is taken out every time the number of / 2 is counted.

The image data processing circuit 8 fetches the brightness data Y0 and the color data C0 output from the A / D conversion circuit 3 for each data, and performs a predetermined signal processing to obtain new brightness data Y and brightness components. And color difference data U and V representing the difference between the red component and the blue component. In the generation process of the luminance data Y, an aperture process for enhancing the contour and contrast of the subject, a gamma correction for correcting visual non-linearity with respect to the luminance level, and the like are performed. Then, in the generation processing of the color difference data U and V, first, the demodulation of the color components subjected to the balanced modulation and the adjustment of the white balance are performed, and then the luminance component is subtracted from each color component. The image data processing circuit 8 processes the luminance data Y0 and the color data C0 at a common timing, whereby the luminance data Y and the color difference data U and V are processed.
Are grouped at the same timing for each data and sent to the recording system or the reproducing system.

[0007]

In the image signal i, the horizontal synchronizing signal HS that determines the timing of the luminance component and the burst signal CB that determines the timing of the color component are asynchronous. Further, the horizontal synchronizing signal HS has a longer cycle than the burst signal CB, and when the image signal i is supplied from a reproducing device such as a video tape recorder, it is easily affected by the jitter generated in the reproducing device. Therefore, from the horizontal synchronization signal HS and the reference clock CK to the horizontal timing signal HD
In the timing signal generation circuit 7 for generating the
It may shift by several cycles. For example, in the NTSC system, where the original cycle of the horizontal timing signal HD should be 910 clocks of the reference clock CK, 908
It may fluctuate in the range of ˜912 clocks. When the cycle of the horizontal timing signal HD is shifted in this way, the phase of the color data C is also shifted from the luminance data Y, which causes a problem that the contrast is lowered on the screen and the contour of the object is disturbed.

Therefore, the present invention is based on the horizontal timing signal HD.
It is an object of the present invention to correct the deviation of the cycle of to prevent deterioration of the image quality of the playback screen.

[0009]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it represents the luminance information of a plurality of pixels forming a screen and a horizontal synchronizing signal. Luminance data that continues in line units in synchronization with
In an image data processing device that processes color data representing color information corresponding to the luminance data in parallel, a phase-locked loop that generates a reference clock of a constant cycle in synchronization with a color synchronization signal that obtains synchronization of color information. , Measuring the cycle of the reference clock, generating first data representing the cycle, measuring the phase difference of the horizontal synchronizing signal with respect to the reference clock, and generating second data representing the phase difference. A correction data generation circuit that measures the period of the horizontal synchronizing signal based on the reference clock and generates third data indicating a deviation from the predetermined reference period; A luminance data correction circuit that generates corrected luminance data by combining at a rate determined based on the first and second data, and the reference clock according to the third data. In response to the horizontal synchronizing signal by dividing it by the timing lies in comprising a timing signal generating circuit for generating a timing signal of the horizontal scanning period, a.

By determining the cycle of the horizontal synchronizing signal and correcting the deviation of the cycle in the process of generating the timing signal,
Even if the period of the horizontal synchronizing signal is shifted due to the jitter included in the image signal, the phase shift between the luminance data and the color data is eliminated, and the screen disorder is less likely to appear on the playback screen.

[0011]

1 is a block diagram showing a first embodiment of an image data processing apparatus of the present invention, and FIG. 2 is a timing chart for explaining the operation of the main part thereof. The image data processing device includes a Y / C separation circuit 11, an amplifier 12, and an A
/ D conversion circuit 13, synchronous detection circuit 14, burst detection circuit 15, phase lock loop 16, correction data generation circuit 1
7, a luminance data correction circuit 18, a timing signal generation circuit 19 and an image data processing circuit 20.

The Y / C separation circuit 11 takes in the image signal i, separates the luminance component and the color component into a luminance signal y and a color signal c. The amplifier 12 amplifies the separated luminance signal y and color signal c to a predetermined amplitude. The A / D conversion circuit 13 quantizes the amplified luminance signal y and chrominance signal c in a constant cycle to generate luminance data Y0 and color data C0. This Y / C separation circuit 11 and amplifier 12
The A / D conversion circuit 13 has the same configuration as that shown in FIG.

The synchronous detection circuit 14 takes out the synchronous component of the image signal i and generates a horizontal synchronous signal HS and a vertical synchronous signal VS which determine the timing of horizontal scanning and vertical scanning. The burst detection circuit 15 selectively extracts a color synchronization signal (burst signal) CB that is superimposed on a specific period of the image signal i and determines the phase of the color component. The phase lock loop (PLL) 16 generates a reference clock CK having a constant period with the burst signal CB as a reference. This reference clock CK is used as a sampling clock in the A / D conversion circuit 13, and in the case of the NTSC system, it is 4
The frequency is divided and synchronized with the burst signal CB.

The correction data generation circuit 17 detects the period Ta from the rise of the reference clock CK to the fall of the horizontal synchronizing signal HS and the period Tb of the reference clock CK,
First data Da representing the period Ta and second data Da representing the period Tb
The data Db of each is output. At the same time, the correction data generation circuit 17 measures the cycle of the horizontal synchronizing signal HS by using the reference clock CK, and the third data Dc indicating how many cycles the cycle of the reference clock CK deviates from the reference cycle. Is output. The brightness data correction circuit 18 corrects the image data Y0 on a data-by-data basis based on the first and second data Da and Db supplied from the correction data generation circuit 17, and outputs the corrected image data Y1. This correction processing is configured to generate new image data Y1 (n) by performing an operation according to the following equation on continuous image data Y0 (n).

[0015]

[Equation 1]

That is, as shown in FIG. 2, the reference clock C
When the horizontal synchronizing signal HS deviates from K by the period Ta, the A / D conversion circuit 13 should be operated by the sampling clock CK ′ synchronized with the horizontal synchronizing signal HS. Therefore, the image data Y1 (n) to be obtained by the original reference clock CK 'is a certain image data Y0 (n).
And the previous image data Y0 (n-1) are synthesized.
The composition ratio at that time is Db−Da: D according to the first data Da (period Ta) and the second data Db (cycle Tb).
Set to a.

The timing signal generation circuit 19 has a counter for counting the reference clock CK and a decoder for decoding the count value of the counter, and the synchronous detection circuit 14
Vertical sync signal VS and horizontal sync signal HS extracted by
The vertical timing signal VD and the horizontal timing signal HD are generated based on This timing signal generation circuit 19
Is composed of a counter that operates in a vertical scanning period and a horizontal scanning period. At this time, the timing signal generating circuit 19 outputs the third signal output from the correction data generating circuit 17.
The generation timing of the horizontal timing signal HD is changed in units of one clock based on the data D3. For example, when the correction data generation circuit 17 determines the cycle of the horizontal synchronizing signal HS and it is determined that the reference clock CK is one cycle shorter than a predetermined reference cycle, the decoder that generates the horizontal timing signal HD The decode value is lowered by one and the cycle of the horizontal timing signal HD is set shorter by one clock period. Therefore, even if the cycle of the horizontal synchronizing signal HS extracted from the image signal i is deviated due to the influence of the jitter, the timing signal generation circuit 19 changes the timing of generation of the horizontal timing signal HD so as to match the deviation. .

The image data processing circuit 20 takes in the brightness data Y1 output from the brightness data correction circuit 18 and the color data C0 output from the A / D conversion circuit 13 for each data and performs a predetermined signal processing. New brightness data Y
Also, color difference data U, V representing the difference between the luminance component and the red component or the blue component is generated. The image data processing circuit 20 has the same configuration as the image data processing circuit 8 of FIG. 9, and aperture processing and gamma correction are performed in the generation processing of the luminance data Y, and demodulation and demodulation are performed in the generation processing of the color difference data U / V. White balance adjustment is performed. In the image data processing circuit 20, since the A / D conversion circuit 13 operates at the same timing, the input luminance data Y1 and the color data C0 have the same timing, and it is not necessary to adjust the timing.

According to the above configuration, the luminance data correction circuit 18 corrects the error in the luminance data Y0 due to the phase difference between the horizontal synchronizing signal HS and the burst signal CB, so that the optimum luminance data corresponding to the color data C0 is corrected. Y1 can be obtained. Therefore, the color data C0 for the luminance data Y0
Is eliminated, and the disturbance of the contour on the reproduction screen is prevented.

FIG. 3 is a block diagram showing a configuration example of the brightness data correction circuit 18. The latch 21 takes in the image data Y0 (n) that is continuously input according to the reference clock CK for each data, holds it for one clock period, and then outputs it at the timing according to the reference clock CK. The first multiplier 22 performs the operation of the second term on the right side of the equation (1), and the image data Y0 input from the A / D conversion circuit 13
For (n), the first obtained from the correction data generation circuit 17
And the coefficient Da / Db based on the second data Da, Db. The second multiplier 23 performs the operation of the first term on the right side of the equation (1), and corrects the previous image data Y0 (n-1) output from the latch 21 with the correction data generation circuit. 17
The coefficient 1-Da / Db based on the first and second data Da and Db obtained from Then, the adder 24 adds the multiplication results output from the first and second multipliers 22 and 23 to each other. As a result, the calculation according to the equation (1) is executed, and the reference clock CK and the horizontal synchronization signal H
New image data Y1 (n) in which the error due to the phase difference from S is corrected is output.

FIG. 4 is a block diagram showing the configuration of the correction data generating circuit 17, and FIG. 5 is a timing chart for explaining the operation thereof. In this figure, the horizontal synchronization signal H
The figure shows a case where the deviation of the cycle of S is determined within one cycle of the reference clock CK, and the phase difference between the reference clock CK and the horizontal synchronization signal HS is determined in eight steps. Counter 2
Reference numeral 5 counts the reference clock CK, and outputs three types of pulses C1 to C3 that are raised for one clock period when a predetermined number is counted. The pulse C2 is raised only for one clock period when the counter 25 reaches a count value corresponding to the cycle ratio of the reference clock CK and the horizontal synchronizing signal HS, and the pulses C1 and C3 are the pulse C2 raised. 1 clock period before and after the start. For example, when complying with the NTSC system, the frequency of the reference clock CK becomes 14.32 MHz, and when the reference clock CK is counted 910, the pulse C2
Is configured to launch. This counter 25
It is configured to be reset at the trailing edge of the horizontal synchronizing signal HS and repeat counting, and when the period of the horizontal synchronizing signal HS is short, the pulse C2 or C3 may not rise.

The cycle determination circuit 26 takes in the pulses C1 to C3 output from the counter 25 at the falling timing of the horizontal synchronizing signal HS, and each pulse C1 at that time.
The period of the horizontal synchronizing signal HS is determined from the states of C3 to C3, and the determination result is output as the third data Dc. For example, if the pulse C2 rises at the falling timing of the horizontal sync signal HS, it is determined that the cycle of the horizontal sync signal HS is a predetermined cycle, and if the pulse C1 rises, one clock is supplied for the predetermined cycle. It is judged as short.

The pulse synthesizing circuit 27 is constructed so as to extract the reference clock CK only during the rising period of the pulses C1 to C3 output from the counter 25, and the pulse C
A clock pulse P0 whose pulse rises in the period designated by 1 to C3 is generated. The delay circuit 28 is configured by connecting a plurality of delay elements having the same delay time in series, and delays the clock pulse P0 stepwise to generate a plurality of clock pulses P1 to P9 having a constant phase difference. . The phase difference between these clock pulses P0 to P9 is set according to how finely the phase difference of the horizontal synchronizing signal HD with respect to the reference clock CK is determined. Here, the frequency of the reference clock CK is 14.32 MHz
At this time, the phase difference between the clock pulses P0 to P9 is set to 9 nsec, and 10 types of clock pulses P0 to P9 are set.
Is being generated.

The period (Ta) determination circuit 29 determines each clock pulse P at the falling timing of the horizontal synchronizing signal HS.
The states Ta to P9 are fetched, and the period Ta from the rising of the reference clock CK to the falling of the horizontal synchronizing signal HS is determined from these states. In the Ta determination circuit 29, the period Ta is determined based on the position where the states of the clock pulses P0 to P9 change. For example, the state of the clock pulses P0 to P1 is "HHLLLLLHHHH".
When it is, it is determined that the period Ta is entered at the timing of changing from “H” to “L”, that is, 9 to 18 nsec. Every time this change position shifts by one, the period Ta shifts by 9 nsec. Therefore,
The first data Da is generated so as to represent how many times this period Ta becomes 9 nsec. With respect to the first data Da, as long as the cycle Tb of the reference clock CK is not shifted, the period Ta is in one of the periods Tb divided into eight, and therefore it is sufficient to distinguish eight kinds of states.

The cycle (Tb) determination circuit 30 determines each clock pulse P at the rising timing of the reference clock CK.
The states of 0 to P9 are taken in, and the cycle Tb of the reference clock CK is determined from those states. In the Tb determination circuit 30, as in the Ta determination circuit 29, each clock pulse P0
The period Tb is determined based on the position where the states of P9 to P9 are switched. For example, when the state of the clock pulses P0 to P1 is "LLLLHHHHLL",
Timing of switching from “H” to “L”, that is,
It is determined that the cycle Tb is included between 63 and 72 nsec. Therefore, the second data Db is generated so as to represent how many times this cycle Tb becomes 9 nsec.

Normally, when the PLL 16 is operating normally, the cycle of the reference clock CK does not change greatly and the second data Db represents "8". However, when the cycle of the reference clock CK fluctuates for some reason, the second data Db comes to represent "7" or "9". To ensure such a margin, 1
Generates 0 types of clock pulses P0 to P9 to generate a cycle Tb
Is configured to judge. The first and second data Da and Db obtained as described above represent simple integers and are maintained during one horizontal scan. Based on this, the image data Y0 in the brightness data correction circuit 18 The composition ratio is set.

If the horizontal synchronizing signal HS deviates from the predetermined cycle by two clock periods or more, it cannot be determined with the above configuration. When detecting the deviation of the horizontal synchronizing signal HS for two clock periods, the five kinds of pulses that rise sequentially are taken out from the counter 25 at the timings that are shifted by one clock period, and the five kinds of pulses are taken to the falling edge of the horizontal synchronizing signal HS. It is configured to be taken into the cycle determination circuit 26 at the timing of. In the normal image signal i, the cycle of the horizontal synchronizing signal HS does not greatly deviate, so that it is possible to cope with almost all cases if the determination can be made in one clock period or two clock periods before and after the predetermined period.

Further, the reference clock CK and the horizontal synchronizing signal H
When the phase difference from S is determined more finely, the delay time of the delay element of the delay circuit 28 is shortened and the number is increased to generate more delayed clock pulses. At the same time, the Ta determination circuit 29 and the Tb determination circuit 30
The number of determination bits may be increased so that the state of each clock pulse can be captured and determined. In this determination, it is preferable that one cycle of the reference clock CK (14.23 MHz) is divided into 16 or more in consideration of the visual effect.

FIG. 6 is a block diagram showing the structure of the synchronizing signal generating circuit 19, and FIG. 7 is a timing chart for explaining its operation. The synchronization signal generation circuit 19 corresponds to the correction data generation circuit 17 shown in FIG.
A case will be described in which the deviation of S is corrected by one clock of the reference clock CK. The H counter 31 has a horizontal synchronization signal H.
It is reset by S to count the reference clock CK and supplies the count value to the H decoder 32. The H decoder 32 decodes the count value supplied from the H counter 31, and generates a horizontal timing signal HD which is raised when the count value reaches a predetermined count value. In this H decoder 32, ± 1 with respect to the reference decode value
Of the horizontal timing signals HD [± 0], HD [−1], and HD [+1] are generated in total. For example, with respect to the count value of the H counter 31, “9
09, “910”, and “911” decode values are set, and horizontal timing signals HD [± 0], HD [−1], HD [+1] having a cycle corresponding to each decode value are output. To be done. The selector 33 includes the correction data generation circuit 17
From the H decoder 32 in response to the third correction data Dc input from the H decoder 32.
One of D [± 0], HD [−1], and HD [+1] is selected and output.

The V counter 34 counts the horizontal timing signal HD which is reset by the vertical synchronizing signal VS and selectively fetched from the selector 33, and supplies the count value to the V decoder 35. The V decoder 35 decodes the count value supplied from the V counter 34 and generates a vertical timing signal VD which is raised when the count value reaches a predetermined count value. The V counter 34 and the V decoder 35 count with a clock having a half cycle of the horizontal timing signal HD, and when the count value of the V counter 34 reaches “525”, the V decoder 35.
Is designed to raise the vertical timing signal VD. As a result, the timing of horizontal scanning is shifted by ½ horizontal scanning period for each vertical scanning period in response to interlaced scanning.

Here, it is conceivable that the H counter 31 is reset before the decoding value set in the H decoder 32 is reached due to fluctuations in the cycle of the horizontal synchronizing signal HS serving as a reference. In order to prevent this, the count value at the time of reset is set to be shifted from "0". For example, when reset, the count value is set to "10", and from "10" to "92".
It is configured to continue counting to "0".

According to the above configuration, even if the cycle of the horizontal synchronizing signal HS is deviated, the cycle of the horizontal timing signal HD is changed according to the deviation, so that the luminance data and the color are changed in each horizontal scanning period. The phase difference with the data can be corrected. FIG. 8 is a block diagram showing a second embodiment of the image data processing device of the invention. In this figure,
The signal processing for separating the luminance component and the color component is digitized, and the reference clock CK and the horizontal synchronization signal H
The detection of the phase difference from S and the correction of the jitter are the same as in FIG.

Synchronous detection circuit 14 and burst detection circuit 1
5, the PLL 16, the correction data generation circuit 17, the brightness data correction circuit 18, the timing signal generation circuit 19, and the image data processing circuit 20 are the same as those in FIG. The amplifier 36 is a high frequency amplifier in the video band and takes in the image signal i and amplifies it to a predetermined amplitude. The A / D conversion circuit 37 outputs the amplified image signal i from the reference clock C output from the PLL 16.
Quantization is performed according to K to generate image data I. Y / C
The separation circuit 38 takes in the image data I, separates the luminance component and the color component, and generates luminance data Y0 and color data C0. The Y / C separation circuit 38 is obtained by digitizing the signal processing in the Y / C separation circuit 1 of FIG.
For example, in the NTSC system, the luminance data Y is obtained by shifting the image data I by one horizontal scanning period and adding them in the same column.
The color data C0 is generated by generating 0 and similarly performing subtraction. The luminance data Y0 output from the Y / C separation circuit 38 is supplied to the image data processing circuit 20 as the image data Y1 through the jitter correction circuit 20, and the color data C0 is directly supplied to the image data processing circuit 20.

According to the second embodiment, the predetermined processing can be achieved by the one-channel amplifier 36 and the A / D conversion circuit 37, so that the circuit scale can be further reduced as compared with the first embodiment. Moreover, since the number of analog circuits is reduced, it is less likely to be affected by noise and the like, and improvement in operating characteristics can be expected.

[0035]

According to the present invention, the phase difference between the luminance data and the color data due to the jitter contained in the image signal is corrected, and the disturbance of the outline of the subject and the color bleeding on the reproduction screen are prevented. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an image data processing apparatus of the present invention.

FIG. 2 is a timing diagram illustrating a correction operation of brightness data.

FIG. 3 is a block diagram showing a configuration example of a brightness data correction circuit.

FIG. 4 is a block diagram showing a configuration example of a phase difference detection circuit.

FIG. 5 is a timing diagram illustrating the operation of the phase difference detection circuit.

FIG. 6 is a block diagram showing a configuration example of a synchronization signal generation circuit.

FIG. 7 is a timing diagram illustrating the operation of the synchronization signal generation circuit.

FIG. 8 is a block diagram showing a second embodiment of the image data processing device of the invention.

FIG. 9 is a block diagram showing a configuration of a conventional image data processing device.

FIG. 10 is a waveform diagram of an image signal and each synchronization signal.

[Explanation of symbols]

1, 11, 38 Y / C separation circuit 2, 12, 36 amps 3, 13, 37 A / D conversion circuit 4, 14 Synchronous detection circuit 5, 15 Burst detection circuit 6, 16 Phase Lock Loop (PLL) 7, 19 Synchronous signal generation circuit 8, 20 Image data processing circuit 17 Correction data generation circuit 28 Luminance data correction circuit 21 Latch 22, 23 Multiplier 24 adder 25 counter 26 Period judgment circuit 27 pulse synthesis circuit 28 Delay circuit 29, 30 period determination circuit 31 H counter 32 H decoder 33 Selector 34 V counter 35 V decoder

Claims (3)

(57) [Claims] 1. Luminance data representing a plurality of pixels constituting a screen, which is continuous in a row unit in synchronization with a horizontal synchronizing signal, and color data representing color information corresponding to the luminance data. In the image data processing device that processes in parallel,
A phase-locked loop that generates a reference clock with a constant period in synchronization with a color synchronization signal that obtains synchronization of color information, and measures the period of the reference clock, generates first data representing the period, and generates the reference clock. With respect to the horizontal synchronization signal is measured, second data representing the phase difference is generated, the period of the horizontal synchronization signal is measured based on the reference clock, and a deviation from the predetermined reference period is measured. A correction data generation circuit that generates third data that represents
A luminance data correction circuit for generating the corrected luminance data by combining the luminance data continuous in time series at a rate determined based on the first and second data, and the reference clock according to the third data. An image data processing device, comprising: a timing signal generation circuit that generates a timing signal of a horizontal scanning period by dividing the frequency in response to the horizontal synchronization signal. 2. A luminance signal and a color signal are generated by individually taking out the luminance signal and the color signal from an image signal including the luminance signal and the color signal and various synchronization components, and the luminance signal and the color signal are respectively used as the reference clocks. The image data processing apparatus according to claim 1, wherein the image data processing apparatus quantizes the luminance data and the color data according to quantization. 3. An image signal including a luminance component and a color component and various synchronization components is quantized according to the reference clock to generate image data, and the luminance component and the color component are individually extracted from the image data to obtain the luminance data. The image data processing apparatus according to claim 1, wherein the image data processing apparatus generates color data.