JP4679748B2 - Digital video processing circuit and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital video processing circuit and method, and more particularly, to a clock phase for sampling an analog video signal and zero of the horizontal synchronization portion of the analog video signal. _H Control the reference point to be related to accurately reproduce the relationship between horizontal synchronization and video phase in digital data, and the sampling clock is 0 _H The present invention relates to a digital video processing circuit and method for sending a phase error signal to a sampling clock generator to sample a reference point.
[0002]
[Prior art]
Conventionally, synchronization separation is performed by an analog circuit. That is, the analog circuit determines the midpoint level of the synchronous portion of the analog video signal, compares the analog video signal at the determined midpoint level, and uses this comparison output to generate a sampling clock by the PLL, or A separate sync signal or a sync-like sync signal is generated from the comparator output.
[0003]
The composite video signal in the NTSC system is an interlace system, and is composed of an odd field and an even field. That is, in the case of a still image, the repetition of the image is an odd / even two-field cycle. However, in relation to the color carrier signal, the phase is shifted by 90 degrees for each field, and the original image signal is returned in four fields. This is called a four field sequence and is also called a color field sequence.
[0004]
In connection with the NTSC video signal having this four-field sequence, in particular, it prevents horizontal shift of the image when recording to the VTR (ie, the relationship between the phase of the clock locked to the burst and the horizontal sync phase). The new EIA RS-170A has been created as a standard for composite sync signals, compared to the conventional EIA RS-170. In this standard, the phase relationship between the horizontal synchronizing signal (H-SYNC) and the color subcarrier signal (color burst signal signal) is defined. This relationship is called SCH (Sub Carrier to Horizontal).
[0005]
FIG. 1 is a waveform diagram showing timing within the horizontal blanking period (10.9 ± 0.2 μs) before and after the horizontal synchronization signal of the television signal of EIA RS-170A in the NTSC standard. In this standard, the reference point of the horizontal synchronizing signal is a timing point having a level of −20 IRE, which is the midpoint of the amplitude level of 40 IRE, at the starting partial point of the signal. _H It is called a reference point. This 0 _H The reference point, when expressed in relative terms, points to the center value of the synchronization level. _H With reference to the reference point, the trailing edge of the horizontal synchronizing signal, the phase of the color burst signal, and the trailing edge of the horizontal blanking are determined.
[0006]
[Problems to be solved by the invention]
However, it is difficult to accurately obtain the average value of the horizontal sync tip level and the pedestal level in the sync separation by the analog circuit. Even if the accuracy is obtained accurately, the values of the horizontal sync tip level and the pedestal level are average values of the past sync signals, not the sync signal itself that is to be detected.
[0007]
Also, even if the level of a television signal in the form of an analog signal is generated at a specified level at the signal source, it is obtained at a usable position due to cable loss, amplifier gain error, etc. The level is attenuated or the level is too large, and does not necessarily have a level according to the standard.
[0008]
Even in the sampling clock for A / D conversion by the PLL generated based on the synchronization separation by the analog circuit described above, 0% of the analog signal is not necessarily generated due to the signal delay included in the control loop. _H The reference point is not necessarily sampled. In addition, the delay of the analog signal is adjusted by adjusting the signal delay and the delay caused by the analog processing circuit. _H Although it is possible to sample the reference point, for this purpose, a stable delay circuit is required, and adjustment work for manually adjusting the circuit and parts individually is required.
[0009]
In particular, in an apparatus for digitizing an analog video signal, it is important to have a sampling point as a synchronization reference point. Further, in the digital processing circuit, there are merits in improving performance and making no adjustment, and providing such individual adjustment points in the digital processing circuit has been overturned. Exact 0 _H Obtaining the reference point on the digitized quantized sample is also important for accurate reproduction of the horizontal image phase.
[0010]
The present invention has been made in view of such a problem, and an object of the present invention is to obtain a synchronization signal from an A / D converted video signal by digital processing. _H Accurately estimate the reference position and use the result for subsequent digital video signal processing or return it as a phase error signal to the PLL oscillator that generates the sampling clock signal for A / D conversion. Correct the horizontal position of the data to be represented, or set the sampling point to 0 _H It is an object of the present invention to provide a digital video processing circuit and method for use in generating a clock signal matched with a reference point.
[0011]
In the present invention, an accurate 0 of the synchronization signal which has been obtained by analog in the past is obtained. _H The position is obtained by digital calculation processing, and the result is accurately reflected in the relationship with the horizontal position of the screen of the signal representing the video; _H The phase difference of the sampling point with respect to the reference point is obtained by arithmetic processing, and this is fed back to the PLL as a phase error signal, thereby synchronizing with the sampling point _H The purpose is to match the reference points.
[0012]
[Means for Solving the Problems]
In order to achieve such an object, the present invention provides a digital video processing circuit according to claim 1, wherein an analog video signal is input, and a synchronized portion and an image of the analog video signal are input. An A / D converter that converts a quantized sample signal into a quantized sample signal according to a sampling clock including a portion, and a horizontal sync that extracts a horizontal sync component signal by inputting the quantized digital signal and comparing it with a predetermined threshold value A horizontal coordinate generating means for receiving a horizontal coordinate for each quantized sample of the quantized sample signal in response to an output from the separating means;
In response to the output from the horizontal sync separator, 0 of the horizontal sync portion of the quantized sample signal _H Waveform storage / reproducing means for temporarily storing and outputting a plurality of continuous quantized sample values in the vicinity of the reference point, and a quantized sample value output from the A / D converter are input, and the horizontal sync separating means In response to the output, calculate the average value of the quantized samples in each of the period representing the leading edge of the horizontal synchronization part and the period representing the pedestal level part in the blanking period. SYNC slice level setting means for determining, a plurality of consecutive quantized sample values output from the waveform storage / reproduction means and the midpoint level output from the SYNC slice level setting means are compared, Correction data generating means for determining a relationship between the sample having the midpoint level and a plurality of the quantized sample values and outputting correction data; and from the correction data generating means Based on the correction data, it is characterized in that and a horizontal coordinate correction means for correcting the output of the horizontal coordinate generating means.
[0013]
According to a second aspect of the present invention, there is provided the digital video processing circuit according to the first aspect, wherein correction data is inputted and phase adjustment including a delay or phase advance of less than one clock of the quantized sample signal is performed. A phase adjustment unit for performing the correction, wherein the correction data generation unit compares the quantized sample value and the quantized sample extracted by the horizontal sync separating unit in comparison with the midpoint level and a plurality of consecutive quantized sample values. A clock unit difference between them, and if they do not match, one quantized sample of two consecutive quantized samples including the midpoint level value between them and the quantized sample extracted by the horizontal sync separating means, The phase adjustment means outputs the difference from the clock unit to the horizontal coordinate correction unit as integer part correction data, and uses the amount of deviation from the one quantized sample as decimal part correction data. It is characterized in that output.
[0014]
According to a third aspect of the present invention, there is provided the digital video processing circuit according to the second aspect, wherein the digital video processing circuit is output from the horizontal coordinate generation means and is based on the horizontal coordinate data corrected by the correction means. System clock signal generating means for generating an error signal and generating the sampling clock signal is further provided, and the correction data generating means converts the integer part of the correction data in units of the sampling clock into the horizontal coordinate correcting means. Output the fractional part of the correction data to the system clock signal generator, the system clock signal generation means receives the decimal part from the correction data generation means and superimposes it on the error signal, The phase of the sampling clock is set to 0 of the horizontal synchronization portion of the quantized sample signal. _H Control is performed so as to be a reference point.
[0015]
According to a fourth aspect of the present invention, there is provided an A / D converter for inputting an analog video signal and converting the analog video signal into a quantized sample signal according to a sampling clock including a synchronizing portion and a video portion of the analog video signal. In a digital video processing method in a digital video processing circuit comprising: a horizontal sync separation step for extracting a horizontal sync component signal by inputting the quantized digital signal and comparing it with a predetermined threshold; and the horizontal sync Based on the horizontal synchronization component signal extracted in the separation step, a horizontal coordinate start step for starting generation of horizontal coordinate data representing the horizontal coordinate for each quantized sample of the quantized sample signal, and extraction in the horizontal synchronization separation step Of the horizontal synchronization component signal of the quantized sample signal _H A waveform storing step for temporarily storing a plurality of continuous quantized sample values near the reference point, and a quantized sample value output from the A / D converter are input, and an output from the horizontal sync separator is received. A SYNC slice for calculating the average value of quantized samples in each of the period representing the leading end portion of the horizontal synchronization portion and the period representing the pedestal level portion in the blanking period, and determining the midpoint of the two average values A level setting step and 0 of the horizontal synchronization portion of the quantized sample signal stored by the waveform storing step _H A plurality of consecutive quantized sample values in the vicinity of a reference point are input and compared with the midpoint level output from the SYNC slice level setting means, a sample having the midpoint level and a plurality of the quantized samples A correction data generation step for determining a relationship with the value and outputting correction data; and output of the horizontal coordinate data started in the horizontal coordinate generation step based on the correction data representing the relationship from the correction data generation step. A horizontal coordinate correction step for correction is provided.
[0016]
The invention according to claim 5 is the digital video processing method according to claim 4, wherein correction data is input and phase adjustment including a delay or phase advance of less than one clock of the quantized sample signal is performed. A phase adjustment step to perform, wherein the correction data generation step includes a quantization sample value that matches the midpoint level compared with a plurality of consecutive quantization sample values and a quantization sample extracted by the horizontal synchronization separation means A clock unit difference, and if not, one quantized sample of two consecutive quantized samples including the midpoint level value in between and the quantized sample extracted in the horizontal sync separation step; Is output to the horizontal coordinate correction step as integer part correction data, and the amount of deviation from the one quantized sample is used as decimal part correction data. And outputs to the phase adjustment step.
[0017]
The invention according to claim 6 is the digital video processing method according to claim 5, wherein the video processing circuit outputs an error signal based on horizontal coordinate data output from the horizontal coordinate generation means. And further comprising a system clock signal generator for generating the sampling clock signal, wherein the determining step outputs an integer part of the correction data in units of the sampling clock to the horizontal coordinate correction means, Outputting a fractional part of the correction data to the system clock signal generator, the system clock signal generator receiving the fractional part from the correction data generating step and superimposing it on the error signal; The clock phase is set to 0 of the horizontal synchronization part of the quantized sample signal _H Control is performed so as to be a reference point.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
FIG. 2 is a diagram showing an embodiment of a digital processing circuit including an A / D converter to which the present invention is applied. This figure shows a horizontal timing processing unit in an analog video processing circuit and is drawn as a functional block diagram. An A / D converter 201 that converts an analog video signal into quantized samples, a low-pass filter 202, a slice unit 203 that has a fixed slice level and separates synchronization components, and a variety of components from the separated synchronization components A timing generation unit 204 that generates a timing signal, a signal from the timing generation unit, an average value calculation unit 205 at the tip of the horizontal synchronization portion (Sync tip), an average value calculation unit 206 at the pedestal portion, and an average value calculation thereof Waveform storage for storing and reproducing the start part of the synchronization signal delayed by the delay unit 209 in response to the outputs from the arithmetic unit 207 and the timing generation unit A correction data generation unit 2 that generates correction data by comparing each quantized sample value from the reproduction unit 210 and the waveform storage reproduction unit with an output value from the calculation unit. 1, receives the output from the timing generation unit, and configured to include a pixel counter section 212 which generates a horizontal coordinate data for digital processing.
[0020]
The pixel counter unit 212 is attached with a correction circuit that receives the output from the correction data generation unit 211 and corrects the output coordinate data. The output from the correction data generation unit is sent to a PLL circuit of a sampling clock signal generation unit (not shown) and superimposed on the phase difference detection signal.
[0021]
In FIG. 2, the video component processing circuit or processing system is omitted for the sake of simplicity. Also, a sampling clock as a processing clock in digital processing is omitted.
[0022]
The output data signal of the pixel counter unit 212 shown in FIG. 2 is 0 after the timing at which correction processing described later is executed. _H This signal represents the horizontal synchronization expressed with reference to the timing of the reference point. Specifically, the sampling clock is counted throughout one horizontal scanning period, and the horizontal position, for example, the position of the color burst, the blanking area. Are used as a signal for determining the phase of a counter called an H counter that finally determines the range.
[0023]
The timing at which the output of the pixel counter 212 is corrected by the correction data generation unit 211 will be clarified in the description to be described later, but is at least a timing delayed from the period when the color burst signal starts. Therefore, in some cases, it is possible to accurately predict the end timing of a color burst based on the corrected horizontal coordinate, but in the above-described embodiment, the pixel counter 212 may be Since it starts at the edge and the start portion, the start portion of the color burst is temporary horizontal coordinate data. The range indicated by the corrected horizontal coordinate is expanded by delaying a predetermined number of clocks from the leading edge and start portion of the synchronous component and starting immediately before correction from the correction data generation unit. It is possible.
[0024]
The operation of the block diagram shown in FIG. 2 will be described below.
[0025]
Although the input analog video signal is not shown in the figure, it is a signal in which the DC component is reproduced and within a specific voltage range, and the level representing the black level in the pedestal portion of the video signal, that is, the blanking portion, is predetermined. For example, if the A / D converter outputs 8 bits, it is set to a level that outputs a quantized value of 80 (decimal display, and so on). Here, assuming that the white specified level of 100IRE is 240, the leading edge level of synchronization of −40IRE is 16. In this case, it becomes possible to A / D-convert a video signal (television signal) of a specified level, leaving a margin of 15 quantization levels above and below.
[0026]
ITU-R BT. In the studio coding parameter defined in 601, 16 is set when the black level of Y is 8 bits, and the white level of Y is 235. However, a look-up table in which 80 to 240 corresponds to 16 to 235 is 80. This can be handled by converting ~ 255 to 16 ~ 254. In addition, since a 10-bit A / D converter is normally used, even if A / D conversion is performed including the synchronous portion as described above, there is no problem with respect to reduction of the dynamic range.
[0027]
In this embodiment, when a specified level is input, the synchronization tip is 16, the black level is 80, and the white level is 240. Here, the black level is basically set so that the DC voltage of the pedestal level is set to a constant voltage by the pedestal clamp circuit on the input side of the A / D converter, and is at least 80 or in the vicinity thereof. A value is assumed to be set. Further, the A / D converter has 8 bits for simplification, and the quantized value is 8 bits in decimal notation.
[0028]
The analog video signal as described above is quantized by the A / D converter 201. In order to remove noise and color subcarrier components from this output signal, first, a filter 202 (a low-pass filter or a bandpass filter that removes only the subcarrier frequency under conditions without noise) is passed. The digital video signal from which the subcarrier frequency component is removed is compared with a fixed value (for example, 59) determined in advance in the fixed value slicing unit 103 (fixed value slice) to extract a synchronization signal. This fixed value is 48 when the level of the input video signal is half of the specified level or when the level of the sync component is halved, because the leading end of the sync component has a value of 48. This is a numerical value that makes it possible to detect only the sync signal while avoiding noise near the black level.
[0029]
If the input level of the fixed slice unit 203 is a composite video signal having a level value between a specified level and a half level of the specified level, a separated composite sync signal is present at the output of the fixed slice unit. Is output. Upon receiving this signal, the timing generation unit removes an equivalent pulse or V synchronization component from the input composite synchronization signal, detects only the horizontal synchronization portion, and generates a predetermined timing signal.
[0030]
Normally, when taking out the horizontal sync component, the state of the composite sync signal input after a period of 3/4 of the horizontal sync signal width from the start of the composite sync signal (since the horizontal equivalent pulse is 1/2 of the horizontal sync signal width) Is done by examining. In this case, the timing assumed to be the horizontal synchronizing signal is after a period of 3/4 of the horizontal synchronizing signal width from the start portion, and in this embodiment, from the output timing of the fixed slice portion.
[0031]
The output of the filter unit 202 is delayed by the delay unit 209 so that the waveform storage / reproduction unit 210 stores the horizontal synchronization start portion detected at the horizontal synchronization detection timing. At the output point of the delay unit, when the timing generation unit detects horizontal synchronization, the timing is before the horizontal synchronization start point. This is because when the input signal level is ½ of the specified value, the slice level of the fixed slice is lower than the midpoint of the input synchronization level, and therefore, 0 _H This is because the reference point exists before the timing detected by the fixed value slice part, and the signal state within that range needs to be waveform-stored.
[0032]
As described above, the signal delayed by the delay unit 209 starts to be stored in the waveform storage / reproduction unit 210 by a signal indicating that horizontal synchronization is detected from the timing generation unit, and a predetermined number of clocks (for example, 32 clocks; corresponding to a period of about 1.2 μs in the case of a 27 MHz clock).
[0033]
The Sync Tip average value calculation unit 205 and the pedestal average value calculation unit 206 add and subtract 64 data numbers in consideration of a predetermined number of data, in this embodiment, bit shift calculation. That is, after the start of integration of one data per clock, the first integrated data is subtracted 65 clocks (corresponding to about 2.37 μs for a 27 MHz clock, which is about 1/2 of the horizontal sync width). As a result, the integrated value of the past 64 data is obtained. In addition, a value of 1/64 or a value of 1/2 can be obtained by bit operation of this output. Here, data of 1/128 of the integrated value is output by bit operation.
[0034]
FIG. 3 is a diagram for explaining the operation of each block in FIG.
[0035]
The timing generation unit 204 detects the horizontal synchronization component (indicated by t1), and this point is already at the input point of the Sync Tip average value calculation unit 205 after the horizontal synchronization signal portion has been input. / 4 data is input. Therefore, when the Sync Tip average value calculation unit 205 calculates the average value of the quantized sample values that are input over about a half of the horizontal synchronization period, the horizontal synchronization detection from the timing generation unit is performed. When the signal is received, the average value of the region excluding the start portion corresponding to 1/2 of the horizontal synchronization width is output. This is indicated by the rectangular frame depicted in FIG. Therefore, the Sync Tip average value calculation unit 205 receives the horizontal synchronization start signal from the timing generation unit, outputs the average value so far, and maintains the output value until receiving the signal from the next timing generation unit. .
[0036]
The pedestal average value calculation unit 206 has the same configuration as the Sync Tip average value calculation unit 205, and the color removed by the filter 202 by the timing signal (indicated by t 2) generated from the horizontal synchronization component detection signal in the timing generation unit. -At the timing (indicated by t2) at which the average value of the signal in a predetermined period including the burst signal portion is calculated, the average value of the previous period is output, and the output value is received from the next timing generation unit Keep up.
[0037]
At the time when the output of the pedestal average value calculation unit 206 is updated, the output of the Sync Tip average value calculation unit 205 has already been updated. The midpoint level of the value, ie 0 _H Outputs a reference level for detecting a reference point.
[0038]
The timing generation unit performs read start control on the waveform storage / reproduction unit when the above-described reference level is supplied to the correction data generation unit.
[0039]
The waveform storage / reproduction unit 210 starts reproduction from a quantized sample at a timing prior to the quantized sample that has become the fixed slice level or lower for the first time, for example, data having a value near 80 (shown below in FIG. 3). Here, for simplification of control, it is convenient that the address of the quantized sample that has become below the fixed slice level for the first time is determined in advance.
[0040]
FIG. 4 shows the quantized sample value of the synchronization start portion that is processed and stored in the waveform storage / playback unit after the input signal of the specified level is processed. The numerical value on the left side of the figure indicates the quantized value. In this figure, there is no quantized sample having the level of the midpoint of the synchronization level (in this case, the quantized value 48). In the example shown, the midpoint between the sample below the fixed slice level and the next sample is 0. _H This is a point corresponding to the reference point.
[0041]
If the level of the input signal is ½ of the specified level, the middle of the synchronization level is a value of 64, which is larger than the fixed slice level. In this case, 0 before the sample below the fixed slice level. _H There will be a point corresponding to the reference point.
[0042]
FIG. 5 is an enlarged view of a part of FIG. 4 and illustrates the operation of the correction data generation unit in more detail.
[0043]
The correction data generation unit compares the quantized samples one after another, and specifies the address of the quantized sample having a level that is the same as or lower than the reference level. Here, the address of the quantized sample output first in the fixed slice part is A _FIX , And the address of the specified quantized sample is A _C It is assumed that the numerical value of the quantized sample address increases with time. Also, set the fixed slice level to C _FIX And the synchronization midpoint level calculated by the calculation unit 107 is C _0H And
[0044]
(Fixed slice level> Sync midpoint level)
0 if fixed slice level> sync midpoint level _H The reference point exists at a timing (large address) that is equal to or later than the fixed slice output timing.
[0045]
Here, the reference level supplied to the correction data generation unit 211 has a decimal part by calculating an average value. Therefore, the probability that the level of the quantized sample value to be compared matches the reference level is considerably low. Therefore, normally, the address of the quantized sample that first falls below the reference level is specified. Where the address of the identified quantized sample is A _C , The value is S _C And the address of the immediately preceding quantized sample is (A _C -1), the value is S _C-1 (This quantized sample value has a level value greater than the reference level), and the reference level is S _ref And The following two operations are performed between
(S _C-1 -S _ref ) / (S _C-1 -S _C ) ... Formula 1
(S _ref -S _C ) / (S _C-1 -S _C ) ... Formula 2
Here, the value of Equation 1 is the quantized sample S when the clock period is 1. _C-1 0 against _H Indicates the timing deviation of the reference point, and the quantized sample S _C-1 0 against _H It represents the delay amount of the reference point. Further, Equation 2 represents the quantized sample S when the clock period is 1. _C 0 against _H This represents the deviation from the reference timing, and the quantized sample S _C 0 against _H Indicates the advance amount of the reference point.
[0046]
The correction data for the pixel counter is as follows.
Correction data = {(A _C -1) -A _FIX } + (S _C-1 -S _ref ) / (S _C-1 -S _C ) ... Formula 3
Where {(A _C -1) -A _FIX } Is a numerical value in clock units, and the remainder is a fraction in clock units.
[0047]
(When fixed slice level <sync midpoint level)
0 if fixed slice level <sync midpoint level _H The reference point exists at an advanced timing (larger address) than the fixed slice output timing. The correction data for the pixel counter in this case is as follows.
Correction data = (A _C -A _FIX )-(S _ref -S _C ) / (S _C-1 -S _C ) ... Formula 4
Or
Correction data = {(A _C -1) -A _FIX } + (S _C-1 -S _ref ) / (S _C-1 -S _C ) ... Formula 5
It can be expressed as. Here, Expression 4 and Expression 5 represent the same contents, and (A _C -A _FIX ), {(A _C -1) -A _FIX } Is a numerical value in clock units, and the remaining is a fraction in clock units.
[0048]
(Part 1 of correction data fraction processing)
The fractions of Equation 3 and Equation 5 above are the same. In this case, when the pixel counter 212 is corrected by each integer part, the phase of the sample representing each video is represented by the fractional part of Expression 3 or Expression 5 rather than the phase represented by the pixel counter 212. It is represented with a delay by the amount. That is, 0 _H The reference point is at a position that is delayed by a fractional part of Equation 3 or Equation 5 from the sample position on which the pixel counter 212 is based. In this case, the fact that the fractional part of Equation 3 or 5 is the same indicates that the digital processing of the fractional part of Equation 3 or 5 is the same. In this process, each sample value of the video area is converted to a fractional value (S _C-1 -S _ref ) / (S _C-1 -S _C ) Can only be achieved. This phase advance is to execute the following calculation and set the value as the value of the address M + 1. Where (S _C-1 -S _ref ) / (S _C-1 -S _C ) = Α.
(Quantized value of address M + 1) × α + (quantized value of address M) × (1-α) Equation 6
[0049]
When considering the above-described expression 3 or expression 5 by changing the expression 5 to the expression 4, for example, by delaying the focus point by one clock, the fractional part is expressed as (S _ref -S _C ) / (S _C-1 -S _C ) In this case, (S _ref -S _C ) / (S _C-1 -S _C ) (Clock unit), only the amount _H Since the reference point is advanced, it is necessary to delay each sample value of the video. In this case as well, the only difference is that the value obtained by the operation is stored in the address M, and the operation result is equivalent to Equation 6.
[0050]
(Part 2 of correction data fraction processing)
The fraction of the correction data can be set to 0 or substantially 0 by shifting the phase of the sampling clock. In this case, only the integer part of the correction data can be used as pixel counter correction data.
[0051]
When the fraction of the correction data is a sampling clock PLL circuit, how to express the fraction part becomes a problem. Here, it is assumed that the PLL circuit is configured based on the output of the fixed value slice unit.
[0052]
When the fractional part is 0 (zero), it is natural that the error signal is 0. _H It is necessary to make + when the reference point is late and minus it when it is advanced.
[0053]
Therefore, in comparison with the above-described Expression 1 and Expression 2, when Expression 1 is small, the value of Expression 1 is +, and when Expression 2 is small, the value of Expression 2 is negative and is generated as a phase error correction signal. To do. In this case, the correction data of the pixel counter is {(A _C -1) -A _FIX }, If Formula 1> Formula 2 then (A _C -1-A _FIX ) In short, 0 _H Sampling phase close to the reference point is 0 _H It will be closer to the reference point. When the polarity of the phase error correction signal described above is +, the phase is advanced to decrease the value of the error signal. When the polarity is negative, the phase is advanced to decrease the absolute value of the error signal. The PLL circuit is operated.
[0054]
Even in this case, a minute jitter of 1 clock or less is inevitable. For example, it may be assumed that the jitter is about 1/40 of the clock. In this case, an exact 0 _H The reference point is positioned before and after the sample point at the specific position. In this case, 0 _H The integer part of the correction data is generated based on the (temporal) sample position in the vicinity of the reference point.
[0055]
(Part 3 of correction data fraction processing)
A PLL different from the configuration described above will be described.
[0056]
FIG. 6 shows a PLL configured based on the fractional part of the phase error data of the pixel counter and the correction data generation unit shown in FIG. A voltage-controlled crystal oscillator (XVCO) 601, a free-running counter 602 that inputs a 13.5 MHz clock signal of XVCO output, for example, and divides 1/858, an output of the free-running counter 602, and a pixel counter (this output) Is a subtractor 603 that outputs a difference from the output of the corrected data), an error signal generator 604 that generates an error signal from this output, and a decimal number of correction data from the error signal and the correction data generator An adder that inputs and adds a part is provided. The output of the adder 605 is analog-converted by D / A conversion or PWM modulation, and is supplied to the XVCO unit.
[0057]
For example, the error signal generation unit keeps the case where the result of subtracting the corrected pixel counter output data from the free-running counter 602 is a numerical value between 0 and 428 (= 858/2), and keeps it as it is from 429 to 857. If the numerical value is between 1 and 858, the error signal is generated by further subtracting 858 from the subtraction value to obtain a negative number.
[0058]
The configuration shown in FIG. 6 can separate the phase comparison point of the PLL from the generation time of the horizontal synchronization signal. Although omitted in the above description, the horizontal synchronization 0 in the 9H vertical synchronization signal period is omitted. _H Even if the calculation completion point at the midpoint level when the reference point is detected deviates from the calculation completion point in the case of a normal horizontal synchronizing signal, the deviation can be ignored.
[0059]
Of course, the polarities of the error signal generation unit 604 and the decimal part of the correction data of the correction data generation unit are matched, and the control polarity of the XVCO is also matched.
[0060]
By controlling as described above, the input signal 0 _H A sampling clock that samples the reference point can be generated and at the same time 0 _H The horizontal coordinate data starting from the reference point can be obtained.
[0061]
As mentioned above, although this invention was demonstrated using this embodiment, it is easy to change into the following form, without deviating from the meaning of this invention.
When sampling at 1.27 MHz and performing basic processing with a half 13.5 MHz clock, this 13.5 MHz clock phase is set to 0. _H The present invention can also be applied when matching with a standard. Several methods can be considered for this method. When the phase error signal is not sent to the PLL circuit, it can be executed by performing a filtering process using a resampling method. Also, when sending a phase error signal to the PLL circuit, the pixel counter activation timing is halved with a 13.5 MHz clock, the correction data generator remains at 27 MHz, and the integer part is an even value. If 1 is generated too much, it is possible to perform the processing when the formula 1 is small without comparing the formula 1 and the formula 2 described above, and to set the phase correction error at that time to 1 + formula 1. .
2. In FIG. 2, the delay unit 209 can be replaced with a ring-shaped RAM having a predetermined capacity, or can be replaced with a FIFO.
3. Although the filter 202 is used in FIG. 2, the delay amount has a fixed value, so that time coincidence between the signals is achieved with the video component processing circuit that processes the output data of the A / D converter. Things are usually done.
4). Although the Sync tip average value calculation unit and the pedestal average value calculation unit are provided independently, it is also possible to use one average value calculation unit and store each average value at different timings in a register.
5. If the input analog video signal contains a lot of noise components and jitter is generated in the horizontal sync separation signal by the above method, the input analog video signal itself can be obtained by the above method if the jitter is minimal. In addition, the corrected pixel counter is not directly used for the horizontal coordinate of the data representing the video, but is provided separately from the counter used for the horizontal coordinate of the data representing the video, and the corrected pixel counter. There is also a method of synchronizing with the input while taking the jitter at the time of detection. Such a method is used in frame synchronizers, TBCs and the like and is publicly known.
[0062]
【The invention's effect】
As described above, according to the present invention, a quantized digital signal is input, and a horizontal synchronization component signal is extracted by comparison with a predetermined fixed threshold value, and the horizontal coordinate for each quantized sample is represented by the leading edge of this signal. Start horizontal coordinate generation and set the horizontal synchronization part to 0 _H Waveform storage / playback unit that temporarily stores and outputs quantized sample values near the reference point, calculates the average value of quantized samples during the period representing the tip and pedestal level of the horizontal synchronization part, and outputs the midpoint of both A reference level generation unit that compares the output of the waveform storage and reproduction unit with the reference, determines the relationship between the midpoint level point and the reproduced sample value, and has a correction data generation unit for correcting the horizontal coordinates. Therefore, the phase of the video signal with respect to the synchronization signal can be accurately restored.
[0063]
The correction data generation unit for correcting the horizontal coordinate outputs an integer part of the correction data in units of sampling clock to the horizontal coordinate correction unit, and the decimal part of the correction data is the system clock signal. Since it is output to the generator, the phase of the sampling clock is set to 0 in the horizontal synchronization part. _H The phase can be controlled so as to sample the reference point.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an SCH in the RS-170A standard of an NTSC television signal.
FIG. 2 is a block diagram illustrating the gist of the present invention, and is a block diagram illustrating horizontal synchronous coordinate control in the digital processing circuit of the present embodiment.
FIG. 3 is a diagram for explaining an operation of horizontal synchronous coordinate control shown in FIG. 2;
FIG. 4 is a diagram illustrating a quantization sample value of a synchronization start portion stored in a waveform storage / playback unit.
FIG. 5 is an enlarged view of a part of FIG. 4, and is a diagram for explaining the operation of the correction data generation unit in more detail.
6 is a diagram illustrating a configuration of a PLL that inputs a fractional part of phase error data of the pixel counter and the correction data generation unit illustrated in FIG. 1;
[Explanation of symbols]
201 A / D converter
202 Filter
203 Fixed value slice part
204 Timing generator
205 Sync Tip average value calculator
206 Pedestal average value calculator
207 Calculation unit
209 Delay part
210 Waveform memory playback unit
211 Correction data generator
212 pixel counter
A _FIX The address of the first quantized sample output in the fixed value slice part
A _C Quantized sample value below the midpoint level of the sync component
C _FIX First quantized sample value output in fixed value slice part
S _C Address of the quantized sample that falls below the midpoint level of the synchronous component
S _C-1 S _C Quantized sample value before
S _ref Midpoint level of synchronous component
601 Voltage controlled crystal oscillator
602 Self-propelled counter
603 subtractor
604 Error signal generator
605 Adder

Claims (6)

An A / D converter that inputs an analog video signal and converts the analog video signal into a quantized sample signal according to a sampling clock including a synchronization portion and a video portion of the analog video signal;
Horizontal sync separation means for extracting a horizontal sync component signal by inputting the quantized digital signal and comparing it with a predetermined threshold;
A horizontal coordinate generating means for receiving a horizontal coordinate for each quantized sample of the quantized sample signal in response to an output from the horizontal sync separating means;
Waveform storage / reproducing means for temporarily receiving and outputting a plurality of continuous quantized sample values in the vicinity of the 0 _H reference point of the horizontal synchronizing portion of the quantized sample signal in response to the output from the horizontal synchronizing separation means;
A quantized sample value output from the A / D converter is input, and a period representing a leading end portion of a horizontal synchronizing portion and a pedestal level portion in a blanking period are received in response to an output from the horizontal synchronizing separating means. SYNC slice level setting means for calculating the average value of the quantized samples in each period and determining the midpoint of the two average values;
A plurality of consecutive quantized sample values output from the waveform storage / reproducing means and the midpoint level output from the SYNC slice level setting means are compared, and a sample having the midpoint level and a plurality of samples are compared. Correction data generating means for determining a relationship with the quantized sample value and outputting correction data;
Horizontal coordinate correction means for correcting the output of the horizontal coordinate generation means based on correction data from the correction data generation means;
A digital video processing circuit comprising: Phase adjustment means for inputting correction data and performing phase adjustment including a delay or phase advance of less than one clock of the quantized sample signal;
The correction data generating means includes a clock unit difference between the quantized sample value that is compared with the midpoint level and a plurality of consecutive quantized sample values and the quantized sample extracted by the horizontal sync separating means, If not, the difference in clock units between one quantized sample of two consecutive quantized samples including the midpoint level value and the quantized sample extracted by the horizontal sync separator is an integer part. The digital data according to claim 1, wherein the correction data is output to the horizontal coordinate correction unit and the amount of deviation from the one quantized sample is output to the phase adjustment unit as correction data of a decimal part. Video processing circuit. A system clock signal generating means for generating an error signal based on the horizontal coordinate data corrected by the correcting means and output from the horizontal coordinate generating means, and generating the sampling clock signal;
The correction data generation means outputs an integer part of the correction data in units of the sampling clock to the horizontal coordinate correction means, and outputs a decimal part of the correction data to the system clock signal generator, The system clock signal generating means receives the fractional part from the correction data generating means and superimposes it on the error signal so that the phase of the sampling clock becomes the 0 _H reference point of the horizontal synchronization portion of the quantized sample signal. 3. The digital video processing circuit according to claim 2, wherein the digital video processing circuit is controlled. A digital video processing circuit including an A / D converter that inputs an analog video signal and converts the analog video signal into a quantized sample signal according to a sampling clock including a synchronization portion and a video portion of the analog video signal. In the video processing method,
A horizontal sync separation step of extracting a horizontal sync component signal by inputting the quantized digital signal and comparing it with a predetermined threshold;
A horizontal coordinate start step for starting generation of horizontal coordinate data representing a horizontal coordinate for each quantized sample of the quantized sample signal based on the horizontal sync component signal extracted in the horizontal sync separating step;
A waveform storage step of receiving a horizontal synchronization component signal extracted in the horizontal synchronization separation step and temporarily storing a plurality of consecutive quantized sample values near a 0 _H reference point of a horizontal synchronization portion of the quantized sample signal;
A quantized sample value output from the A / D converter is input, and a period representing a leading end portion of a horizontal synchronizing portion and a pedestal level portion in a blanking period are received in response to an output from the horizontal synchronizing separating means. A SYNC slice level setting step for calculating an average value of quantized samples in each period and determining a midpoint between the two average values;
The midpoint output from the SYNC slice level setting means by inputting a plurality of continuous quantized sample values near the 0 _H reference point of the horizontal synchronization portion of the quantized sample signal stored by the waveform storing step A correction data generation step of comparing a level, determining a relationship between a sample having the midpoint level and a plurality of the quantized sample values and outputting correction data;
A digital video processing comprising a horizontal coordinate correction step for correcting an output of horizontal coordinate data started in the horizontal coordinate generation step based on correction data representing the relationship from the correction data generation step Method. A phase adjustment step of inputting correction data and performing phase adjustment including a delay or phase advance of less than one clock of the quantized sample signal;
The correction data generation step includes a clock unit difference between the quantized sample value that is compared with the midpoint level and a plurality of consecutive quantized sample values and the quantized sample extracted by the horizontal sync separator, If not, an integer part of the difference in clock units between one quantized sample of two consecutive quantized samples including the midpoint level value and the quantized sample extracted in the horizontal sync separation step The digital data according to claim 4, wherein the correction data is output to the horizontal coordinate correction step, and the amount of deviation from the one quantized sample is output to the phase adjustment step as decimal correction data. Video processing method. The video processing circuit further includes a system clock signal generator that generates an error signal based on horizontal coordinate data output from the horizontal coordinate generation means and generates the sampling clock signal,
The determining step includes a step of outputting an integer part of the correction data in units of the sampling clock to the horizontal coordinate correcting unit and outputting a decimal part of the correction data to the system clock signal generator,
The system clock signal generator receives the fractional part from the correction data generation step and superimposes it on the error signal so that the phase of the sampling clock becomes the 0 _H reference point of the horizontal synchronization portion of the quantized sample signal. 6. The digital video processing method according to claim 5, wherein the digital video processing method is controlled as follows.

Images