JP3121493B2 - Horizontal sync signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronizing signal generator, and more particularly to a horizontal synchronizing signal generator used for digital video equipment such as EDTV.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 7, a horizontal synchronizing separation circuit used in analog video equipment is provided with a noise removing device 22 for removing noise from a video signal 100 input from an input terminal 1, and a noise removing device 22 for removing noise. A frequency separation circuit 23 for extracting a horizontal frequency component 102 from the separated video signal 101, a synchronization separation circuit 24 for separating a component equal to or less than a predetermined threshold value as a horizontal synchronization signal 103, and a separated horizontal synchronization signal 103
A phase comparator 25 that compares the phase of an output pulse 104 oscillated by the horizontal oscillation circuit 26, a horizontal oscillation circuit 26 controlled by a phase difference component 105 output from the phase comparator 25, An output terminal 27 from which an output pulse 104 is output as a horizontal synchronizing signal HD.

Next, the operation of this conventional example will be described.

[0006] A video signal 100 is input from an input terminal 1, and the noise of the video signal 100 is removed by a noise removing device 22. A horizontal frequency component 102 is extracted from the video signal 101 from which noise has been removed by a frequency separation circuit 23, and components of the extracted horizontal frequency component 102 that are equal to or less than a predetermined threshold value are extracted by a synchronization separation circuit 24 into the horizontal synchronization signal 10.
3. The separated horizontal synchronizing signal 103
Is compared with the output pulse 104 oscillated by the horizontal oscillation circuit 26 by the phase comparator 25. The horizontal oscillation circuit 2 is controlled by the phase difference component 105 output from the phase comparator 25.
6 is controlled, and the output pulse 10 from the horizontal oscillation circuit 26 is controlled.
4 is output from the output terminal 27 as the horizontal synchronization signal HD.

Next, a conventional horizontal sync separation circuit used in digital video equipment will be described with reference to FIG.

The horizontal sync separation circuit includes an A / D converter 21 for A / D converting an analog video signal 100 input from the input terminal 1 into a digital video signal 106, and a video signal input from the input terminal 1. A clock signal generating circuit 3 which generates a clock signal CLK having a frequency four times the frequency of the chrominance carrier locked to the 100 burst signals and supplies the clock signal CLK to each section as an operation clock of the system or a sampling clock of the A / D converter 21; A low-pass filter 28 for removing components equal to or greater than the color subcarrier of the video signal 106 quantized by the D converter 21, and an output 10 of the low-pass filter 28
7 is compared with a preset level, for example, a half level of the pedestal level, and a sync separation circuit 29 that separates a signal lower than that level as a sync signal 108, and a pulse width of the separated sync signal 108 is a predetermined width or more. Pulse width detector 30 which outputs as synchronization signal 109 when
And a periodicity detection circuit 31 that detects a cycle of the synchronization signal 109 and outputs a signal having a predetermined cycle as a horizontal synchronization pulse from the output terminal 11.

Next, the operation of the conventional example of the horizontal sync separation circuit will be described.

A video signal 100 is input from an input terminal 1, the video signal 100 is converted into a digital video signal 106 by an A / D converter 21, and a burst of the video signal 100 input by a clock signal generation circuit 3. A clock signal CLK having a frequency four times the frequency of the chrominance carrier locked to the signal is generated and supplied to each section as a system operation clock and a sampling clock of the A / D converter 21. The low pass filter 28 removes the components of the video signal 106 quantized by the A / D converter 21 which are higher than the color subcarrier, and the output 107 of the low pass filter 28 is set to a predetermined level, for example, a pedestal by the sync separation circuit 29. A signal lower than the half level is separated as a synchronization signal 108. When the pulse width of the synchronization signal 108 separated by the pulse width detector 30 becomes equal to or more than a predetermined width, the synchronization signal 109 is output as a synchronization signal 109, and the period of the synchronization signal 109 is detected by the periodicity detection circuit 31 to determine the predetermined period. The held signal is output from the output terminal 11 as a horizontal synchronization pulse.

However, the horizontal synchronization separation circuit shown in FIG. 8 has a problem that some jitter is generated due to the influence of noise or the like, so that stability cannot be obtained. Therefore, means for obtaining the stability of the horizontal synchronization signal will be described with reference to FIG. The same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted.

The periodicity detection circuit 31 is connected to a horizontal period value memory 32 for storing a horizontal period value 110 output from the detection circuit 31 as a clock count value. A cycle difference determination circuit 33 for determining whether or not the difference 111 between the cycle values within 32 is within a predetermined value is connected. Horizontal cycle value memory 32
The horizontal cycle value averaging circuit 34 outputs an average horizontal cycle value 113 obtained by averaging a plurality of horizontal cycle values in the memory 32 under the control of the output 112 of the cycle difference determination circuit 33. Are connected to the periodicity detection circuit 31 and the horizontal period value averaging circuit 34. The output synchronization signal 114 output from the periodicity detection circuit 31 and the averaging circuit 3
A horizontal synchronizing pulse generation circuit 35 that outputs a horizontal synchronizing pulse from the output terminal 11 based on the average horizontal cycle value 113 output from the output terminal 4 is connected.

Next, the operation of the conventional example of the horizontal sync separation circuit will be described.

A video signal 100 is input from an input terminal 1, the video signal 100 is converted into a digital video signal 106 by an A / D converter 21, and a burst signal of the video signal 100 input by a clock signal generation circuit 3. Clock signal CL of 4 times the frequency of the color carrier locked to
K is generated and supplied to each unit as an operation clock of the system and a sampling clock of the A / D converter 21.
The low-pass filter 28 removes components of the video signal 106 which have been quantized by the A / D converter 21 and more than the color subcarrier, and the sync separation circuit 29 removes the low-pass filter 28.
Is compared with a preset level, for example, half of the pedestal level, and a signal lower than that level is separated as a synchronization signal 108. When the pulse width of the synchronization signal 108 separated by the pulse width detector 30 is equal to or greater than a predetermined width, the synchronization signal 108 is output as a synchronization signal 109,
The period of the synchronization signal 109 is detected by the periodicity detection circuit 31, and a signal having a predetermined period is output to the horizontal synchronization pulse generation circuit 35 as the horizontal synchronization signal 114, and
The horizontal period value 110 output from the detection circuit 31 by the horizontal period value memory 32 is stored as a clock count value. The cycle difference determination circuit 33 determines whether or not the difference 111 between the cycle values in the memory 32 is within a predetermined value, and the horizontal cycle value averaging circuit 34 controls the output 112 of the cycle difference determination circuit 33 to The average horizontal cycle value 113 obtained by averaging the horizontal cycle values for a plurality of cycles is output.
The horizontal synchronization pulse generation circuit 35 generates the periodicity detection circuit 31.
A horizontal synchronizing pulse is output from the output terminal 11 based on the output synchronizing signal 114 output from the averaging circuit 34 and the average horizontal cycle value 113 output from the averaging circuit 34.

However, the horizontal synchronization separation circuit shown in FIG. 9 has a problem that the circuit configuration becomes complicated.

[0014]

The digital video equipment such as the second generation EDTV has a high performance and a high stability enough to control up to the pixel position in order to reproduce the augmented signal compressed in the time domain. A horizontal sync separation circuit is required. For example, the color subcarrier frequency fsc (frequency subcarrie
In the case of sampling at four times r), it is necessary to always fix the number of sample pixels from the horizontal 910 sample points counted from the fall of the horizontal synchronization. Therefore, if only the analog sync separation circuit as shown in FIG.
When a jitter occurs due to noise or the like, a synchronizing signal that cannot fix the sampling point cannot be obtained.

The digital sync separation circuit shown in FIGS. 8 and 9 has a pulse width,
It is necessary to provide a circuit for detecting the periodicity of the pulse width and a circuit for averaging the horizontal period value and a memory circuit for controlling the pixel position. Therefore, the circuit scale becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is a horizontal synchronizing signal generator capable of improving the stability of a horizontal synchronizing pulse enough to control a pixel position while being a simple device. The purpose is to provide.

[0017]

According to the present invention, the above object is achieved by a separating means for separating a horizontal synchronizing signal from an input video signal, and one of the changing positions of the horizontal synchronizing signal is determined every horizontal period. Position detection means for detecting and accumulating one of the detected change positions for a predetermined period to generate a maximum displacement position detection pulse at a position where the frequency becomes maximum, and the input video signal reset by the detection pulse and And a horizontal synchronizing pulse generating means for receiving the synchronizing pulse and outputting a horizontal synchronizing pulse by receiving the synchronizing pulse and outputting a horizontal synchronizing pulse. This is achieved by one horizontal synchronizing signal generator.

According to the present invention, the above object is attained by the horizontal synchronizing signal generator according to claim 2, wherein one of the change positions is a falling position.

According to the present invention, the above-mentioned object is achieved by the position detecting means, comprising: extracting means for generating a falling pulse which becomes high at the falling of the horizontal synchronizing signal; Cumulative means for accumulating the falling pulses to determine the frequency of the position of the falling pulse, and generating means for generating a pulse at the falling position where the frequency of the falling pulse is maximum as a maximum displacement position detection pulse. 4. The horizontal synchronizing signal generator according to claim 3, wherein said horizontal counter means comprises: generating means for generating said clock signal; and a horizontal counter reset by said maximum displacement position detection pulse and counting said clock signal. Achieved.

According to the present invention, the object is to obtain a delay difference between the generated maximum displacement position detection pulse and the outputted horizontal synchronization pulse, and when the delay difference is smaller than a predetermined value, the maximum difference is obtained. The apparatus further includes control means for controlling the displacement position detection pulse not to reset the horizontal counter means, and controlling the maximum displacement position detection pulse to reset the horizontal counter means when the delay difference is larger than a predetermined value. This is achieved by the horizontal synchronizing signal generator according to claim 4.

According to the present invention, it is an object of the present invention to accumulate and average a horizontal synchronizing signal portion of an input video signal for a predetermined period, delay the accumulatively averaged horizontal synchronizing signal portion by one clock, and accumulate the signal. Output means for outputting a pulse corresponding to the peak position of the difference signal of the averaged horizontal synchronization signal portion as a peak detection pulse; and counting a clock signal reset by the peak detection pulse and generated from the input video signal. 6. A horizontal synchronizing signal generator according to claim 5, further comprising horizontal counter means for generating a synchronizing pulse for each horizontal cycle count, and horizontal synchronizing pulse generating means for receiving said synchronizing pulse and outputting a horizontal synchronizing pulse. Achieved.

According to the present invention, the object is as described above, wherein the output means adds A / D conversion means for converting an input video signal into a digital signal, and the converted digital signal for a predetermined period. Accumulating means for averaging in the predetermined period and outputting a cumulative average signal; a signal obtained by delaying the cumulative average signal by one clock; and a differential means for outputting a difference signal of the output cumulative average signal; And a peak detecting means for detecting a peak of the clock signal, wherein the horizontal counter means includes a generating means for generating the clock signal, and a horizontal counter reset by the peak detection pulse and counting the clock. 6 horizontal synchronizing signal generators.

According to the present invention, the above object is to obtain a delay difference between the peak detection pulse and a horizontal synchronization pulse, and when the delay difference is smaller than a predetermined value, the peak detection pulse resets the horizontal counter means. 8. The horizontal synchronizing signal generator according to claim 7, further comprising comparison control means for controlling the horizontal detection means so that the peak detection pulse is reset when the delay difference is larger than a predetermined value. Is done.

[0024]

According to the horizontal synchronizing signal generator of the first aspect, the horizontal synchronizing signal is separated from the video signal inputted by the separating means, and the falling or rising position of the horizontal synchronizing signal separated by the position detecting means is horizontal. A pulse is detected for each period, and a pulse at a position where the rising edge is maximized by accumulating for a predetermined period is generated. The pulse generated by the horizontal counter means is used as a reset signal, and the clock signal is counted. An output pulse is generated, and a horizontal synchronization pulse is generated by the horizontal synchronization pulse generation means based on the output pulse output from the horizontal counter means. Thus, the falling position of the horizontal synchronizing signal is detected by using the principle of majority decision, so that the stability of the horizontal synchronizing pulse can be improved as far as the pixel position can be controlled.

According to the horizontal synchronizing signal generator of the third aspect, the extracting means generates a falling pulse which becomes high at the falling of the horizontal synchronizing signal, and the accumulating means generates the falling pulse for a predetermined period. The cumulative addition is performed to determine the frequency at the position of the falling pulse. The generating means generates a pulse at the falling position where the frequency of the falling pulse is maximum as a maximum displacement position detection pulse. The generating means generates a clock signal. The horizontal counter is reset by the maximum displacement position detection pulse and counts the clock signal. Thus, the falling position of the horizontal synchronizing signal is detected by using the principle of majority decision, so that the stability of the horizontal synchronizing pulse can be improved as far as the pixel position can be controlled.

According to a fourth aspect of the present invention, the control means compares the maximum displacement position detection pulse corresponding to the falling position of the horizontal synchronization signal with the horizontal synchronization pulse output from the horizontal counter means. If the delay difference is smaller than a predetermined value, the maximum displacement position detection pulse is controlled not to reset the horizontal counter means, and if the delay difference is larger than a predetermined value, the maximum displacement position detection pulse resets the horizontal counter means. Control. Therefore, even when the synchronization such as a noise or a flutter failure is temporarily out of synchronization, the horizontal counter means continuously counts, and the stability of the horizontal synchronization pulse can be improved as the pixel position can be controlled. . When synchronization is lost, as in the case of synchronization discontinuity, reset is performed.

According to the horizontal synchronizing signal generator of the fifth aspect, the output means accumulates the video signal for a predetermined period every horizontal synchronizing, and outputs the horizontal synchronizing signal of the accumulated video signal and its falling or rising by one clock. A difference signal from the delayed signal is obtained, a peak of the difference signal is detected, a pulse at the detected peak position is generated, and a pulse generated by the pulse generation means by the horizontal counter means is used as a reset signal. In addition, the clock signal is counted and an output pulse is generated every horizontal cycle count, and a horizontal synchronization pulse is generated by the horizontal synchronization pulse generation means based on the output pulse output from the horizontal counter means. Therefore, regardless of the performance of the horizontal sync separation circuit, the stability of the horizontal sync pulse can be improved as far as the pixel position can be controlled.

According to the horizontal synchronizing signal generator of the sixth aspect, the A / D converter converts the input video signal into a digital signal. The accumulating means adds the converted digital signals for a predetermined period, averages the signals for a predetermined period, and outputs a cumulative average signal. The difference means outputs a signal obtained by delaying the accumulated average signal by one clock and a difference signal of the outputted accumulated average signal. The peak detecting means detects a peak of the difference signal.
The generating means generates a clock signal. The horizontal counter is reset by the peak pulse and counts the clock. Therefore, regardless of the performance of the horizontal sync separation circuit, the stability of the horizontal sync pulse can be improved as far as the pixel position can be controlled.

According to the seventh aspect of the invention, the control means compares the peak detection pulse corresponding to the falling position of the horizontal synchronization signal with the horizontal synchronization pulse output from the horizontal counter means, If the difference is equal to or less than a predetermined value, control is performed so that the peak detection pulse does not reset the horizontal counter means. If the delay difference is equal to or more than the predetermined value, control is performed so that the peak detection pulse resets the horizontal counter means. Therefore, even when the synchronization such as a noise or a flutter failure is temporarily out of synchronization, counting is continuously performed by the horizontal counter means, and the stability of the horizontal synchronization pulse can be improved as far as the pixel position can be controlled. .
When synchronization is lost, as in the case of synchronization discontinuity, reset is performed.

[0030]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a horizontal synchronizing signal generator according to the present invention. An object of the present embodiment is to provide a horizontal synchronizing signal generating device which can improve the stability of a horizontal synchronizing pulse while being a simple device.

In the present embodiment, as shown in FIG. 1, a horizontal synchronizing signal HD as shown in FIG. 2B is converted from an input video signal 100 as shown in FIG. A horizontal synchronization separation circuit 2 as separation means for separation, and a clock signal C having a frequency four times the frequency of the color carrier locked to the burst signal of the video signal 100 input from the input terminal 1
A clock signal generating circuit 3 that generates LK and supplies it to each unit as an operation clock of the system is provided. The horizontal synchronization separation circuit 2 is connected to a falling extraction circuit 7 that generates a pulse that becomes “H” at the falling position of the separated horizontal synchronization signal HD. FIG. 2 shows that the falling position of the synchronizing signal is detected every horizontal period, and the falling is maximized during a predetermined period.
A falling position detecting circuit 12 as a pulse generating means for generating a pulse at a position as shown in FIG. The position detection circuit 12 detects the falling pulse position over several tens of lines set in advance as shown in FIG.
A position accumulating circuit 8 for accumulating the position of the gate pulse as shown in (d), and a pulse at the position where the frequency of the falling pulse becomes the maximum is a falling detection pulse 11.
5 and a pulse generating circuit 9 which outputs the pulse signal as a signal 5.

The clock signal generation circuit 3 counts the clock signal and outputs an output pulse 1 for each horizontal cycle count.
The horizontal counter 5 is connected to the horizontal counter 5 as a horizontal counter means for generating a reset pulse RST. The reset counter selection circuit 4 supplies a falling detection pulse 115 as a reset pulse RST. A gate pulse generating circuit 6 for generating a gate pulse which becomes "L" several seconds before and after, and a horizontal synchronization for generating a horizontal synchronization pulse as shown in FIG. 2E based on an output pulse 116 output from the horizontal counter 5 A horizontal synchronization pulse generation circuit 10 as a pulse generation means is connected. The horizontal synchronizing pulse generated by the generating circuit 10 is output from an output terminal 11.

Next, the operation of this embodiment will be described with reference to the time chart of FIG.

A video signal 100 is supplied from an input terminal 1 to a horizontal sync separation circuit 2 and a clock generation circuit 3. The horizontal sync signal HD shown in FIG. 2B is separated from the video signal 100 shown in FIG. As shown in FIG. 2C, the falling extraction circuit 7 sets "H" at the falling position of the horizontal synchronizing signal HD.
Is generated, and this pulse is supplied to the falling position detection circuit 12 and the reset pulse selection circuit 4.

The video signal 1 is generated by the clock signal generation circuit 3.
A clock signal CLK having a frequency four times the frequency of the color carrier locked to the burst signal 00 is generated. At the start of the operation of the device, the falling pulse from the falling extraction circuit 7 is output from the reset pulse selection circuit 4 to the reset pulse RS.
It is output to the horizontal counter 5 as T. Horizontal counter 5
Then, when the reset pulse RST becomes "H", the count value is reset and counted up by the clock signal. The counter 5 is reset every time counting is performed at a frequency four times the frequency of the chrominance carrier locked to the burst signal, that is, for 910 clock cycles. Counter 5
Is supplied to the gate pulse generation circuit 6 and the horizontal synchronization pulse generation circuit 10. As shown in FIG. 2D, the horizontal synchronizing signal HD is generated by the gate pulse generation circuit 6.
Is supplied to the falling position detecting circuit 12 for several μsec before and after the falling of the gate. As shown in FIG. 2E, a pulse at the falling position "L" is output by the horizontal synchronization pulse generation circuit 10 as a horizontal pulse.

The falling pulse accumulating circuit 8 of the falling position detecting circuit 12 accumulates the position of the falling pulse in the gate pulse over several tens of lines set in advance. For example, the position accumulation circuit 8 can be realized by a circuit configuration in which a falling pulse is cumulatively added for each gate pulse. When the accumulation of the preset number of lines is completed, the accumulated addition result is supplied to the maximum falling pulse generation circuit. The pulse at the position where the frequency of the falling pulse is maximum by the maximum falling pulse generation circuit 9 is supplied to the reset pulse selection circuit 4 as a falling pulse. For example, if the result of the cumulative addition of the falling pulse is as shown in FIG. 2F, the peak position is the point of the maximum frequency of the falling position. Is generated as follows. After the falling detection pulse is generated, the reset pulse selecting circuit 4 selects the detection pulse from the falling detection unit 12 as the reset pulse RST.
The horizontal counter 5 is reset. Its horizontal counter 5
2 from the output signal of FIG.
A horizontal synchronization pulse as shown in (h) is generated.

Next, the falling position accumulating circuit 8 is shown in FIG.
It will be described based on. When the system is operating with a system clock of 4 fsc and the power is turned on, the 910 clock delay circuit 203 is reset and the internal value becomes 0. A falling pulse that is 1 at the falling position of the horizontal synchronization signal and 0 at other positions is input from the input terminal 201. The number of lines to be accumulated is determined in advance. In the adder 202, the output of the adder is added to the signal delayed by 910 clocks, and the result is input to the 910 clock delay circuit 203. When the prescribed number of lines have been accumulated, the output of the adder indicates the frequency at which a falling pulse exists at each sample point. Gate pulse is "H"
A signal indicating the frequency of the falling is output from the terminal 206 through the gate circuit 204 for a period of about ten clocks before and after the pixel where the falling pulse exists.

Next, the maximum falling pulse generation circuit 9 will be described with reference to FIG. The comparison circuit 214 compares the value stored in the maximum value memory 213 with the value input from the input terminal 211, and when the input value is large,
The "H" output is supplied to the maximum value memory 213 and the maximum value pulse generation circuit 215. The maximum value memory 213 determines that the signal input to the comparison circuit is larger than the stored value.
The input signal value is stored as a new maximum value. The maximum value pulse generation circuit 215 determines the last position where the comparison output becomes “H” while the gate pulse is “H”,
Alternatively, a pulse is generated after a constant clock and output from the output terminal 216.

Next, the operation of the reset pulse selection circuit 4 will be described.

(1) When power is turned on, falling extraction circuit 7
Is selected as the reset pulse.

(2) The reset pulse is not supplied to the horizontal counter 5 so that the position of the gate pulse does not change until the maximum falling pulse is generated.

(3) After the falling position detecting circuit 12 generates a maximum falling pulse by accumulating several tens of lines, the pulse is supplied to the horizontal counter 5 as a reset pulse.

According to the present embodiment, even if there is some jitter in the horizontal synchronization signal output from the horizontal synchronization separation circuit, the position of the majority at the rising edge is used as the reset pulse of the horizontal counter, so that it is possible to control the pixel position. The stability of the horizontal synchronization pulse can be improved.

Hereinafter, an embodiment of the horizontal synchronizing signal generator according to claim 5 will be described with reference to FIG. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. An object of the present embodiment is to provide a horizontal synchronizing signal generating device which can improve the stability of a horizontal synchronizing pulse while being a simple device.

In this embodiment, an A / D converter 21 for A / D converting a video signal 100 input from the input terminal 1 is provided.
An accumulation circuit 16 as accumulation means for accumulating and adding the / D-converted video signal for a predetermined period every horizontal synchronization;
A difference circuit 19 for obtaining a difference signal between the horizontal synchronizing signal of the video signal accumulated by the above and a signal obtained by delaying the falling or rising of the signal by one clock, and detecting the peak of the difference signal obtained by the difference circuit 19 And a peak detecting circuit 20 as a peak detecting means. The accumulator 16 adds the video signal quantized by the A / D converter 21 and the output of the delay circuit 14 to the adder 13.
A delay circuit 14 for delaying the quantized video signal by one horizontal period, and a frequency multiplier 15 for multiplying the output of the adder by 1 / n.
It is composed of The difference circuit 19 includes an accumulation circuit 16
And a subtractor 18 for subtracting the video signal delayed by one clock by the latch 17 from the video signal cumulatively averaged by the accumulation circuit 16. I have.

Next, the operation of this embodiment will be described with reference to the time chart of FIG.

A video signal 100 as shown in FIG. 4A is supplied from an input terminal 1 to an A / D converter 21 and a horizontal sync separation circuit 2.
And supplied to the clock generation circuit 3. The horizontal synchronization signal HD shown in FIG. 4B is separated from the video signal 100 shown in FIG. As shown in FIG. 4C, the falling extraction circuit 7 generates a pulse which becomes "H" at the falling position of the horizontal synchronizing signal HD. The clock signal generation circuit 3 generates a clock signal CLK having a frequency four times the frequency of the color carrier locked to the burst signal of the video signal 100. At the start of the operation of the device, the falling pulse from the falling extraction circuit 7 is output to the horizontal counter 5 by the reset pulse selection circuit 4 as the reset pulse RST. In the horizontal counter 5, when the reset pulse RST becomes "H", the count value is reset and counted up by the clock signal. The counter 5 is reset every time counting is performed at a frequency four times the frequency of the chrominance carrier locked to the burst signal, that is, for 910 clock cycles. The count output of the counter 5 is supplied to a gate pulse generation circuit 6 and a horizontal synchronization pulse generation circuit 10. The gate pulse generating circuit 6 supplies a gate pulse in which several μsec before and after the falling of the horizontal synchronizing signal HD becomes “L” to the accumulation circuit 16, the difference circuit 19, and the peak detection circuit 20 as shown in FIG. You. As shown in FIG. 4E, the horizontal synchronizing pulse generating circuit 10 outputs a pulse which becomes "L" at the falling position as a horizontal pulse.

The video signal quantized by the A / D converter 21 in the section in which the gate pulse is "L", that is, in the section before and after the fall of the horizontal synchronizing signal, is delayed by the adder 13 of the accumulating circuit 16 by the adder 13. 14 and is added to the signal delayed by one horizontal period. When the accumulation for several tens of lines set in advance is completed, the accumulated signal is multiplied by 1 / n by the multiplication circuit 15 as shown in FIG.

In the difference circuit 19, the video signal accumulated and averaged is delayed by one clock by the latch 17, and the video signal accumulated and averaged by the accumulation circuit 16 is subtracted from the video signal delayed by one clock by the subtracter 18. 4 (h) is supplied to the peak detection circuit 20. The peak detection circuit 20 detects the peak of the difference signal in the gate pulse, and the detected position is shown in FIG.
Is generated. After the peak detection pulse is generated, the reset pulse selection circuit 4
, The detection pulse from the falling detection unit 12 is selected as the reset pulse RST, and the horizontal counter 5 is reset. A horizontal synchronizing pulse is generated by the horizontal synchronizing pulse generating circuit 10 from the output signal of the horizontal counter 5 as shown in FIG.

Therefore, according to the present embodiment, regardless of the performance of the horizontal sync separation circuit, the stability of the horizontal sync pulse can be improved as far as the pixel position can be controlled.

Hereinafter, an embodiment of the horizontal synchronizing signal generator according to claim 4 will be described with reference to FIG. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. An object of the present embodiment is to provide a horizontal synchronizing signal generating device which can improve the stability of a horizontal synchronizing pulse while being a simple device.

In this embodiment, a pulse corresponding to the falling position of the horizontal synchronizing signal is compared with an output pulse output from the horizontal counter 5. If the comparison value is equal to or larger than a predetermined value, the horizontal synchronizing signal is compared. A pulse corresponding to the rising position of the horizontal counter is input as a reset signal of the horizontal counter 5, and when the comparison value is equal to or smaller than a predetermined value, the comparison control circuit 22 for controlling the reset pulse selection circuit 4 so as not to input the reset signal to the horizontal counter. Have.

Next, the operation of this embodiment will be described with reference to the time chart of FIG.

A video signal 100 as shown in FIG. 6A is supplied from an input terminal 1 to a horizontal sync separation circuit 2 and a clock generation circuit 3. As shown in FIG.
The horizontal synchronizing signal HD as shown in FIG. 6B is separated from the video signal 100 as shown in FIG. The horizontal synchronizing signal H as shown in FIG.
A pulse that becomes “H” is generated at the falling position of D,
This pulse is supplied to the falling position detection circuit 12 and the reset pulse selection circuit 4.

The video signal 1 is generated by the clock signal generation circuit 3.
A clock signal CLK having a frequency four times the frequency of the color carrier locked to the burst signal 00 is generated. At the start of the operation of the device, the falling pulse from the falling extracting circuit 7 is selected by the reset pulse selecting circuit 4, and when a falling detection pulse accumulated over several tens of lines is input, it is selected as the reset pulse RST. The horizontal counter 5 is reset. The horizontal synchronizing pulse generating circuit 10 operates according to the count output of the counter 5 as shown in FIG.
A horizontal synchronization pulse as shown in (d) is generated. The falling detection pulse and the horizontal synchronization pulse are supplied to the comparison control circuit 2
2 and the selection control signal C from the comparison control circuit 22
ON is supplied to the reset pulse selection circuit 4.

After the once accumulated falling detection pulse is sent out as the reset pulse RST, the comparison control circuit 22 starts the next accumulated falling detection pulse after the next accumulated falling detection pulse.
As shown in (f), the delay difference between the falling detection pulse and the horizontal synchronization pulse is obtained, and the delay difference is set to a predetermined value T.
If it is less than k, this shift is regarded as a jitter due to noise or the like, and the selection control signal Con is set so that the falling detection pulse is not supplied to the horizontal counter 5 as the reset pulse RST so that horizontal synchronization is not unstable. It is output to the reset pulse selection circuit 4. Horizontal counter 5
Will continue to be counted in the same phase at 910 clock cycles. If the delay difference is larger than the set value, the comparison control circuit 22 determines that the horizontal synchronization signal is shifted due to synchronization discontinuity or the like, and supplies a falling detection pulse to the horizontal counter 5 as a reset pulse. 4 is controlled.

For example, as shown in FIG. 6 (f), the time of Δt before and after the horizontal synchronizing pulse as shown in FIG.
Is generated. FIG. 6 (g)
When the falling detection pulse exists in the gate as shown in the above, the reset pulse selection circuit 4 is controlled by the comparison control circuit 22 so that the reset pulse is not generated from the reset pulse selection circuit 4. When the falling detection pulse does not exist in the gate as shown in FIG. 6H, the reset control circuit 22 controls the reset pulse selection circuit 4 so that the reset pulse selection circuit 4 does not generate the reset pulse. . Note that a gate signal may be generated from the falling detection pulse to detect whether or not the horizontal synchronization pulse is within the gate.

Accordingly, even when the tuning is temporarily disturbed due to noise, flutter failure, or the like, the horizontal counter counts continuously, and the stability of the horizontal synchronizing pulse can be improved. If there is an out-of-synchronization such as at the time of discontinuity of synchronization, a reset is performed again.

In the above-described embodiment, an example is shown in which the comparison control circuit 22 is added to the horizontal synchronizing signal generator of claim 1, but the present invention is not limited to this. The same effect can be obtained even when added to the signal generator.

In the above embodiment, the comparison control circuit 22
Is used to compare the horizontal synchronization pulse with the accumulated falling detection pulse of the synchronization signal, but the present invention is not limited to this, and the horizontal synchronization pulse may be compared with the falling detection pulse of the synchronization signal before accumulation.

In the above embodiment, the description has been made using the falling edge of the synchronization signal. However, the present invention is not limited to this, and the rising edge of the synchronization signal may be used. The same effect can be obtained even if an analog circuit or a digital circuit is used for the sync separation circuit 2.

[0062]

According to the horizontal synchronizing signal generator of the first aspect, even if the horizontal synchronizing signal output from the horizontal synchronizing separation circuit has some jitter, the position of the majority decision at the rising edge is used as the reset pulse of the horizontal counter. As a result, the stability of the horizontal synchronization pulse can be improved as far as the pixel position can be controlled.

According to the horizontal synchronizing signal generator of the third aspect, even if the horizontal synchronizing signal output from the horizontal synchronizing separation circuit has some jitter, the position of the majority at the rising edge is used as the reset pulse of the horizontal counter. The stability of the horizontal synchronization pulse can be improved as far as the pixel position can be controlled.

According to the horizontal synchronizing signal generator of the present invention, even when the tuning is temporarily disturbed due to noise, flutter failure, or the like, the horizontal counter counts continuously, thereby improving the stability of the horizontal synchronizing pulse. Can be improved.
If there is an out-of-synchronization such as at the time of discontinuity of synchronization, a reset is performed again.

According to the horizontal synchronizing signal generator of the fifth aspect, the stability of the horizontal synchronizing pulse can be improved as far as the pixel position can be controlled, regardless of the performance of the horizontal synchronizing separation circuit.

According to the horizontal synchronizing signal generator of the fifth aspect, regardless of the performance of the horizontal synchronizing separation circuit, the stability of the horizontal synchronizing pulse can be improved as far as the pixel position can be controlled.

According to the horizontal synchronizing signal generator of the present invention, even when the tuning is temporarily disturbed due to noise, flutter failure, etc., the horizontal counter counts continuously, and the stability of the horizontal synchronizing pulse is improved. Can be improved.
If there is an out-of-synchronization such as at the time of discontinuity of synchronization, a reset is performed again.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a horizontal synchronizing signal generator according to claim 1;

FIG. 2 is a time chart showing the operation of the embodiment of the horizontal synchronizing signal generator of claim 1;

FIG. 3 is a block diagram showing a configuration of an embodiment of a horizontal synchronization signal generator according to claim 5;

FIG. 4 is a time chart showing the operation of the embodiment of the horizontal synchronizing signal generator according to claim 5;

FIG. 5 is a block diagram showing a configuration of an embodiment of a horizontal synchronizing signal generator according to claim 4;

FIG. 6 is a time chart showing the operation of the embodiment of the horizontal synchronizing signal generator according to claim 4;

FIG. 7 is a block diagram showing a configuration of an embodiment of a conventional horizontal sync separation circuit.

FIG. 8 is a block diagram showing a configuration of an embodiment of a conventional horizontal sync separation circuit.

FIG. 9 is a block diagram showing a configuration of a conventional horizontal sync separation circuit.

FIG. 10 is a block diagram showing a configuration of a falling position accumulating circuit according to claim 3;

FIG. 11 is a block diagram showing a configuration of a maximum falling pulse generation circuit according to claim 3;

[Explanation of symbols]

 2 Horizontal sync separation circuit 4 Reset pulse selection circuit 5 Horizontal counter 7 Fall extraction circuit 8 Fall position accumulation circuit 9 Fall pulse generation circuit 10 Horizontal synchronization pulse generation circuit 12 Rise position detection circuit 13 Adder 14 Delay circuit 15 Multiplication circuit 16 Accumulation circuit 17 Latch 18 Subtractor 19 Difference circuit 20 Peak detection circuit 22 Comparison control circuit

Claims (7)

(57) [Claims] 1. A separating means for separating a horizontal synchronizing signal from an input video signal, detecting one of changing positions of the horizontal synchronizing signal every horizontal period, and accumulating one of the detected changing positions for a predetermined period. Position detecting means for generating a maximum displacement position detection pulse at a position where the frequency is maximum, and counting a clock signal generated from the input video signal, reset by the detection pulse, and counting every one horizontal cycle. A horizontal counter means for generating a synchronization pulse; and a horizontal synchronization pulse generating means for receiving the synchronization pulse and outputting a horizontal synchronization pulse. 2. The horizontal synchronizing signal generator according to claim 1, wherein one of the change positions is a falling position. 3. The position detecting means for extracting a falling pulse which becomes a high level at the falling of the horizontal synchronizing signal, and a cumulative addition of the falling pulse for a predetermined period, Accumulating means for calculating the frequency of the position of the falling pulse, and generating means for generating a pulse at the falling position at which the frequency of the falling pulse is the maximum as a maximum displacement position detection pulse, wherein the horizontal counter means comprises: Generating means for generating a clock signal, reset by the maximum displacement position detection pulse,
3. The horizontal synchronizing signal generator according to claim 2, further comprising a horizontal counter that counts the clock signal. 4. A delay difference between the generated maximum displacement position detection pulse and the output horizontal synchronization pulse is obtained, and when the delay difference is smaller than a predetermined value, the maximum displacement position detection pulse is output to the horizontal counter means. 4. The control device according to claim 1, further comprising control means for controlling not to reset the horizontal counter means when the delay difference is larger than a predetermined value. A horizontal synchronization signal generator according to claim 1. 5. A horizontal synchronization signal portion of an input video signal is cumulatively averaged for a predetermined period, and a difference between a signal obtained by delaying the cumulatively averaged horizontal synchronization signal portion by one clock and the cumulatively averaged horizontal synchronization signal portion. Output means for outputting a pulse corresponding to the peak position of the signal as a peak detection pulse; and a clock signal reset by the peak detection pulse and generated from the input video signal and synchronized with each horizontal cycle count A horizontal synchronizing signal generating apparatus comprising: horizontal counter means for generating a pulse; and horizontal synchronizing pulse generating means for receiving the synchronizing pulse and outputting a horizontal synchronizing pulse. 6. An A / D converter for converting an input video signal into a digital signal, adding the converted digital signal for a predetermined period, averaging the converted digital signal for the predetermined period, and performing a cumulative average. Accumulating means for outputting a signal; a signal obtained by delaying the accumulated average signal by one clock; and a difference means for outputting a difference signal of the outputted accumulated average signal; and peak detecting means for detecting a peak of the difference signal. 6. The horizontal synchronizing signal generator according to claim 5, wherein said horizontal counter means comprises: generating means for generating said clock signal; and a horizontal counter reset by said peak detection pulse and counting said clock. . 7. A delay difference between the peak detection pulse and the horizontal synchronization pulse is obtained, and if the delay difference is smaller than a predetermined value, control is performed so that the peak detection pulse does not reset the horizontal counter means. 7. The horizontal synchronizing signal generator according to claim 5, further comprising comparison control means for controlling the peak detection pulse to reset the horizontal counter means when is larger than a predetermined value.