JP2004048088A - Signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the degradation of an S/N ratio, the generation of beat noise or the missing of teletext data to be multiplexed in a blanking period, in a signal processor which A/D converts a video signal, performs YC separation or time axis correction in synchronism with a horizontal synchronizing signal, and so on. <P>SOLUTION: An output signal of an A/D conversion circuit 2 sampled in a free run clock (27 MHz) is interpolated into sampling data of 4 fsc by a first interpolation filter 3 on the basis of interpolation position information of 27 MHs and a burst-locked clock 4 fsc calculated by a first interpolation phase calculating circuit 6. The resulted signal is processed with the 4 fsc in a Y/C separation circuit 4, and then is restored into the original state of 27 MHz by a second interpolation filter 13 on the basis of interpolation phase information of the 4 fsc and 27 MHz calculated in a second interpolation phase calculating circuit 14. In this way, D/A conversion can be applied to the signal without passing the signal through a frame synchronizer 11, and the signal can be output as an analog signal (luminance signal and color signal). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal processing device that converts an analog video signal into a digital signal, and then separates the signal into a luminance signal and a chrominance signal, and performs processing such as time axis correction synchronized with a horizontal synchronization signal.
[0002]
[Prior art]
In recent years, devices that convert an analog video signal into a digital video signal and record or reproduce digital data that is digitally compressed by a method such as MPEG2 (Moving Picture Experts Group Phase 2) have been released. In these devices, a composite video signal input from an analog tuner or an external input terminal is separated into a luminance signal (hereinafter, referred to as Y signal) and a modulated chrominance signal (hereinafter, referred to as C signal), and the C signal is subjected to color difference. After demodulation into a signal, the signal is input to an MPEG2 encoder (encoding device) together with the Y signal and subjected to digital compression processing. Also, as an analog signal output from the device, it has an S video output terminal and has a function of outputting a Y signal and a C signal as analog signals.
[0003]
Hereinafter, a conventional signal processing device will be described.
[0004]
FIG. 4 shows a first configuration example of a conventional signal processing device. In FIG. 4, 1 is an analog video signal input terminal, 2, 22, and 23 are analog-to-digital conversion circuits (hereinafter, referred to as A / D conversion circuits), and 4 is a luminance that separates a composite video signal into a Y signal and a C signal. A signal / color signal separation circuit (hereinafter, referred to as a Y / C separation circuit), 5 is a burst phase detection circuit for detecting the phase of the color burst signal, and 24 is a clock synchronized with the phase of the color burst signal (for example, 4 fsc, where fsc is a burst lock clock generation circuit for generating a color subcarrier frequency, 15 and 16 are digital / analog conversion circuits (hereinafter referred to as D / A conversion circuits), 10 is a synchronization signal removal circuit, and 7 is a color difference A color demodulation circuit for demodulating the signal, a frame synchronizer for performing a time axis correction, and a digital signal for outputting a digital signal composed of a luminance signal and a color difference signal; Power terminal, an analog Y signal output terminal 17, 18 analog C signal output terminal, 19 is a free run clock generation circuit for generating a predetermined frequency clock (e.g., 27 MHz).
[0005]
The operation of the conventional signal processing device configured as described above will be described.
[0006]
The composite video signal input from the analog video signal input terminal 1 is converted into a digital signal by the A / D conversion circuit 2 by the burst locked clock output from the burst lock clock generation circuit 24. The converted digital signal is separated into a Y signal and a C signal by a Y / C separation circuit 4 and then converted into an analog Y signal and an analog C signal by D / A conversion circuits 15 and 16, respectively. The signal is output from a signal output terminal 17 and an analog C signal output terminal 18. The burst phase detection circuit 5 detects a phase shift of the color burst signal included in the C signal output from the Y / C separation circuit 4 with respect to the clock. The burst lock clock generation circuit 24 corrects the clock frequency in the direction to correct the deviation, thereby establishing a lock state (synchronization state) between the color burst signal and the clock, and securing the separation performance in the Y / C separation circuit 4. are doing.
[0007]
The analog Y signal and the analog C signal output from the D / A conversion circuits 15 and 16 are converted into digital signals by the clock output from the free-running clock generation circuit 19, and the Y signal is converted into a synchronization signal by the synchronization signal removal circuit 10. Is removed, and the C signal is demodulated into a color difference signal by the color demodulation circuit 7 and then input to the frame synchronizer 11. The frame synchronizer 11 writes the Y signal and the color difference signal from which the synchronization signal has been removed into the frame memory based on the horizontal and vertical synchronization signals of the Y signal, and outputs the frame memory at the standard horizontal and vertical scanning periods created from the free-run clock. , The digital signal is output from the digital signal output terminal 12 as a standard digital signal, and is compressed by an MPEG encoder or the like at the subsequent stage.
[0008]
FIG. 5 shows a second configuration example of a conventional signal processing device. In FIG. 5, reference numeral 3 denotes a first interpolation filter, 6 denotes a first interpolation phase calculation circuit, 8 denotes a third interpolation filter, 9 denotes a third interpolation phase calculation circuit, 20 denotes a synchronization signal addition circuit, and 21 denotes color. Modulation circuit. The difference from the first configuration example is that the first interpolation phase calculation circuit 6 calculates the phase of the burst lock clock with respect to the free-run clock instead of directly feeding back the burst lock to the sampling clock of the A / D converter. The first interpolation filter 3 generates sampling data based on the burst lock clock based on the sampling data based on the free-run clock. Since the data rate after the interpolation is set lower than the data rate before the interpolation, the interpolated burst lock data discretely exists in the free-run clock. Therefore, a signal indicating the presence or absence of the burst lock data is output from the first interpolation phase calculation circuit 6. The processing circuit based on the burst lock clock, such as the Y / C separation circuit 4 at the subsequent stage, performs the same processing as the burst lock clock by loading and holding the processing circuit with this signal. In the third interpolation phase calculation circuit 9, an interpolation phase from the burst lock frequency to the free-run clock is calculated, interpolated by the third interpolation filter 8, and returned to the sampling data of the free-run clock frequency. Since the calculation of the interpolation phase by the third interpolation phase calculation circuit 9 is performed with a finite number of digits, sometimes the input data and the calculated interpolation data become inconsistent due to error integration, and a waveform is distorted. . Therefore, by resetting the third interpolation phase calculation circuit 9 in the horizontal blanking interval, the distortion is driven into the blanking period, and the frame synchronizer 11 absorbs the distortion together to solve the problem. The analog output terminals 17 and 18 are supported by using a signal corrected to continuous data by the frame synchronizer 11. Since no synchronization signal is added to the output signal of the frame synchronizer 11, the synchronization signal is added by the synchronization signal adding circuit 20. Further, the color difference signal is modulated by the color sub-carrier by the color modulation circuit 21, and is converted into a modulated color signal before being output.
[0009]
[Problems to be solved by the invention]
However, in the above-described first configuration example, since the analog signal is once returned to the analog signal by the D / A converters 15 and 16 and then A / D converted again, the signal-to-noise ratio (S / N) deteriorates. When the burst lock clock component included in the signal to be A / D converted is sampled by the free-run clock, a beat of the frequency difference of the clock is generated. Further, in the above-described second configuration example, since the blanking data is dropped when passing through the frame synchronizer 11, there is a problem that teletext data multiplexed in the vertical blanking period is not output. I was
[0010]
The present invention solves the above-mentioned conventional problem. After performing a burst lock operation such as Y / C separation using a free-running clock, it is possible to extract analog data without performance deterioration due to beats or data loss during a blanking period. The present invention provides a signal processing device capable of performing the following.
[0011]
[Means for Solving the Problems]
In order to solve this problem, a signal processing device according to the present invention includes an A / D conversion circuit that samples an analog signal at a first sampling frequency and converts the analog signal into a digital signal, and a predetermined value for each first sampling frequency. A first interpolation phase calculation circuit for calculating an interpolation phase at a second sampling frequency by adding, and interpolating a digital signal into sampling data at a second sampling frequency based on an output of the first interpolation phase calculation circuit A first interpolation filter, a processing circuit for performing predetermined processing on an output of the first interpolation filter at a second sampling frequency, and a second interpolation frequency based on an output of the first interpolation phase calculation circuit. A second interpolation phase calculation circuit for calculating an interpolation phase at a first sampling frequency for the sampling data, and a second interpolation phase calculation And a second interpolation filter for interpolating an output signal processing circuit based on the output of the circuit to the sampling data at the first sampling frequency.
[0012]
By setting the reference values of the first and second interpolation phase calculation circuits to the same value, there is no error accumulation, and the data can be completely returned to continuous data. It is possible to perform D / A conversion without performing correction processing and output the analog signal. For this reason, occurrence of beat noise, missing blanking data, and the like can be eliminated.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
The signal processing device according to the present invention samples an analog signal at a first sampling frequency and converts the analog signal into a digital signal, and adds a predetermined value for each of the first sampling frequencies to thereby obtain a second signal. A first interpolation phase calculation circuit for calculating an interpolation phase at a sampling frequency of, and the digital signal is interpolated into data sampled at the second sampling frequency based on an output of the first interpolation phase calculation circuit. A first interpolation filter, a processing circuit for performing a predetermined process on an output of the first interpolation filter at the second sampling frequency, and a second circuit based on an output of the first interpolation phase calculation circuit. Calculating an interpolation phase at the first sampling frequency for data sampled at the sampling frequency of An interphase calculation circuit, and a second interpolation filter for interpolating an output signal of the processing circuit to data sampled at the first sampling frequency based on an output of the second interpolation phase calculation circuit. Things.
[0014]
Further, in the above invention, in the first interpolation phase calculation circuit, the predetermined value added for each first sampling frequency is a fixed value obtained by a ratio between a first sampling frequency and a second sampling frequency; The processing circuit detects the phase between the color subcarrier of the video and the processing clock, and is generated based on a correction value obtained from the phase difference.
[0015]
Further, in the above invention, the processing circuit includes a process of separating the composite video signal into a luminance signal and a modulated chrominance signal.
[0016]
In the above invention, the processing circuit includes a process of converting the modulated color signal into a low-frequency color signal.
[0017]
In the above invention, a third interpolation phase detection circuit that does not depend on the first interpolation phase calculation circuit and an output of the third interpolation phase detection circuit perform an interpolation of an output signal of the processing circuit. Of the present invention.
[0018]
According to the above invention, after converting an analog signal into a digital signal at the first sampling frequency, desired processing such as separation into a luminance signal and a modulated chrominance signal is performed at the second sampling frequency, and the first processing is performed again. Since the signal is converted to a digital signal of the sampling frequency, the signal can be converted back to an analog signal without deterioration in performance due to occurrence of a beat or loss of data inserted during a blanking period.
[0019]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
(Embodiment)
FIG. 1 is a block diagram illustrating a configuration of a signal processing device according to an embodiment of the present invention.
[0021]
In FIG. 1, reference numeral 1 denotes an analog video signal input terminal to which a composite video signal is input, and 2 denotes a converter for converting a composite video signal input from the analog video signal input terminal 1 into a digital signal by a free-running clock (for example, 27 MHz). A / D converter 3 is a first interpolation filter for converting a digital signal sampled with the free-run clock output from the A / D converter 2 into sampling data at the frequency of the burst clock, and 4 is a first interpolation filter. A Y / C separation circuit for separating the digital composite video signal output from the filter 3 into a luminance signal (Y signal) and a modulated chrominance signal (C signal), 5 denotes a color burst signal from the C signal output from the Y / C separation circuit 4 A burst phase detection circuit for detecting the phase of the burst clock and outputting information for correcting a phase error with respect to the burst clock; A first interpolation phase calculation circuit for calculating a phase of a burst clock (for example, 4 fsc = 14.31818 MHz) with respect to the free-run clock based on the phase information from 5 and outputting the calculated result to the first interpolation filter 3; A color demodulation circuit 8 for demodulating the C signal output from the separation circuit 4 to obtain a color difference signal, and 8 receiving the Y signal output from the Y / C separation circuit 4 and the color difference signal output from the color demodulation circuit 7, A third interpolation filter for converting a sampling frequency to a free-running clock frequency, and a third interpolation phase calculation 9 for calculating an interpolation phase in the third interpolation filter 8 independently of the first interpolation phase calculation circuit 6 A circuit 10 is a synchronizing signal removing circuit for removing a synchronizing signal component from the Y signal output from the third interpolation filter 8, and 11 is a synchronizing signal removing circuit which outputs A frame synchronizer for inputting a color difference signal output from the interpolation filter and removing time axis fluctuation; a digital signal output terminal 12 for outputting a digital Y signal output from the frame synchronizer 11 and a color difference signal; and 13 for Y / C separation A second interpolation filter for inputting the Y signal of the output of the circuit 4 and the color difference signal of the output of the color demodulation circuit 7 and converting a sampling frequency from a burst clock frequency to a free-run clock frequency, and 14 is a second interpolation filter A second interpolation phase calculation circuit for calculating the interpolation phase in 13 based on the data from the first interpolation phase calculation circuit 6; 15 converts the Y signal from the second interpolation filter 13 into an analog signal with a free-run clock A D / A conversion circuit 21 for converting the color difference signal from the second interpolation filter 13 into a C signal; A D / A converter circuit for converting a C signal from the modulation circuit 21 into an analog signal using a free-run clock, and 19 is a free-run clock generation circuit for generating a free-run clock.
[0022]
As described above, the difference between the present embodiment and the second configuration example in the conventional signal processing device is that the second embodiment is based on the sampling phase reference value used in the first interpolation phase calculation circuit 6. The interpolation phase calculation circuit 14 calculates the interpolation phase, and the second interpolation filter 13 interpolates the signal after Y / C separation and color demodulation into complete continuous data on a free-run clock without error accumulation. It is a point. In this case, since the synchronization signal is still added, the color difference signal is converted back to a C signal by the color modulation circuit 21 and converted to an analog signal by the D / A conversion circuit 16 to obtain a Y / C separated Y signal. A C signal can be output.
[0023]
FIG. 2 is a block diagram showing a configuration of the first interpolation phase calculation circuit 6 and the second interpolation phase calculation circuit 14 when using 4 fsc (14.31818 MHz) as a burst lock clock frequency and 27 MHz as a free-run clock. It is.
[0024]
In FIG. 2, reference numeral 30 denotes an input terminal to which a correction value for a burst phase shift is input from the burst phase detection circuit 5. 31, 36, 39 are fixed values, 32, 33 are adders, 34, 35, 42 are registers, 37 is subtractors, 38, 41, 45 are dividers, 40 is multipliers, 43, 44, 46 are outputs Terminal. The output terminal 43 receives a load / hold signal to a circuit operated by the burst lock clock, the output terminal 44 receives interpolation phase information for controlling the first interpolation filter 3, and the output terminal 46 receives the second interpolation filter 13. Interpolation phase information to be controlled is output.
[0025]
Fixed value 31 indicates the value of 14.31818 / 27 × ^{2 32} in hexadecimal. This value is added to the value of the register 34 having a 32-bit width by the adders 32 and 33 for each free-run clock, thereby providing a common reference value for the interpolation phase. The interpolation phase of each interpolation filter is calculated based on the reference value.
[0026]
Hereinafter, the operation of the signal processing device according to the present embodiment will be described with reference to FIG.
[0027]
FIG. 3A shows a sampling waveform in the A / D conversion circuit 2. In the figure, black circles indicate phases actually sampled by the free-run clock (27 MHz), and FIG. 2B shows sampled data values (x0 to x7). Also, white circles in the diagram of FIG. 4A indicate sampling phases in the burst lock clock (4 fsc) to be interpolated, and FIG. 4C shows data values (X0 to X4). In the circuit shown in FIG. 2, the period of the burst lock clock is divided and managed by a value of 2 32. This division number N means the period of the phase shift of the burst lock clock. In the case of N division, the worst case is that the burst lock clock is one clock in the free-run clock period × N (when the color subcarrier is 4 fsc, the division is N). (90 degrees in phase). Therefore, it is necessary to select the value of N so that the value of the free-running clock cycle × N becomes sufficiently large with respect to the response speed of the burst lock mechanism.
[0028]
Fixed value 31 of FIG. 2, 14.31818 / 27 × ^{2 32} values, i.e., the value of the free run clock cycle when the 32 squares of 2 burst lock clock cycle, the value for each free run clock The sum is stored in the register 34 of FIG. At the time of addition, when the value exceeds 2 to the 32nd power, that is, when the sampling point of the black circle exceeds the sampling point of the white circle in FIG. 3A, it means that the sampling point of the burst lock clock exists. I have. At this time, since the carry is output from the adder 33 in FIG. 2, the carry is output from the output terminal 43 via the register 35 as a load hold signal. This load hold signal is shown in FIG. Although FIGS. 3D to 3F actually have a clock delay caused by a register, the delay is corrected for ease of understanding the correspondence with FIG. 3A.
[0029]
First, the operation of the first interpolation phase calculation circuit 6 will be described with reference to an example of calculating the interpolation phase of the data indicated by X2 in FIG. X2 of the interpolation phase, when the free-run clock period is ^Tx, a (2 32 -T3) / Tx. Setting the resolution of the interpolation filter 10 bits (1024 division), since it is ^{Tx = 2 32 × 14.31818 / 27} , 1024 × (2 32 -T3) / Tx = {(2 32 -T3) / 2 22 {× {1024 × 27 / (2 × 14.31818)} / 2 ⁹ .
[0030]
Fixed value 39 of FIG. 2 is a value showing a 1024 × 27 / (2 × 14.31818 ) in hexadecimal, after multiplier 40, is 1/2 ⁹ in divider 41, via the registers 42 Output from the output terminal 44. FIG. 3F shows the value of the interpolation phase information for each sampling point.
[0031]
Next, the operation of the second interpolation phase calculation circuit 14 will be described. The value of the register 34 of FIG. 2 shows the case in which the period of 14.31818MHz ^{2 32,} the phase value of the 27MHz clock directly. Therefore, when the resolution of the interpolation filter is set to 2 to the power of M, the upper M bits of the register 34 may be obtained. Since the resolution of the interpolation filter is set to 10 bits, it is output from an output terminal 46 after being set to ^1/22 (2 ⁻²² ) by a divider 45. FIG. 3E shows the value of the interpolation phase information for each sampling point.
[0032]
As described above, both the interpolation and the inverse interpolation phase calculation are based on the value of the register 34 shown in FIG. 2, so that the rate of the interpolated data to be sent always matches the inverse interpolation phase information calculation. Does not occur.
[0033]
However, since the circuits to be processed by the burst lock each have a circuit delay, when the correction value from the burst phase detection circuit 5 changes, the interpolation reference in the first interpolation filter 3 and the second interpolation filter 13 Will be slightly different during the circuit delay. Although there is almost no effect on the luminance signal, the C signal may be detected as a change in hue. For this reason, color demodulation is performed before the second interpolation filter 13 to return to a free-running clock by interpolation processing as a color difference signal.
[0034]
As described above, according to the present embodiment, the first interpolation phase calculation circuit 6 that calculates the interpolation phase at the burst lock clock frequency by adding the fixed value 31 for each free-run clock frequency, A first interpolation filter 3 for interpolating an output signal of the A / D conversion circuit 2 based on an output of the interpolation phase calculation circuit 6, a Y / C separation circuit 4 for processing an output of the first interpolation filter 3, A second interpolation phase calculation circuit for calculating an interpolation phase at a free-running clock frequency of data sampled at a burst lock clock frequency based on an output of the first interpolation phase calculation circuit; With the configuration of the second interpolation filter 13 that interpolates the output signal of the Y / C separation circuit 4 based on the output of the calculation circuit 14, the sampling is performed with the free-run clock. The signal is converted into a signal by the burst lock clock, and after performing desired processing with the burst lock clock, the signal can be completely restored to the original free-run clock. Therefore, the analog signal is subjected to D / A conversion without passing through the frame synchronizer 11. As an output. Therefore, Y / C separation by burst lock can be performed without occurrence of a beat by the burst lock clock, and since there is no need to pass through the frame synchronizer 11, blanking data is not lost.
[0035]
In the above embodiment, the clock frequency, the resolution of the circuit, and the like have been described with specific numerical values. However, it is needless to say that various modifications are possible without being limited to these numerical values.
[0036]
【The invention's effect】
As described above, the signal processing circuit of the present invention adds the predetermined value to the A / D conversion circuit that converts an analog signal into a digital signal by sampling the analog signal at the first sampling frequency. A first interpolation phase calculation circuit for calculating an interpolation phase at the second sampling frequency, and a first interpolation filter for interpolating an output signal of the A / D conversion circuit based on an output of the first interpolation phase calculation circuit And a processing circuit that performs processing at the second sampling frequency, and calculates an interpolation phase at the first sampling frequency of data sampled at the second sampling frequency based on an output of the first interpolation phase calculation circuit. A second interpolation phase calculation circuit, and a second interpolation filter for interpolating an output signal of the processing circuit based on an output of the second interpolation phase calculation circuit By interpolating the signal sampled at the first sampling frequency to the second sampling frequency, performing desired processing at the second sampling frequency, and then returning to the original first sampling frequency Since the data can be completely restored, D / A conversion can be performed without passing through the frame synchronizer, and the signal can be output as an analog signal. Therefore, processing such as Y / C separation at the second sampling frequency can be performed without occurrence of a beat at the second sampling frequency, and a frame synchronizer that removes the vertical blanking period and performs time axis correction. Since there is no need to pass the data, there is an excellent effect that data inserted during the vertical blanking period is not lost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a signal processing device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a first interpolation phase calculation circuit and a second interpolation phase calculation circuit in the signal processing device. FIG. 3 is a waveform diagram for explaining the operation of the signal processing device. FIG. 4 is a block diagram showing a first configuration example of a conventional signal processing device. FIG. 5 is a second configuration of a conventional signal processing device. Block diagram showing an example [Description of reference numerals]
Reference Signs List 1 analog signal input terminal 2 A / D conversion circuit 3 first interpolation filter 4 Y / C separation circuit 5 burst phase detection circuit 6 first interpolation phase calculation circuit 7 color demodulation circuit 8 third interpolation filter 9 third Interpolation phase calculation circuit 10 Synchronization signal removal circuit 11 Frame synchronizer 12 Digital signal output terminal 13 Second interpolation filter 14 Second interpolation phase calculation circuit 15, 16 D / A conversion circuit 17 Analog Y signal output terminal 18 Analog C signal output Terminal 19 Free-run clock generation circuit 21 Color modulation circuit

Claims (5)

An A / D conversion circuit that samples an analog signal at a first sampling frequency and converts it into a digital signal;
A first interpolation phase calculation circuit that calculates an interpolation phase at a second sampling frequency by adding a predetermined value for each of the first sampling frequencies;
A first interpolation filter that interpolates the digital signal into data sampled at the second sampling frequency based on an output of the first interpolation phase calculation circuit;
A processing circuit for performing a predetermined process on an output of the first interpolation filter at the second sampling frequency;
A second interpolation phase calculation circuit that calculates an interpolation phase at the first sampling frequency with respect to data sampled at the second sampling frequency, based on an output of the first interpolation phase calculation circuit;
A signal processing device comprising: a second interpolation filter that interpolates an output signal of the processing circuit into data sampled at the first sampling frequency based on an output of the second interpolation phase calculation circuit. In the first interpolation phase calculation circuit, the predetermined value added for each first sampling frequency is a fixed value determined by a ratio between the first sampling frequency and the second sampling frequency, and a color of an image in the processing circuit. 2. The signal processing device according to claim 1, wherein the signal processing device detects the phase of the subcarrier and the processing clock, and generates the signal based on a correction value obtained from the phase difference. The signal processing device according to claim 1, wherein the processing circuit includes a process of separating the composite video signal into a luminance signal and a modulated chrominance signal. The signal processing device according to claim 3, wherein the processing circuit includes a process of converting the modulated color signal into a low-frequency color signal. A third interpolation phase detection circuit that does not depend on the first interpolation phase calculation circuit; and a third interpolation filter that interpolates an output signal of the processing circuit based on an output of the third interpolation phase detection circuit. The signal processing device according to claim 1, wherein

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