JP3524817B2 - Burst gate pulse timing correction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TV and a VTR for processing a carrier color signal of the NTSC system. 2. Description of the Related Art In recent years, TVs and home VTRs that perform digital processing of signal processing have increased. In such a system, a burst portion in a carrier chrominance signal of an input signal is extracted, and a frequency fsc = 14.3 MHz which is four times the 3.58 MHz which is a chrominance subcarrier is used.
Is generally synchronized with the burst of the input signal by a PLL. FIG. 3 shows a circuit example. Hereinafter, description will be given with reference to FIG. [0005] The luminance signal or the composite video signal input to the A / D converter is subjected to low-pass filter (hereinafter, LPF) in a sync separation circuit 1 to remove high-frequency noise and color signals.
The PF output is compared with the threshold level, and a period that is equal to or lower than the threshold level is defined as a synchronization signal. The timing of a burst gate pulse (hereinafter abbreviated as BGP) used for burst detection is determined by fixing the values of the H counter 2 and the line counter 3 from the synchronization signal. For example, in the case of a clock of 14.3 MHz,
Approximately 75 to 11 in H counter value from the fall of the synchronization signal
Create BGP6 that is "H" for about 0 clocks,
The color signal in the “H” period is regarded as a burst. The formal color difference signals in the NTSC signal are the I and Q signals, but in the following description,
The U and V signals whose processing is simple will be described as color difference signals. In consumer equipment, U and V signals are generally used. Note that the BY signal is the U signal and the R signal is the R signal.
The -Y signal is the V signal. The carrier chrominance signal is decoded into a UV color difference signal by a decoding circuit 8. An error signal for PLL is generated from a UV level which is a decoding result in the BGP, and an external voltage controlled crystal oscillator (hereinafter, VCXO) is generated. The main clock is phase-locked to the burst by controlling the oscillation phase. If there is a sag, the DC of the sync chip
Since the level rises, timing below the threshold for sync separation is earlier than when there is no sag. For this reason, the interval between the burst and the synchronously separated H becomes long, and the burst may not be included in the BGP. For this reason, in the vertical flyback period with sag, PL
Since L cannot be pulled in, the effect of sag disappears at the upper part of the screen where the effective image starts, and the PLL pulls in, so that the hue differs at the upper part of the screen. [0014] Most of the reproduction signals of a home VTR are analog-processed separately for YC, and therefore, when dubbing is repeated, a YC time shift is likely to occur. Further, the DC component of the synchronizing signal during the vertical blanking period is lost due to the sag, and in this period, the Y signal leads the C signal in time. Therefore, a time lag occurs between the BGP created from the synchronization signal and the actual burst signal, so that the PLL
Is inaccurate, and cannot be demodulated into a color difference signal of a correct level, resulting in color unevenness and hue shift. The color shift cannot be automatically corrected because the shift amount cannot be quantified. The present invention provides means for solving such problems, and the invention of each claim constitutes the following technical means. To achieve the above object, the burst gate pulse timing correction circuit device of the present invention has the following components. A synchronization separation circuit for separating horizontal synchronization and vertical synchronization from the input luminance signal after A / D conversion, horizontal counter means reset by the horizontal synchronization output from the synchronization separation circuit and increasing every clock, Line counter means reset by vertical synchronization and increased every horizontal synchronization, burst discrimination pulse generation circuit means for generating a burst discrimination pulse from the horizontal counter and line counter values, and a decoding circuit for converting an input color signal into a color difference , A low-pass filter for smoothing the output of a decoding circuit, the LPF
Minimum value detection circuit means for detecting a minimum value in a burst determination pulse of the output of the burst determination pulse generation circuit among outputs, and outputting a position in the burst determination pulse at which the minimum value is obtained as a counter value; A difference calculation circuit for calculating a difference between the output of the minimum value detection circuit and the center of BGP;
A variable delay circuit for varying the delay amount of any of the Y and C signals, and by varying the output timing of the BGP generation circuit and the delay amount of the Y or C signal in accordance with the difference value. It is characterized by providing a high-quality image without color unevenness and color shift. FIG. 1 is a block diagram of the present invention. This will be described below with reference to FIG. The input luminance or video signal is converted into a digital value by an AD converter, and the video signal is separated into Y and C by a YC separator 4. A horizontal synchronizing signal (H) and a vertical synchronizing signal (V) are obtained from the luminance or the video signal after the AD by the synchronizing / separating circuit 1. 3 is generated. The burst is 10H to 263 in the case of NTSC.
H, 273H to 525H, the BGP sets the H counter value of the corresponding line to 75 to 10 by default.
A period “H” considering the delay in each circuit to about 7 is output from the six blocks. The separated color signal or the AD input color signal is 7 S
After selecting by W, it is decoded by 8 and UV respectively LPF9, 1
By passing 0, 3.58M carrier components are removed. Since the burst has only a negative U component, the phase relationship between the BGP and the burst can be understood by examining the U level in the BGP after decoding. FIG. 2 shows this state. BGP center and U
Assuming that the difference between the H count and the minimum value of the level is Diff, FIG.
Since the center of the BGP coincides with the minimum value of the U level in the BGP, Diff = 0. When the BGP is advanced with respect to the burst, as shown in FIG. 2B, and when the BGP is delayed, it is as shown in FIG. 2C. In the case of FIG. 2B, Diff is a positive value.
Is a negative value. In the vertical flyback period, sag is likely to occur, and YC
Even if the time is not shifted, the BGP and the burst may not be in phase. In the BGP generation circuit 6, 12 Diff_Is for the vertical blanking period are set to 10H to 21H, 273H to 284.
H, and Diff_V of 13 outputs is applied to the effective image areas of 22H to 263H and 285H to 525H. Each of Diff_I and Diff_V is reset every vertical synchronization, and the first line (D
In the case of if_V, the detection results at 22H and 285H) are held unless a detection result exceeding an allowable error is obtained. When the detection result exceeds the allowable error, Di
The values of both ff_I and Diff_V are updated. Diff
By adding _I and Diff_V to the default BGP start count value and reflecting the result on the next line, the phases of the burst and the BGP match. Since Diff_V is not affected by sag,
Is the main cause of the occurrence. Therefore, by controlling the amount of delay of the Y signal in accordance with the value of Diff_V, the time lag of YC can be corrected. For example, when Diff_V = 3, the delay amount of Y may be delayed by three clocks from the default. According to the present invention described above, the following effects can be obtained. According to the present invention, since the phase relationship between the BGP and the burst is always the same, dubbing is repeated to
Even if the signal has a large time difference of C, or the H signal, which is synchronously separated only for the vertical retrace period due to sag, and the positional relationship between the burst and the H signal, the error signal of the PLL does not become inaccurate and the UV can be demodulated at the correct level. In addition, since the YC time shift can be corrected, it is possible to provide a high-quality image without color unevenness, hue shift, and time shift.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional block diagram showing an embodiment of a burst gate pulse timing correction circuit device according to the present invention. FIG. 2 is an operation explanatory diagram of a burst gate pulse timing correction circuit device according to the present invention. FIG. 3 shows a block diagram of the prior art. [Description of Signs] 1: Sync separation 2: Horizontal counter 3: Line counter 4: Y / C separation 5: SW 6: BGP generation circuit 7: SW 8: Decode circuit 9: Low-pass filter for U 10: Low-pass filter for V 11: minimum value detection circuit 12: vertical flyback period difference value detection circuit 13: effective image difference value detection circuit 14: luminance signal variable delay line 15: phase detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/455 H04N 5/08 H04N 9/77

Claims (1)

(57) [Claims 1] a) A synchronization separation circuit for separating horizontal synchronization and vertical synchronization from an input luminance signal after A / D conversion, and b) a horizontal output from the synchronization separation circuit. Horizontal counter means which is reset by synchronization and increases every clock; c) line counter means which is reset by vertical synchronization and increases every horizontal synchronization; d) a burst discrimination pulse is generated from the values of the horizontal counter and the line counter. E) a decoding circuit for converting an input color signal into a color difference, a low-pass filter for smoothing the output of the decoding circuit, and a burst discrimination pulse output from the burst discrimination pulse generation circuit output of the LPF output. The minimum value detection circuit detects the minimum value of the pulse and outputs the position in the burst discrimination pulse at which the minimum value was obtained as a counter value. F) a difference calculation circuit for calculating a difference between the output of the minimum value detection circuit and the center of the burst discrimination pulse; and g) a variable delay circuit for varying a delay amount of one of the Y and C signals. The present invention provides a high-quality image free from color unevenness and color misregistration by varying the output timing of the burst determination pulse generation circuit and the delay amount of one of the Y and C signals in accordance with the difference value. Characteristic burst gate pulse timing correction circuit device.