JP2001016603A - Correction circuit for timing of burst gate pulse - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image of high quality which is free from color shading, hue slippage and time lag by providing a difference calculation circuit which calculates the difference between the output of a minimum value detection circuit and the center of a burst discriminating pulse, a variable delay circuit which varies the delay of a Y or C signal, etc. SOLUTION: The low-pass filters(LPF) 9 and 10 filter the output of a decoding circuit 8 which converts the input color signals into the color difference. A minimum value detection circuit 11 detects the minimum value of a burst discriminating pulse of the output of a BGP generation circuit 6 from the outputs of the LPFs 9 and 10 and then outputs a position set in the pulse as the counter value. Each of difference calculation circuits 12 and 13 calculates the difference between the output of the circuit 11 and the center of a BGP. A variable delay circuit 14 varies the delay value of a Y or C signal that is separated by a Y/C separation circuit 4. Then the output timing of the circuit 6 and the delay value of the Y or C signal are varied according to the calculated difference value, so that an image of high quality having no color shading nor hue slippage, etc., is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a TV and a VTR for processing carrier color signals of the NTSC system.

[0002]

2. Description of the Related Art In recent years, TVs and home VTRs that perform digital signal processing have increased.

In such a system, a burst portion in a carrier chrominance signal of an input signal is extracted, and a frequency fsc = 14.3 MHz which is four times as high as 3.58 MHz which is a chrominance subcarrier.
Is generally synchronized with the burst of the input signal by a PLL.

FIG. 3 shows an example of a circuit. Hereinafter, description will be made with reference to this figure.

A high-frequency noise and color signals are removed from the luminance signal or the composite video signal input to the A / D converter by a low-pass filter (hereinafter, LPF) in a sync separation circuit 1.
The PF output is compared with the threshold level, and a period that is equal to or lower than the threshold level is defined as a synchronization signal.

The timing of a burst gate pulse (hereinafter abbreviated as BGP) used for detecting a burst is determined by fixing the values of the H counter 2 and the line counter 3 from the synchronization signal.

For example, in the case of a clock of 14.3 MHz,
Approximately 75 to 11 in H counter value from the falling edge of the synchronization signal
Create BGP6 which becomes "H" for about 0 clocks,
The color signal in the “H” period is regarded as a burst.

By the way, although the official color difference signals in the NTSC signal are the I and Q signals, in the following description,
The U and V signals whose processing is simple will be described as color difference signals.

In consumer equipment, U and V signals are generally used. Note that the BY signal is the U signal and the R signal is the R signal.
The -Y signal is the V signal.

The carrier chrominance signal is decoded into a UV color difference signal by a decoding circuit 8. An error signal for PLL is generated from a UV level which is a decoding result in the BGP, and an external voltage controlled crystal oscillator (hereinafter, VCXO) is generated. The main clock is phase-locked to the burst by controlling the oscillation phase of the main clock.

If there is a sag, the DC of the sync chip
Since the level rises, timing below the threshold for sync separation is earlier than when there is no sag.

For this reason, the interval between the burst and H which is synchronously separated becomes long, and the burst may not enter the BGP in some cases.

For this reason, in the vertical flyback period with sag, PL
Since L cannot be pulled in, the effect of sag is eliminated at the upper part of the screen where the effective image starts and the PLL is pulled in, so that the hue differs at the upper part of the screen.

[0014]

Most of the reproduction signals of a home VTR are analog-processed separately for YC, and therefore, when dubbing is repeated, a YC time shift is likely to occur.

Further, the DC component of the synchronizing signal during the vertical blanking period is lost due to the sag, and in this period, the Y signal leads the C signal in time. Therefore, a time lag occurs between the BGP created from the synchronization signal and the actual burst signal, and the PLL
Is inaccurate, and cannot be demodulated into a color difference signal of a correct level, resulting in color unevenness and hue shift. Further, the color shift cannot be automatically corrected because the shift amount cannot be quantified.

[0016]

The present invention provides means for solving such problems, and the invention of each claim constitutes the following technical means.

In order to achieve the above object, a burst gate pulse timing correction circuit device of the present invention has the following components.

A synchronization separation circuit for separating horizontal synchronization and vertical synchronization from the input luminance signal after A / D conversion, and horizontal counter means reset by the horizontal synchronization output from the synchronization separation circuit and increasing every clock; Line counter means reset by vertical synchronization and increased every horizontal synchronization; burst discrimination pulse generation circuit means for generating a burst discrimination pulse from the horizontal counter and line counter values; and a decoding circuit for converting an input color signal into a color difference , A low-pass filter for smoothing the output of a decoding circuit, the LPF
Minimum value detection circuit means for detecting a minimum value in a burst determination pulse of the output of the burst determination pulse generation circuit among outputs, and outputting a position in the burst determination pulse at which the minimum value is obtained as a counter value; A difference calculation circuit for calculating a difference between the output of the minimum value detection circuit and the center of the BGP;
A variable delay circuit for varying the delay amount of any of the Y and C signals, and by varying the output timing of the BGP generation circuit and the delay amount of the Y or C signal in accordance with the difference value. It is characterized by providing a high-quality image without color unevenness and color shift.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of the present invention. This will be described below with reference to FIG.

The input luminance or video signal is converted into a digital value by an AD converter, and the video signal is separated into Y and C by a YC separator 4.

A horizontal synchronizing signal (H) and a vertical synchronizing signal (V) are obtained from the luminance or video signal after AD by the synchronizing separation circuit 1, and an H counter 2 in the horizontal direction from H and a line counter in the vertical direction from HV. 3 is generated.

The burst is 10H to 263 in the case of NTSC.
H, 273H to 525H, the BGP sets the H counter value of the corresponding line to 75 to 10 by default.
The period “H” considering the delay in each circuit to about 7 is output from the block 6.

The separated color signal or the AD input color signal is 7 S
After selecting by W, it is decoded by 8 and UV respectively LPF9, 1
The carrier component of 3.58M is removed by passing 0.

Since the burst has only a negative U component, the phase relationship between the BGP and the burst can be understood by checking the U level in the BGP after decoding.

FIG. 2 shows this state. BGP center and U
Assuming that the difference between the H count and the minimum value of the level is Diff, when the BGP and burst have the same phase, FIG.
Since the center of the BGP coincides with the minimum value of the U level in the BGP, Diff = 0.

When the BGP is advanced with respect to the burst, as shown in FIG. 2B, and when the BGP is delayed, it is as shown in FIG. 2C.

In the case of FIG. 2B, Diff is a positive value.
Is a negative value.

During the vertical blanking period, sag is likely to occur, and YC
Even if the time is not shifted, the phase of the BGP and the burst may not match.

In the BGP generation circuit 6, 12 Diff_Is for the vertical blanking period are set to 10H to 21H, 273H to 284.
H, and 13-output Diff_V is applied to the effective image areas of 22H to 263H and 285H to 525H.

Each of Diff_I and Diff_V is reset every vertical synchronization, and the first line (D
In the case of if_V, the detection results at 22H and 285H) are held unless a detection result exceeding an allowable error is obtained.

When the detection result exceeds the allowable error, Di
The values of both ff_I and Diff_V are updated. Diff
By adding _I and Diff_V to the default BGP start count value and reflecting the result on the next line, the phases of the burst and the BGP match.

Diff_V is not affected by sag, so YC
Is the main cause of the occurrence.

Therefore, by controlling the delay amount of the Y signal in accordance with the value of Diff_V, the time lag of YC can be corrected.

For example, when Diff_V = 3, the delay amount of Y may be delayed by three clocks from the default.

[0035]

According to the present invention described above, the following effects can be obtained.

According to the present invention, since the phase relationship between the BGP and the burst is always the same, dubbing is repeated and Y
Even when a signal having a large time difference of C or an H signal which is synchronously separated only for a vertical retrace period due to sag and a positional relationship between a burst and the burst signal are separated, the error signal of the PLL is not inaccurate and the UV can be demodulated at a correct level. In addition, since the YC time shift can be corrected, it is possible to provide a high-quality image without color unevenness, hue shift, and time shift.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a burst gate pulse timing correction circuit device according to the present invention.

FIG. 2 is an operation explanatory diagram of a burst gate pulse timing correction circuit device according to the present invention.

FIG. 3 shows a block diagram of the prior art.

[Explanation of symbols]

 1: Synchronous separation 2: Horizontal counter 3: Line counter 4: Y / C separation 5: SW 6: BGP generation circuit 7: SW 8: Decoding circuit 9: Low-pass filter for U 10: Low-pass filter for V 11: Minimum value detection Circuit 12: Difference value detection circuit for vertical blanking period 13: Difference value detection circuit for valid image 14: Variable luminance signal delay line 15: Phase detection circuit

Claims (1)

[Claims] 1. a) a synchronization separation circuit for separating horizontal synchronization and vertical synchronization from an input luminance signal after A / D conversion; and b) reset by the horizontal synchronization output from the synchronization separation circuit and increased every clock. C) line counter means reset by vertical synchronization and increased every horizontal synchronization; d) burst determination pulse generation circuit means for generating burst determination pulses from the values of the horizontal counter and the line counter; e) a decoding circuit for converting an input color signal into a color difference, a low-pass filter for smoothing the output of the decoding circuit, and detecting a minimum value in the burst discrimination pulse of the output of the burst discrimination pulse generation circuit among the LPF outputs. Minimum value detection circuit means for outputting the position in the burst discrimination pulse from which the value has been obtained as a counter value; f) the minimum value A difference calculating circuit for calculating the difference between the output circuit output and the center of the burst discrimination pulse; and g) a variable delay circuit for changing the delay amount of one of the Y and C signals. Burst gate pulse timing correction characterized by providing a high-quality image free from color unevenness and color misregistration by varying the output timing of a burst discrimination pulse generation circuit and the delay amount of any of the Y and C signals. Circuit device.