JP2001186376A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal processor generating a picture of superior quality without stretched and contracted pixels by using a line lock clock as a sampling signal on the locking circuit of the line clock used for processing a video signal and the video signal processor generating a sub-carrier frequency based on the line clock locking and generating a color difference signal using a sub-carrier frequency. SOLUTION: A fall detector 3 detects a horizontal synchronizing signal included in the video signal supplied from VTR and a free run counter 5 outputs the count of the number of clocks for one line to a subtracter 30. The subtracter 30 subtracts a reference M from the count value, outputs the result to a correction value conversion circuit 6 through an adder and converts it into correction data. The sine wave output of a sine wave generation circuit 7 is corrected in accordance with correction data and controls the line clock of the video signal affected by the stretch/contraction of a tape is controlled to a corresponding clock. The precise line clock is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for locking a line clock used for processing a video signal, a video for generating a subcarrier frequency based on the line locked clock, and a color difference signal using the subcarrier frequency. The present invention relates to a signal processing device.

[0002]

2. Description of the Related Art Today, color video technology such as television has been developed, and various systems for processing video signals have been adopted. Normally, the video signal is in NTSC format (National
Television System Committee standerd)
The video signal includes a luminance signal (Y signal) indicating luminance, a chrominance signal (C signal) modulated by a subcarrier (subcarrier), a synchronization signal for synchronizing horizontal and vertical, and the subcarrier (sub). Carrier), and a color synchronization signal (color burst) having the same frequency as the carrier. For this reason, on the receiving side (receiver side) that receives and processes the video signal, it is necessary to separate and process the various signals.

FIG. 25 is a system diagram for explaining the processing of the video signal. In the figure, a TV signal is input to a video detector 81 via an intermediate frequency amplifier (IF amplifier), and a video signal including the luminance signal (Y signal), the chrominance signal (C signal), the horizontal and vertical synchronization signals, and the like. (So-called synthesized video signal) is extracted. Then, a part of the video signal is sent to the color subcarrier trap 82, where the color signal (C signal) is removed, and is output to the matrix circuit 84 via the delay line 83. On the other hand, the chrominance signal (C signal) is passed through a band amplifier 85 to an I signal synchronous detector 86 and a Q signal synchronous detector 8.
7 is output. Subcarriers are supplied from the synchronization signal output unit 88 to the I signal synchronization detector 86 and the Q signal synchronization detector 87, and I and Q signals including a color difference signal are created. The I signal is output to the matrix circuit 84 via an I signal low-pass filter (I signal LPF) 89 and a delay line 90, and the Q signal is output via a Q signal low-pass filter (Q signal LPF) 91. Matrix circuit 84
Is output to

In the matrix circuit 84, a luminance signal (Y signal, EY) supplied through a delay line 83 and a delay line 90
Signal (E I) supplied through the I / F and the Q signal (EQ) output from the low-pass filter for Q signal (LPF for Q signal) 91, the red (ER), green (EG), and blue (E
B) Create a color signal.

The synchronizing signal output section 88 comprises a burst extracting circuit 92, a phase comparator 93, a voltage controlled crystal oscillator 94, and a -90 ° phase shifter 95. The burst extracting circuit 92 is included in the video signal. A color burst (color synchronization signal) is extracted and output to the phase comparator 93. Color burst (color synchronization signal) included in video signal
Is inserted in the back porch portion of the horizontal synchronizing signal, and the phase comparator 93 compares the reference signal output from the voltage controlled crystal oscillator 94 with the color burst signal output from the burst extracting circuit 92, and compares the comparison result with an analog signal. The signal is fed back to the voltage controlled crystal oscillator 94 as a signal, and the oscillation output whose phase is controlled is output to the I signal synchronous detector 86. Further, the oscillation output is output to the Q signal synchronous detector 87 via the −90 ° phase shifter 95. I signal synchronous detector 8
In the 6 and Q signal synchronous detector 87, 90
An I signal and a Q signal having a phase difference of ° are created.

[0006]

The above-mentioned conventional video signal processing apparatus has the following problems. (A) First, the voltage-controlled crystal oscillator used in the above-described voltage-controlled crystal oscillator 94 is an analog element, and this circuit also performs analog control in a conventionally used digital video signal processing circuit. However, the standard of subcarriers used for processing a video signal is very strict, and analog control is affected by noise, operation stability is poor, and it is difficult to improve image reproducibility.

(B) On the other hand, a digital voltage controlled oscillator having a plurality of fixed frequency oscillators has also been proposed, but it is difficult to switch the fixed frequency and control the phase shift. In addition, a plurality of fixed-frequency oscillators must be provided, and the circuit scale becomes large. Further, when a subcarrier is generated by switching a fixed frequency oscillator, it is impossible to strictly lock a color burst of an input signal, and problems such as color flow and phase shift occur on a screen.

(C) As described above, in the conventional video signal processing device, the output of the above-described voltage controlled crystal oscillator 94 is used as a system clock. That is, the clock of the subcarrier lock is used as the system clock. In a signal conforming to the NTSC standard, a relationship of an integer multiple is established between the line frequency and the subcarrier frequency, and the relationship of 910 clocks per line is maintained.

However, in a signal that does not conform to the NTSC standard, such as a signal output from a VTR or a signal having a poor reception state, an integer multiple relationship is not established between the subcarrier frequency and the line frequency. Particularly in the case of a VTR, a signal that does not conform to the NTSC standard is often output due to factors such as a motor driving error and expansion and contraction of the tape.

For this reason, in a system such as a video printer that performs a process of writing a video signal to a memory, sampling a video signal using a subcarrier synchronization clock does not necessarily result in 910 samples per line. For example, FIG. 26 illustrates this relationship. FIG. 26A shows a sampling result using a subcarrier lock clock, and FIG. 26B shows a sampling result using a line lock clock. When the subcarrier lock clock is used, the display position of each pixel displayed on the display D has the same period in each line, and the position of the pixel does not change for each line. On the other hand, when the line lock clock is used, the display position of each pixel greatly changes as the line expands and contracts, as shown in FIG.

Therefore, when a video signal fetched from a VTR or the like is sampled based on the subcarrier lock clock, the memory image is bent and the bent image is displayed as shown in FIG. For this reason,
Rather, it is possible to perform appropriate sampling by adjusting the sampling cycle to a different line lock clock for each video signal of the supplied VTR.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a video signal processing apparatus which uses a line lock clock as a sampling signal and creates a high-quality image without expansion or contraction of pixels. .

[0013]

According to the first aspect of the present invention, there is provided a digital sine value generating means for generating a digital sine value in accordance with correction data, and a synchronous signal for detecting a horizontal synchronizing signal contained in a video signal. Signal detecting means, counting means for counting the output of the digital sign value generating means until the synchronization signal detecting means detects the horizontal synchronizing signal and detecting the next horizontal synchronizing signal, Comparing the count result with a reference value, generating correction data in accordance with the comparison result, and outputting the correction data to the digital sine value generation means; and the digital sine value generation means includes a line according to the correction data. This can be achieved by providing a video signal processing device that performs clock locking.

Here, the video signal is a signal supplied from a video reproducing device such as a VTR, and includes a luminance signal and 3.
This is a signal including a color signal, a horizontal and vertical synchronizing signal, a color burst (color synchronizing signal), and the like combined with a subcarrier (subcarrier) of 58 MHz.

The synchronizing signal detecting means detects a horizontal synchronizing signal included in the video signal, and the counting means is a cyclic counter for counting 910, for example.
The output of the digital sign value generation means is counted, and the synchronization signal detection means detects the horizontal synchronization signal and outputs a count result until the next horizontal synchronization signal is detected.

The correction data generating means outputs the counting result (count result) of the counting means to, for example, a subtractor, compares it with a reference value, and generates correction data from the comparison result. The correction data generated by the correction data generating means is output to the digital sine value generating means, and a line clock is locked according to the correction data, and the line lock clock is used as a system clock, for example.

With this configuration, a stable system clock corresponding to the line clock can be obtained even when a video signal from a VTR or the like that is unstable due to expansion and contraction of the tape is supplied.

According to a second aspect of the present invention, there is provided a digital sine value generating means for outputting a subcarrier frequency corrected in accordance with correction data, and a burst position detection for detecting an output timing of a color burst included in a video signal. Means for detecting a color difference signal created according to a subcarrier signal output from the digital sign value generating means, in accordance with the detection timing of the burst position detecting means, a subcarrier signal included in a color burst of the video signal; This can be achieved by providing a video signal processing device having a correction data creating means for making the comparison and creating the correction data.

Here, the digital sine value generating means corrects the frequency of the subcarrier according to the correction data, and outputs a subcarrier matching the line clock. The burst position detecting means is a circuit for detecting the output timing of the color burst included in the video signal, and extracts the timing using, for example, a predetermined pulse signal.

The correction data generator compares the subcarrier signal included in the color burst of the video signal with the color difference signal in accordance with the detection timing of the burst position detector to generate correction data. Then, based on the correction data, a subcarrier signal is created by the digital sign value generating means.

With this configuration, the subcarrier signal output from the digital sine value generating means becomes accurate. When a color difference signal is generated according to the subcarrier, an accurate color difference signal can be generated. it can.

According to an aspect of the present invention, the above object is attained by a first aspect.
A first digital sine value generating means for generating a first digital sine value in accordance with the correction data and locking a line clock; a synchronization signal detection means for detecting a horizontal synchronization signal included in the video signal; Counting means for counting the output of the first digital signature value generating means until the detecting means detects the horizontal synchronizing signal and detecting the next horizontal synchronizing signal; and A first clock data generating means for generating first correction data according to the comparison result and outputting the first correction data to the first digital sine value generating means; A second digital sine value generating means for outputting a subcarrier frequency, and a burst for detecting an output timing of a color burst included in the video signal. A position detecting unit for detecting a color difference signal generated in accordance with a subcarrier signal output from the second digital sign value generating unit, and comparing with a detection timing of the burst position detecting unit; And a second correction data creating means for creating the second correction data, and an addition for adding a result of multiplying the first correction data by -1 to the second correction data creating means. And a color difference signal generation circuit having the means.

This embodiment is an invention in which the line clock lock circuit according to claim 1 and the color difference signal generation circuit according to claim 2 are combined, and in this case, the first correction data output from the line clock lock circuit. The result of multiplying by -1 is added to the second correction data created by the second correction data creation means, and the result is used as second correction data taking into account the change in the line clock.

With such a configuration, a color difference signal can be generated according to more accurate subcarriers, and an image free from image bending and distortion can be output. According to a fourth aspect of the present invention, in the first or the third aspect, the horizontal synchronization signal is detected by using a value at which a signal level included in a video signal maintains a minimum value for a predetermined period as a determination level. It is.

With this configuration, detection of an erroneous horizontal synchronization signal due to noise components such as pulse noise, copy guard, and subcarriers is prevented.

According to a fifth aspect of the present invention, in the first aspect, an error value due to a difference in a falling angle of the horizontal synchronization signal is detected, and information of the error value is included in the correction data. .

According to a sixth aspect of the present invention, in the third aspect, an error value due to a difference in a fall angle of the horizontal synchronization signal is detected, and information of the error value is included in the first correction data. Configuration.

With this configuration, highly accurate synchronization detection becomes possible, and a high-quality image free of distortion and blur can be created. According to a seventh aspect of the present invention, in the first aspect, when the correction data exceeds a certain value, the correction data is restricted.

According to an eighth aspect, in the third aspect, when the first correction data exceeds a certain value,
The first correction data is limited. With this configuration, when a large error occurs between the two signals, it is possible to eliminate a rapid change in the correction data and perform stable line clock lock control.

According to a ninth aspect, in the first or second aspect, a digital filter is used for the digital sine value generating means. According to a tenth aspect of the present invention, in the third aspect, the first and second aspects are different.
A digital filter is used for the digital sine value generating means.

Here, as the digital filter, for example, a digital lag filter, a digital lag read filter and the like are used, and by using such a digital filter, problems such as noise easily affected by an analog circuit can be eliminated. High-quality image data can be created.

[0032] Claim 11 is based on claim 1 or 2 above.
In the above description, the digital sine value generating means has a look-up table for storing a sine value corresponding to the correction data.

According to a twelfth aspect, in the third aspect, the first and second digital sine value generating means store a sine value corresponding to the first or second correction data. This is a configuration having a lookup table.

With this configuration, the first and second digital sine value generating means can easily create a sine value while referring to the look-up table.

According to a thirteenth aspect, in the second aspect, the look-up table stores only data for a quarter cycle of a sine waveform. With this configuration, the memory capacity of the lookup table can be reduced.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a system configuration diagram for explaining a video signal processing apparatus of the present embodiment.

In the figure, a video signal processing device includes a line lock clock generation circuit 1 and a color difference signal generation circuit 2
It is composed of Line lock clock generation circuit 1
Is the falling detector 3, flip-flop (DFF)
4, a free-run counter 5, a correction value converter 6, a digital sine value generation circuit 7, and the like. The color difference signal generation circuit 2 includes a digital sine value generation circuit 8, a band pass filter (BPF) 9, a burst position detection circuit 10,
It comprises a correction value converter 11 and the like.

First, the line lock clock generation circuit 1 will be described. The line lock clock generation circuit 1
As described above, the falling detector 3, the flip-flop (DFF) 4, the free-run counter 5, and the like are provided, and the falling detector 3 is supplied with a video signal. Here, the video signal supplied to the falling detector 3 is, for example, a video signal supplied from a VTR, and the falling detector 3 detects a horizontal synchronizing signal included in the video signal.

FIG. 2 is a diagram for explaining the circuit configuration of the falling detector 3. However, the circuit configuration of FIG. 2 does not output a small error value described later. As shown in FIG. 1, the falling detector 3 includes an analog / digital converter (hereinafter, referred to as an A / D converter) 13, an 8-bit flip-flop (hereinafter, referred to as an 8-bit DFF) 14 to 16, an adder. 17 to 20, a minimum value storage register 21, comparators 22 and 23, an AND gate (AND gate) 24, a DFF 25, and an inverter circuit 26.
The digital signals are converted into digital signals by 3 and sequentially stored in 8-bit DFFs 14 to 16 as digital signals having an 8-bit configuration. The adder 17 outputs the output of the 8-bit DFF 14 and A /
The output of the D converter 13 is added, and the adder 18
The output of the bit DFF 15 is added to the output of the 8-bit DFF 16, and the adder 19 adds the outputs of the adders 17 and 18. Then, the output of the adder 19 is written into the minimum value storage register 21, and the comparator 22 further performs a comparison process with the input value to be input thereafter. If a smaller value is detected, the value of the minimum value storage register 21 is read. Is rewritten. Therefore, with such a configuration, it is possible to store, in the minimum value storage register 21, data in which the addition value of the 8-bit data at least three times is the minimum. Therefore, an erroneous minimum value of the video signal is not stored due to noise elements such as pulse noise, copy guard, and subcarrier.

The adder 20 is a circuit for adding a predetermined value C to the minimum value storage register 21. The adder 20 adds a constant value to the value stored in the minimum value storage register 21 as described later. Stabilize driving. The comparator 23 is a circuit for comparing the output of the adder 20 with the value of the newly input video signal, and supplies the comparison result of the comparator 23 to an AND gate (AND gate) 24. Further, the comparison result of the comparator 23 is supplied to the DFF 25, and after the signal is delayed by the DFF 25 for a certain time, the signal is inverted via the inverter circuit 26 and output to the AND gate (AND gate) 24. An AND gate 24 outputs a falling detection pulse (horizontal synchronization detection pulse) according to the logic of both signals.

For example, the comparator 23 constantly compares the input video signal with a value obtained by adding C to the minimum value stored in the minimum value storage register 21 (judgment level). (L) Output a signal.
On the other hand, when the video signal becomes lower than the determination level, a high (H) signal is output. Therefore, a low (L) signal is output from the comparator 23 while the horizontal synchronization signal is not detected,
A high (H) signal is supplied to one input of an AND gate (AND gate) 24 via the DFF 25 and the inverter circuit 26. In this state, when the output of the comparator 23 is inverted, an AND gate (AND gate) 24
A high (H) signal is also supplied to the other input of, and a falling detection pulse (horizontal synchronization detection pulse) is output from the falling detector 3 (AND gate (AND gate) 24).

The falling detection pulse (horizontal synchronization detection pulse) is supplied to a flip-flop (DFF) 4. The count value output from the free-run counter 5 is supplied to the flip-flop (DFF) 4.
When the falling detection pulse is input, the flip-flop (DFF) 4 holds the count value N supplied from the free-run counter 5 at that time and outputs it to the subtractor 30. Here, the free-run counter 5 ranges from "0" to "90".
9 "is a counter that counts cyclically,
The 910 counts from “0” to “909” are based on the subcarrier frequency. That is, in the NTSC standard, the subcarrier frequency is defined as (910/4) times the line frequency, and when the count value N is 910, a line clock having a frequency of about 4 fsc can be obtained.

The flip-flop (DFF) 4 outputs the count value N of the free-run counter 5 to the subtractor 30 at the timing when the falling detection pulse is input. On the other hand, the reference value M (numerical value 455) is also supplied to the subtractor 30, and the subtractor 30 performs a process of subtracting the reference value M (numerical value 455) from the count value N. By this subtraction processing, for example, when the count value N of the free-run counter 5 is larger than the reference value M (numerical value 455), a plus (+) error value is output, and the count of the free-run counter 5 is increased from the reference value M (numerical value 455). When the value N is small, a negative (-) error value is output.

The integrator 31 multiplies the output of the subtracter 30 by, for example, a constant C. In this process, the error value is multiplied by a constant C to enlarge the error to a certain level. Further, the output of the integrator 31 is input to an adder 32, and a small error value generated at the time of the falling signal detection processing in the falling detector 3 is added. Note that the small error value generated in the falling detector 3 is smaller than the error value output from the integrator 31, and the calculation of the small error value will be described later.

The correction value converter 6 generates a correction value (first correction value) based on the error value supplied from the adder 32. Here, FIG. 3 is a diagram showing a conversion characteristic of the correction value with respect to the error value (phase difference). The upper part of the correction value is minus (-) and the lower part is plus (+). For example,
When the error value (phase difference) is plus (+), the correction value is minus (-), and the minus (-) value also increases at a predetermined rate. On the other hand, when the error value (phase difference) is minus (-), the correction value is plus (+), and the plus (+) value also increases at a predetermined rate.

The correction value data (first correction data) created by the correction value converter 6 is output to the value limiting circuit 33, and if the correction value is larger than the limit value, the limiting process is performed. For example, when the correction value is large, if the correction value is output as it is, the frequency greatly changes, and accurate line clock lock processing cannot be performed. Therefore, the occurrence of the above problem is avoided through the value limiting circuit 33.

The correction data that has passed through the value limiting circuit 33 is input to an adder 34. The adder 34 is a circuit for adding the value C1 to the correction data. The value C1 is a steady-state correction amount, a correction amount theoretically determined in an ideal state, for example, a crystal clock frequency (ideal line lock frequency), and a phase shift obtained by completely ignoring an error component. This is a correction amount corresponding to the amount 90 °. In this example, the value C1 is 2 ^{(m- 2)} . Therefore, the output of the adder 34 is (value C1 + correction data) and is output to the digital sine value generation circuit 7.

FIG. 4 is a circuit block diagram of the digital sine value generation circuit 7. The digital sine value generating circuit 7 includes an adder 7a, a register 7b, a converter 7c, and a look-up table (LUT) 7d. The adder 7a is a circuit for shifting the phase of the register 7b every clock, and the phase shift amount is controlled by the input correction value of the adder 7a. The register 7b has, for example, an m-bit configuration, divides a section from 0 to 360 ° into 2 ^m, and is sequentially updated by data supplied from the adder 7a.

The converter 7c is a circuit for converting into a digital sine value in accordance with the correction data output from the register 7b. The converter 7c is performed with reference to a look-up table (LUT) 7d, and the look-up table (LUT) 7d is composed of, for example, a ROM. FIG. 5 is a diagram showing conversion characteristics using the look-up table (LUT) 7d. In FIG. 5, the horizontal axis shows the value of the register 7b, and the vertical axis shows the converter 7c (look-up table (LUT)). 7d) shows the output value. Further, FIG. 2 shows a configuration in which one cycle (0 to 360 °) of the digital sine wave is divided into 2 ^m by the register 7b, and the clock is advanced by 90 ° for each clock. It is a configuration that goes around. For example, register 7
When the value of b is 2 ^(m-2) , the phase of the sine value is 90 °,
When the value of the register 7b is 2 ^(m-1) , the phase of the sine value is 18
When the value of the register 7b is 3.2 ^(m-2) , the phase of the sine value is 270 °, and the value of the register 7b is 2 ^m.
At this time, the phase of the sine value is 360 °.

The output of the digital sine value generating circuit 7 is output to a digital / analog converter (D / A converter) 35, converted into analog data, and then converted to an analog low-pass filter (hereinafter referred to as analog LPF) 36. Is output to the multiplication circuit 37 through. The multiplication circuit 37 multiplies the input frequency by a factor of 4 to 3.58 × 4 (MH
Output the line clock of z). This signal is used as a lock signal for the line clock and is output to the free-run counter 5 so that the free-run counter 5
Is used for count-up processing.

On the other hand, the color difference signal generation circuit 2 is composed of a band pass filter (BPF) 9, a digital sine value generation circuit (second digital sine value generation means) 8, a burst position detection circuit 10, and the like. (BPF)
9 receives a video signal. Bandpass filter (B
The PF 9 is a filter that passes the same frequency as the subcarrier (3.58 MHz) included in the video signal, and is a circuit that passes the color signal (C signal) and performs YC separation. That is, by using a subtractor (not shown), the color signal (C signal) extracted as described above is used.
Is subtracted from the video signal, a luminance signal (Y signal) is extracted, and YC separation is performed.

The color signal (C signal) extracted by the band-pass filter (BPF) 9 is ACC (Auto Chroma).
Control) circuit 38, and the amplitude of the color signal (C signal) is amplified and normalized. Standardized color signal (C
The signals are output to the multipliers 39 and 40 to generate color difference signals (BY, RY) based on the subcarriers output from the digital sine value generation circuit 8, and are passed through low-pass filters 41 and 42. Is output to a matrix circuit (not shown). The DFF 41a is a circuit for delaying the subcarrier supplied to the multiplier 40 by 90 °.

On the other hand, the burst position detection circuit 10 is a circuit for detecting a burst position included in an input video signal, and detects a color burst position for about 10 cycles inserted into the back porch portion of the horizontal synchronization signal. This detection result is output to the switch 43 and the burst position detection circuit 1
The switch 43 is switched according to the detection timing of 0, and the above-described color difference signals (BY, RY) are output to the correction value converter 11.

The correction value converter 11 compares the color burst with the color difference signals (BY, RY), creates a correction value, and outputs it to the adder 44. That is, the color burst signals (BY, RY) generated by the detection timing of the color burst inserted into the back porch portion of the horizontal synchronization signal and the subcarrier output from the digital sine value generation circuit 8
Are compared, an error of the subcarrier frequency is detected, and is output to the adder 44 as a correction value.

The adder 44 is also supplied with a correction value based on the line lock control from the line lock clock generation circuit 1 described above, and the two correction values are added. Here, the correction value supplied from the line lock clock generation circuit 1 to the adder 44 is the output of the -1 multiplier circuit 45, and the -1 multiplier circuit 45 is supplied via the value limiting circuit 33 described above. This is data obtained by multiplying the line clock correction value by -1. The error correction circuit 46 is a circuit for presetting an error value of the result of multiplication by the -1 multiplication circuit 45.
7 is added to the above-described correction value, and the -1 multiplication circuit 45
Is output to This circuit calculation will be described in a later embodiment.

The correction value from the -1 multiplying circuit 45 compensates for an error in the line clock, and the adder 48 adds the steady-state correction amount C2 to the correction value (the second correction data). The signal is output to the sine value generation circuit 8. The steady-state correction amount C2 is also a correction amount theoretically determined in an ideal state.

The comparator 49 is a circuit for comparing the output of the correction data with a predetermined constant. For example, if the correction data is within the range of the constant, it is output as an NTSC standard discrimination signal.

The circuit operation of the line lock clock generation circuit 1 and the color difference signal generation circuit 2 having the above-described configurations will be described below. First, a video signal is supplied to the falling detector 3. FIG. 6 is a diagram showing a schematic waveform of an input video signal, for example, a signal waveform for one line. As shown in the figure, the video signal first contains a horizontal synchronizing signal (HD pulse), and the falling detector 3 detects this horizontal synchronizing signal (HD pulse). That is, as shown in FIG. 2 described above, the comparator 22 compares the minimum value stored in the minimum value storage register 21 with a value obtained by adding C (determination level). For example, at the timing of time t1 shown in FIG. A horizontal synchronization signal (HD pulse) is detected.

The flip-flop (DFF) 4 outputs the count data (count data) N of the free-run counter 5 to the subtractor 30 at the timing when the falling detection pulse is input. Here, the count data N is equal to the reference value M.
If the value is smaller than (numerical value 455), a negative (-) output is given.
If it is larger, a plus (+) output is output from the subtractor 30.

In the digital sine value generating circuit 7, as described above, the look-up table (LU
T) Search 7d and output the sine value corresponding to the correction value. For example, if the correction value is a minus (-) value and the initial value is "0", the next value is 2 ^(m-2) -α (90 °-
α), and the next value is 2 ^(m-1) -2α (180 ° -2
α), and the next value is 3.2 ( ^m-2) -3α (270 °-
3α). Hereinafter, the read timing is sequentially corrected in the same manner. FIG. 7 shows the sine value output timing of the digital sine value generation circuit 7 in the above case.

On the other hand, although not shown, the correction value is plus (+)
In the case of (2), for example, + α is performed from the 90 ° phase shift change updated by the steady-state correction amount C1, and the readout timing is sequentially corrected.

The signal output from the digital sine value generation circuit 7 (look-up table (LUT) 7d) is output to the multiplication circuit 37 via the D / A converter 35 and the analog LPF 36, and is line-locked. Output as clock. Further, the clock signal is output to the free-run counter 5, the free-run counter 5 is counted up, and the same correction processing as described above is repeated.

FIG. 8 shows a case where the output value of the correction value is limited when the value limiting circuit 33 operates. In this example, when π / 2 and -π / 2, for example, the correction value is -R or R
Is limited to

By processing as described above, the supplied video signal is the output of a VTR or the like. Even if the line signal is not constant due to, for example, expansion or contraction of the tape, the video signal is corrected to the corresponding line clock. , A line lock clock corresponding to the video signal can be supplied.

On the other hand, the circuit operation of the color difference signal generating circuit 2 is as follows. In this case, the aforementioned correction value converter 6
The correction data created by the above is added by the adder 47 to the error correction value output from the error correction circuit 46,
The -1 multiplication circuit 45 performs -1 multiplication. Therefore, at this time, the correction data supplied from the -1 multiplication circuit 45 to the adder 44 is data corresponding to the expansion or contraction of the tape, and the correction value is added to the adder 44 so that a strict subcarrier frequency is generated. The sum is added at 44.

As described above, the burst position detection circuit 10 detects the output timing of the color burst signal in the back porch portion included in the video signal, and the correction data of the subcarrier frequency is output from the correction value converter 11 to the adder. 4
4. Therefore, the adder 44 creates the correction data of the subcarrier frequency from both the correction data, and further adds the steady-state correction amount C2 in the adder 48,
It is supplied to the digital sine value generation circuit 8. In the digital sine value generation circuit 8, a look-up table (L)
UT), and corrects the subcarrier frequency.

Then, color difference signals (BY, RY) are created from the color signals (C signals) included in the video signal according to the subcarriers output from the digital sine value generating circuit 8 and output to the matrix circuit. . Further, the subcarrier frequency is corrected based on the correction data generated by the correction value converter 11, and by repeating the above processing, the accurate color difference signals (BY, R- Y) can be output to the matrix circuit.

<Second Embodiment> Next, a second embodiment of the present invention will be described. In this example, the above-described line-locked clock generation circuit 1 is converted into a full digital circuit. FIG. 9 shows a basic system of a conventional analog PLL circuit. FIGS. 10A and 10B show examples of loop filters used therein. The above analog PL
In the case of the L circuit, an input as a control target (corresponding to a line clock in this example) is input to a phase comparator 60, and is compared with a control signal output from a VCO (voltage controlled oscillator) 61. 62. The loop filter 62 removes high-frequency components and converts a control voltage (analog signal) according to the phase difference into a VCO (voltage controlled oscillator).
VCO (Voltage Controlled Oscillator) 61 changes the oscillation frequency according to the control voltage supplied from the loop filter 62 and outputs it to the phase comparator 60 to control the input phase as described above. , Closer to the target frequency.

In the case of an analog PLL circuit that operates as described above, the control voltage for controlling the VCO (voltage controlled oscillator) 61 is a DC signal, and to generate this signal, FIGS. 10A and 10B Use an analog filter as shown in (1). Also, a D / A converter (not shown) is required.

In the video signal processing apparatus described in the above embodiment, the digital sine value generation circuit 7 shown in FIG. 4 is used instead of the VCO (voltage controlled oscillator) 61, so that a D / A converter is used. It is possible to control without. Further, in this example, FIGS. 10A and 10B
Consider digitizing the analog loop filter shown in FIG. For example, in the case of the La Group filter 62a shown in FIG. 10A, the time constant determined by the resistor R1 and the capacitor C is replaced by a digital circuit.

In this case, a filter can be formed by using an integrator, a multiplier, an adder, and a sign inverter. For example, if each operation element is formed by using an operational amplifier (operational amplifier) or the like, a circuit shown in FIG. become.

Here, A shown in FIG.

[0073]

(Equation 1)

Is as follows. Note that f _CK shown in the above equation (1) is
The horizontal frequency is 15.75 [kHz] according to the NTSC standard, and A can be obtained from the above equation (1). However, since it is considered that the time constant τ in the CR analog circuit is not actually known,
Further, a method for obtaining τ will be described.

[0075]

(Equation 2)

Where K is the gain characteristic Kφ of the phase comparator.
And the conversion gain Kv of the VCO, K = Kφ × Kv (3) Note that Kφ and Kv vary depending on the oscillation frequency of the digital sine value generation circuit 7 and the value of the phase comparison result input to the loop filter. However, the basic idea is as follows.

For example, the unit of Kφ is [V / rad], Kv
Is a unit of [rad / V · s], but in the present invention, since the signal for control is not a voltage but a digital value, each unit of K is considered digitally, and [V] => [step] ]
Is performed.

Then, the unit of Kφ is [step / rad], Kv
Can be replaced by [rad / step · s], and these constants can be determined based on the same concept as the above-described method of obtaining Kφ · Kv.

For ω _n , based on the graph of the initial response (step response) in the PLL control, the lock-up time t is appropriately determined from the condition of ω n × t = 4.5 (4) Decide and decide. Actually, it may be necessary to make a cut-and-try decision on this numerical value.
Assuming that the time for one line of the C video signal is 63.5 [us], ωn = 4.5 ÷ (63.5 × 10) = 70.9 × 10
... (5).

Further, in this example, the relationship between the damping factor ζ and the lock-up time is improved, as shown in FIG.
Was used as a loop filter in an actual video circuit. When this lag lead filter 62b is realized digitally, a digital circuit shown in FIG. 12 is obtained. The lag lead filter 62b shown in FIG. 10 (b) is a lag filter when an output is taken at a point A in FIG. 10 (b). Therefore, the output V _B of the lag lead filter is equal to the output V _{A of the} lag filter and the resistance R
_The pressure is divided by ₁ and R ₂ .

Therefore, when this is digitized,
As shown in FIG. 12, the output value from the circuit block of the lag filter and the original input value (= output of the phase comparator) are configured to take a weighted average by the coefficients B and (1-B). In FIG. 10B,

[0082]

(Equation 3)

Therefore,

[0084]

(Equation 4)

VB = B.VIN + (1-B) .VA (8) Therefore, the circuit of FIG. 12 is equivalent to the lag-lead filter 62b of FIG. 10B. be able to.

In the case of the lag-lead filter 62b, the method of obtaining the coefficients A and B is slightly different from that of the lag filter. That is, Kφ and Kv can be obtained in the same manner as in the case of the lag filter 62a, but the time constant τ is given by τ1 = C · R1 τ2 = C · R2 (9)

In the case of the lag lead filter 82b,

[0088]

(Equation 5)

[0089]

(Equation 6)

## EQU10 ## When you solve this

[0091]

(Equation 7)

[0092]

(Equation 8)

Is obtained. Here, from the above equation (7)

[0094]

(Equation 9)

Therefore, it can be said that in this equation (14),
By substituting equations (12) and (13), B can be obtained. Also, A uses the property of the time constant to

[0096]

(Equation 10)

Can be obtained from As described above, in the present example, the P
The loop filter of the LL circuit was constituted by a digital circuit, and the digital sine value generation circuit was controlled by this to constitute an oscillation circuit for a video signal.

According to the present invention, the VCO ·
All the PLL circuits can be digitized.
Note that the values input to these filters need to be digital values corresponding to the comparison results from the phase comparator 60 shown in FIG. Third Embodiment Next, a third embodiment of the present invention will be described.

This example explains more specifically the detection of a small error value by the falling detector 3 described above.
FIG. 13 shows a circuit for detecting the small error value, which is obtained by adding a small error value detection circuit to the falling edge detection circuit shown in FIG. Therefore, the same circuits as those shown in FIG.

In FIG. 13, reference numerals 13 to 26 denote the aforementioned A
/ D converter, 8-bit FF, adder, minimum value storage register, comparator, AND gate (AND gate), etc.
The small error value detection circuit of the present example includes a subtractor 65, an absolute value conversion circuit 66, a DFF 67, a comparator 68, a switching circuit 69, and a noise removal circuit 70.

FIG. 14 is a diagram for explaining the process of detecting a small error value having the above-described configuration, and in particular, is a diagram specifically illustrating a change in the signal level of the horizontal synchronizing signal at the time of detecting the falling edge.
In the figure, the signal E and the signal F have different slopes. For example, a signal E indicated by a dotted line is a horizontal synchronization signal having a gentle falling angle, and a signal F indicated by a solid line is a signal having a steep falling angle. Therefore, for example, when a horizontal synchronizing signal having a gentle falling angle such as the signal E is input and when a horizontal synchronizing signal having a steep falling angle is input, the signal level at the same timing t0 is only △ shown in FIG. different. Therefore, the circuit shown in FIG. 13 is used to correct the small error value.

[0102] That is, the video signal is
From the value of the judgment level (the minimum value storage register 2 described above).
1) is subtracted from the output of 1) to obtain an absolute value conversion circuit.
66 is output. The absolute value conversion circuit 66 calculates the above subtraction result.
The data is output to the DFF 67 and supplied to the comparator 68 for comparison.
Signal before a predetermined time delay in the DFF 67 in the device 68
Compare with For example, if the video signal output is a horizontal sync signal
, The video signal output rises sequentially
Approaching the judgment level, and the absolute value after the previous absolute value conversion output
The value of the logarithmic conversion output is smaller. So this
The output of the inter-comparator 68 outputs, for example, an L signal. one
On the other hand, when the video signal exceeds the judgment level,
The output at 68 changes from low (L) to high (H). this
At this time, the switching signal (from the high
(H)) is supplied, and the switch 69 is changed from, for example, “0”.
Is switched to "1" and then the aforementioned AND gate (AND gate)
) Removes the noise of the signal output from 24
The falling edge detection pulse (horizontal synchronization detection)
Outgoing pulse). Also, the DFF 67 delays for a predetermined time.
Is output as a correction difference value (small error value).
You.

FIG. 15 is a diagram specifically explaining the above-mentioned processing. FIG. 15A shows a falling part of the horizontal synchronizing signal, and shows an example of input A and input B. For example, for input A,
At the clock t0, the output of the subtractor 65 is output to the absolute value converter 66, and is converted to the value of NA in FIG.
It is held in the DFF 67. At this time, the output of the comparator 23 remains low (L). After that, at the timing of the clock t1, the output of the subtractor 65 becomes the value NA 'shown in FIG. 9A, and the output of the comparator 23 is inverted to become a high signal (H). At this time, the output of the comparator 23 becomes a high signal (H).
9 is switched from “0” to “1” and AND gate (AND)
A signal (NA) output via the gate 24 is output at the timing shown in FIG.

On the other hand, in the case of the input B, at the clock t0, the output of the subtractor 65 is output to the absolute value converter 66 in the same manner as described above, and is converted into the value of NB in FIG.
7 is held. At this time, the output of the comparator 23 remains low (L). After that, at the timing of the clock t1, the output of the subtractor 65 becomes the value of NB 'shown in FIG. 9A, and the output of the comparator 23 is inverted to become a high signal (H). However, the comparison result by the comparator 68 remains a low signal (L), and the switch 69
Remains "0". Therefore, the horizontal synchronization detection pulse is not output at this timing, and the AND gate (AN
The output of the D gate 24 is held in the DFF 71, and a signal (NB) is output at the timing of the next clock t2 as shown in FIG.

With this configuration, the minute error value is added to the above-mentioned correction data, supplied to the digital sine value generation circuit as more accurate correction data, and a line lock clock can be output. <Fourth Embodiment> Next, a fourth embodiment of the present invention will be described.

In this example, the value of the phase comparison result for the digital sine value generation circuit 8 will be described. Burst is C _R component and C _B components, the color signals such as that a value of reference defined by the NTSC video signal standards is a portion superimposed, the value of the burst portion of the decoder output RY · BY signal Is the best way to find out.

FIG. 16 shows some input / output characteristics of the phase comparator.
It was shown to. The input to the phase comparator is not the phase difference but the values of the respective color difference signals of BY and RY. FIGS. 16 (a) to 16 (a) show how the input value takes a value according to the phase difference between the subcarrier and the color burst.
(C) and shown in FIGS. 17 (a) and (b).

Now, the magnitude of the color signal is A
It is standardized by a CC (Auto Chroma Control) circuit 38. From FIG. 16B, for example, when the internal subcarrier and the color burst are locked without a phase difference,
The input that the RY component is 0 and BY is a negative value (−0.2) is supplied to the phase comparator. Of course, this value is a digital value. Actually, when the range of ± 1 is divided into 256 [deg], such as 256 × (−0.2) ÷ 2 (16), −
0.2).

This phase comparator is ideally the one shown in FIG.
As shown in (a), it is preferable that the comparative output increases in proportion to the phase difference. However, FIG.
Since the color difference signal of (b) is provided, a circuit for obtaining a linear output as shown in FIG. 16A from such a nonlinear function input is required. Specifically, in this case, a circuit for obtaining the arctan function is required. To realize such a circuit, a lookup table (LUT) is used as described above. However, such a circuit causes an increase in logic size and circuit cost.

Therefore, in this example, it is proposed to use approximate comparison results as shown in FIG. 16 (c) and FIGS. 17 (a) and 17 (b). In the approximation comparator shown in FIG. 16C, when the phase shift is within ± 90 °, the value of RY is used as the comparison result output as it is, and when there is more phase shift, simple addition and subtraction are performed on the BY value. The applied value is used as a comparison result output. By using such an approximation, it is possible to approximate the comparison result shown in FIG.

FIGS. 17A and 17B show a method of using a certain constant value when the phase shift is ± 90 ° or more.
This example is also a type of method for suppressing the upper limit of the correction value to a certain value or less. In FIG. 17A, the same value as at ± 90 ° is used.
In FIG. 6B, values obtained by adding a constant to the value at ± 90 ° are used. In the case of a phase shift of ± 90 ° or more, since the phase shift is large, it is considered that a fixed value may be approximated until the shift is within a certain range.

As described above, in this example, by using approximation, it is sufficient to input only the sign bit to BY, and as a result, the circuit scale can be further reduced. Also,
When the phase comparison result changes abruptly, the frequency of the sine wave output from the digital sine value generating circuit 8 changes abruptly, thereby preventing the internal subcarrier signal from changing abruptly. <Fifth Embodiment> Next, a fifth embodiment of the present invention will be described.

In this example, the digital sign value generation circuit 7 described above is used.
Specifically, a method of multiplying the correction value created on the side by (−1) and adding it as a correction value to the digital sine value generation circuit 8 for subcarrier output will be specifically described.

First, FIG. 18 shows a specific circuit block diagram of the present example. In the figure, the circuit in the dotted line described as "SIN value generation circuit 1" is the same circuit as that in FIG. Therefore, corresponding circuits are given the same numbers. Further, a circuit described as “SIN value generation circuit 3” is a circuit that outputs a signal of a subcarrier frequency for an encoder, and corresponds to the above-described digital sine value generation circuit 8. Also, for the other circuits shown in the figure, the same circuits as those in FIG.

As described above, as the correction value input to the digital sine value generation circuit 8, data obtained by inverting (-1 multiplying) the correction value of the line lock clock oscillator (digital sine value generation circuit 7) is supplied. A method was proposed.

Hereinafter, a process of outputting the digital sine value generating circuit 8 as a sine wave almost synchronized with the crystal clock by this method will be described. First, the digital sign value generation circuit 7 will be considered. For the sake of simplicity, the oscillation frequency of the crystal clock is set to 4f _SC , and the multiplication circuit used is a quadruple. As described above, the comparator and the correction value are set to 910 clocks per line.

With this circuit configuration, when the input video signal conforms to the NTSC standard, the correction value is 1
It takes a value such that the phase is exactly 90 ° per clock. If the counter is an n [Bit] counter, this value is 2 ^(n-2) . This corresponds to C ₁ in FIG. 18.

If the line is expanding or contracting, the correction value Δe in FIG. 13 is added accordingly, and the correction value ΔHD for the SIN value generation circuit 1 is ΔHD = 2 + Δe ·・ ・ (17)

Then, the line lock clock frequency f
_LCK is

[0120]

[Equation 11]

Is obtained. Similarly, the output SIN wave frequency f _E of the SIN value generation circuit 3 is calculated from the equation (18).

[0122]

(Equation 12)

Is obtained. Here, n is the number of bits of the upper and lower counters. Here, Δe in the equations (18) and (19) is a correction value caused by an error of one line length, and the output S
It can be said that the value is sufficiently smaller than the counter value 2 ⁽ⁿ⁻²⁾ corresponding to 90 ° of the IN wave phase.

Then, equation (19) is obtained by the formula of the product of the sum and the difference.

[0125]

(Equation 13)

It can be said that: As a result, as shown in FIG. 18, a value obtained by inverting the sign of the correction value of the line lock clock oscillator (digital sine value generation circuit 7) is input as the correction value of the digital sine value generator 8 operated by the line lock clock. Thus, a sine wave having a frequency substantially equal to the oscillation frequency of the original crystal clock can be obtained.

In this embodiment, as described above, the sign value of the digital sine value generation circuit 7 is inverted (multiplied by -1) and added to the correction value of the digital sine value generation circuit 8 to generate the digital sine value. The output sine wave which is the reference of the circuit 8 can be synchronized with the crystal clock f _SC, and the input burst signal can be made to follow the signal based on this signal. As a result, it is possible to obtain an image of good quality with stable operation.

Now, in this method, the equation (20)

[0129]

[Equation 14]

The following approximation was used. However,
In the NTSC television signal standard, a very strict standard of subcarrier signal = 3.579545 MHz ± 50 Hz (22) is defined. For this reason, for an input having a relatively large Δe, that is, for a TV signal input such as a VTR signal in which the one-line cycle is greatly shifted, the approximation of Expression (20) does not hold, and as a result, the color changes or the color does not appear. Such a problem may occur.

Here, consider how much error is caused by the value of Δe. In Equation (20), considering without using approximation,

[0132]

(Equation 15)

It can be seen that there is an error of Here, as shown in equation (23), this error is proportional to the square of Δe shown in FIG.

Therefore, in this example, Δe as shown in FIG.
By adding an “error correction circuit” that takes
An error resulting from the approximation of Expression (20) is corrected, and an internal subcarrier frequency having a more stable frequency is generated to achieve high image quality.

Assuming that the output error correction value from this error correction circuit is ε (ε in FIG. 18), this ε is further added to the correction value of the digital sine value generation circuit 8 to remove the error. )Than

[0136]

(Equation 16)

It can be seen that ε determined by solving the following equation should be added to the correction value. Solving the above equation gives

[0138]

[Equation 17]

Thus, the “error correction circuit” in FIG. 18 may be configured to output ε in response to the Δe input.
In this example, a switching circuit 72 that can be switched between the external synchronization mode and the internal synchronization mode is used. <Sixth Embodiment> Next, a sixth embodiment of the present invention will be described.

In this example, the look-up table (LUT) 7d can be completed in a quarter cycle by using the upper two bits of the register indicating the phase of the sine value generator 7 shown in FIG. .

FIGS. 19A to 19D illustrate the principle of the present example. The diagram of the sine wave shown in FIG. 5A corresponds to FIG. 5 described above. Here, the value of the m-bit register is 2 ^(m−2) , that is, a portion corresponding to the phase of the output sine value of 90 °. When the sine waveform of the output is divided, there is a difference between positive and negative signs and left-right symmetry. However, all have the same waveform.

At this time, the upper 2 bits of the m-bit register
The state of the bit changes every 90 ° as shown in FIG. Therefore, in this example, it is proposed to determine the current phase (quadrant) from the upper two bits and control the sign and the reading direction of the look-up table (LUT) 7d. ) The configuration is such that it can be realized by having a quarter period (90 °) of the sine waveform without having the entire period of 7d.

First, when the sine wave shown in FIG. 19A is compared with the most significant bit of the register value shown in FIG. 19B, the most significant bit of the register value indicates the sign of the output sine wave. I understand. Further, comparing the upper 2nd bit with the sine wave, the lookup table (LUT) 7d is read out in the forward direction when the upper 2nd bit is low (L), and the reverse is performed when the upper 2nd bit is high (H). It can be seen that reading in the direction is sufficient.

From the above examination results, it is sufficient that the look-up table (LUT) 7d has data of, for example, a quarter cycle shown in FIG. 20, and the register value can be converted into a sine value. That is, as shown in FIGS. 19C and 19D, a configuration may be adopted in which the sine value is inverted and read every time the phase changes by 90 °.

The circuit shown in FIG.
-1 to 74- (m-2), LUT bit input circuit 75,
When a register value of, for example, m bits is input, the most significant bit (m) and the second most significant bit (m-1) are processed as control signals, and the remainder is processed. (M-2 to 1) is processed as a value representing the phase. Here, when the reading direction of the register value is reversed, the input value is (2 ^m −1) − (register value) (26), and the sine value is obtained from the table of FIG. Good. However, the value of the expression (26) inverts each bit of the original input register value.

Therefore, as shown in the circuit of FIG.
-1) The exclusive OR of the value of the bit and the value of the remaining bits (m-2 to 1st bits) is obtained, and the result is input to a look-up table (LUT). In this way, the value of the remaining bits is input as it is or inverted depending on the value of the (m-1) th bit. Further, the configuration is such that the sign of the output of the look-up table (LUT) is determined by the value of the m-th bit (most significant bit).

Using the circuit of FIG. 21 configured as described above, the look-up table (LUT) can be reduced to a quarter of the conventional one.
Thus, the circuit scale can be significantly reduced. <Seventh Embodiment> Next, a seventh embodiment of the present invention will be described. This example also has a configuration related to a digital sine value generation circuit.
T) This is realized by an electronic circuit not using 7d.

First, as a method of generating a sine value, a method of immediately converting a register value into a sine value using a magnitude comparison circuit or the like can be considered. However, the number of bits of the register / output sine value is increased to improve the accuracy of the sine wave. Attempting to increase it will cause problems such as enormous circuit scale and computation time. For this reason, conventionally, a method of performing a two-stage conversion has conventionally been used.

In this case, as a first step, FIG.
The circuits for obtaining the boundary discrimination signals shown in 2 (a) to (c) are used. In this case, as shown in FIGS. 22A and 22B, a register value R _n at which the output sine value changes is obtained, and as shown in FIG. 22C, when the register value is less than R _n , 1 is set. A boundary discrimination signal a _n which becomes 0 at a time longer than that is generated.

Since even one size comparison circuit becomes a very large circuit, the circuit should be configured with a minimum number. However, the circuit for obtaining the boundary determination signal in FIG. Since it can be constituted by the number of comparison circuits, it is appropriate to obtain the boundary discrimination signal and then obtain the output sine value only from the boundary discrimination signal.

As a second step, a circuit for obtaining the output sine value from the boundary discrimination signal is required. FIG.
(A)-(c) is a figure explaining this step. Here, the boundary discrimination signal an shown in FIG.
This is the same as the signal shown in FIG. At this time, when the direct conversion is performed, at the locations indicated by the black dots shown in FIG.
It is necessary to perform logical judgment using the boundary judgment signal.

On the other hand, the logical decision points necessary for converting to the gray code are the locations shown in FIG. While it may be determined just place the same number of boundary discrimination signal a _n in the case of the Gray code, in the case of direct conversion, a plurality of S at the fall of a certain boundary discrimination signal
(Sign value signal) will use logic judgment as a condition. In other words, it can be said that the logic is complicated in the case of direct determination.

This means that the complexity increases as the number of bits of the output sine value increases. Of course, when converting to a gray code and then obtaining a sine value, gray code =>
A conversion circuit called a sine value is also required.
Since the exclusive ORs 78a and 78b can be realized by using the number of bits of the output sign value as shown in FIG.

By using the method of this embodiment, the conversion circuit of the register value => SIN value can be simplified,
This is very effective when digitizing a video signal circuit, especially when an oscillation circuit is digitally configured.

[0155]

As described above, according to the present invention,
Since a corresponding line clock clock is generated and used as a system clock for a video signal output from a playback device such as a VTR having an unstable tape speed, a high-quality playback image can be reproduced.

Further, the video signal processing circuit can be fully digitalized, and the operation stability, the number of parts can be reduced, and the cost can be reduced, the circuit can be simplified, and the size can be reduced. In addition, it is possible to reduce the influence of noise or the like which is easily affected by the analog circuit, and to construct a high-quality video circuit.

Further, a synchronous clock oscillation circuit which has conventionally been constituted by an analog circuit can be constituted by a digital circuit, and a highly accurate PLL circuit can be constructed.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram illustrating a video signal processing device according to an embodiment.

FIG. 2 is a diagram illustrating a circuit configuration of a falling detector.

FIG. 3 is a diagram illustrating conversion characteristics of a correction value with respect to an error value (phase difference).

FIG. 4 is a circuit block diagram of a digital sine value generation circuit.

FIG. 5 is a diagram showing conversion characteristics using a look-up table (LUT).

FIG. 6 is a diagram showing a schematic waveform of an input video signal.

FIG. 7 is a diagram illustrating a sine value output timing of a digital sine value generation circuit.

FIG. 8 is a diagram illustrating an example in which an output value of a correction value is limited when a value limiting circuit operates.

FIG. 9 is a diagram showing a basic system of an analog PLL circuit.

10A is a diagram illustrating a circuit configuration of an analog lag filter, and FIG. 10B is a diagram illustrating a circuit configuration of an analog lag read filter.

FIG. 11 is a diagram in which each operation element is configured using an operational amplifier (operational amplifier) or the like, and is an example in which an analog lag filter is implemented by a digital filter.

FIG. 12 is a diagram in which each operation element is configured using an operational amplifier (operational amplifier) or the like, and is an example in which an analog lag lead filter is realized by a digital filter.

FIG. 13 is a circuit diagram of a circuit for detecting a small error value.

FIG. 14 is a diagram illustrating a principle of detecting a small error value.

FIG. 15A is a diagram showing a signal change at a falling point of the horizontal synchronization signal, and FIG. 15B is a time chart for the input signal of FIG.

16A is a diagram illustrating a characteristic that a comparison output increases in proportion to a phase difference, FIG. 16B is a diagram illustrating color difference signals having a 90 ° phase difference, and FIG. 16C is a diagram illustrating a color difference signal. FIG. 9 is a diagram showing correction characteristics including the above.

17A is a characteristic diagram when an approximate comparison result is used, and FIG. 17B is a characteristic diagram when an approximate comparison result is used.

FIG. 18 is a system diagram illustrating a fifth embodiment.

19A is a diagram showing characteristics of an output sine value with respect to a phase difference, FIG. 19B is a diagram showing changes in the most significant bit and the second most significant bit, and FIG. It is a figure explaining a phase change, and (d) is a figure explaining the reading direction of a look-up table (LUT).

FIG. 20 is a diagram illustrating a change in a register value in the case of quarter cycle control;

FIG. 21 is a circuit diagram illustrating a circuit configuration used in a sixth embodiment.

FIGS. 22A and 22B are views for explaining the seventh embodiment, and FIG.
Indicates the change of the sine value with respect to the register value, and (b)
Indicates a bit change with respect to the register value, and (c) indicates a boundary determination signal with respect to the register value.

23A shows a boundary determination signal for a register value, FIG. 23B shows a sine value output for the register value, and FIG. 23C shows a gray code value for the register value.

FIG. 24 is a circuit diagram illustrating a seventh embodiment.

And FIG. 25 is a system diagram illustrating processing of a conventional video signal.

FIG. 26 is a diagram illustrating a problem of the conventional example.

[Description of Signs] 1 Line lock clock generation circuit 2 Color difference signal generation circuit 3 Fall detector 4 Flip-flop (DFF) 5 Free-run counter 6 Correction value converter 7 Digital sign value generation circuit 7a Adder 7b Register 7c Converter 7d Look-up table (LUT) 8 Digital sine value generation circuit 9 Bandpass filter (BPF) 10 Burst position detection circuit 11 Correction value converter 12 A / D converter 14-16 16-bit DFF 17-20 Adder 21 Minimum value Storage registers 22, 23 Comparator 24 AND gate (AND gate) 25 DFF 26 Inverter circuit 30 Subtractor 31 Integrator 32 Adder 33 Value limiting circuit 34 Adder 35 D / A converter 36 Analog low-pass filter (hereinafter, analog LP)
37 Multiplier circuit 38 ACC (Auto Chroma Control) circuit 39, 40 Multiplier 41, 42 Low-pass filter 43 Switcher 44 Adder 45 -1 Multiplier circuit 46 Error correction circuit 47, 48 Adder 49 Comparator 60 Phase Comparator 61 VCO (Voltage Controlled Oscillator) 62 Loop filter 62a La group filter 62b Lag lead loop filter 65 Subtractor 66 Absolute value conversion circuit 67 DFF 68 Comparator 69 Switching circuit 70 Noise removal circuit 71 Digital sign value generation circuit 74-1 ７４74- (m-2) Exclusive OR circuit 75 LUT bit input circuit 76 -1 integrator 77 Switching circuit 78a, 78b Exclusive OR

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Claims (13)

[Claims] 1. A digital sign value generating means for generating a digital sign value according to correction data; a synchronizing signal detecting means for detecting a horizontal synchronizing signal included in a video signal; Detecting means for counting the output of the digital sign value generating means until the next horizontal synchronizing signal is detected; comparing the counting result of the counting means with a reference value; And a correction data generating unit that outputs the digital signature value to the digital sign value generating unit, wherein the digital sign value generating unit locks a line clock according to the correction data. 2. A digital sine value generating means for outputting a subcarrier frequency according to correction data; a burst position detecting means for detecting an output timing of a color burst included in a video signal; A color difference signal generated in accordance with the subcarrier signal to be generated, and in accordance with the detection timing of the burst position detection means, compares the color difference signal with a subcarrier signal included in a color burst of the video signal to generate the correction data. A video signal processing device, comprising: 3. A first digital sine value generating means for generating a first digital sine value in accordance with the first correction data and locking a line clock, and a synchronization signal for detecting a horizontal synchronization signal included in the video signal Detecting means; counting means for counting the output of the first digital sign value generating means until the synchronization signal detecting means detects the horizontal synchronization signal and detecting the next horizontal synchronization signal; Means for comparing the count result of the means with a reference value, generating the first correction data according to the comparison result, and outputting the first correction data to the first digital sine value generating means. Circuit, second digital sine value generating means for outputting a subcarrier frequency in accordance with second correction data, and output timing of a color burst included in the video signal. And a color difference signal generated in accordance with a subcarrier signal output from the second digital sine value generating means, and detects a video signal in accordance with the detection timing of the burst position detecting means. A second correction data creating means for making a comparison with a color burst to create the second correction data, and multiplying the first correction data by -1 in the second correction data creating means. A video signal processing device comprising: a color difference signal generation circuit having an addition unit for adding a result. 4. The method according to claim 1, wherein the detection of the horizontal synchronization signal is performed by using a value at which a signal level included in a video signal maintains a minimum value for a predetermined period as a determination level. Video signal processing device. 5. The apparatus according to claim 1, wherein the synchronization signal detecting means detects an error value due to a difference in a falling angle of the horizontal synchronization signal, and includes the information of the error value in the correction data. Video signal processing equipment. 6. The synchronization signal detecting means detects an error value due to a difference in a falling angle of the horizontal synchronization signal, and includes information of the error value in the first correction data. Item 3. The video signal processing device according to Item 3. 7. When the correction data exceeds a certain value,
2. The video signal processing device according to claim 1, wherein the correction data is limited. 8. The video signal processing apparatus according to claim 3, wherein when the first correction data exceeds a certain value, the first correction data is limited. 9. The digital signature value generating means uses a digital filter.
Or the video signal processing device according to 2. 10. The video signal processing apparatus according to claim 3, wherein a digital filter is used for said first and second digital sine value generating means. 11. The video signal processing device according to claim 1, wherein said digital sine value generating means has a look-up table for storing a sine value corresponding to said correction data. 12. The video signal according to claim 3, wherein said first and second digital sine value generating means have a look-up table for storing a sine value corresponding to said first correction data. Processing equipment. 13. The video signal processing apparatus according to claim 12, wherein the look-up table stores only data for a quarter cycle of a sine waveform.