JP3249363B2 - Clock recovery circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit, and more particularly, to a clock recovery circuit for generating a sampling clock for A / D conversion of a color video signal in a VTR or a TV set. The present invention relates to a clock recovery circuit.

[0002]

2. Description of the Related Art In order to sample a composite color video signal in synchronization with the color burst signal, conventionally,
Constituting a so-called burst PLL (phase locked loop),
The sampling clock is obtained from the output of the PLL. That is, referring to FIG. 3, the input composite color video signal is applied to A / D converter 3 through low-pass filter 1 and pedestal clamp circuit 2 for removing aliasing noise, and is generated by PLL 4.
A / D conversion is performed based on a sampling clock of Fsc (four times the frequency of the subcarrier).

In the PLL 4, a composite color video signal is applied to a band-pass filter 4a, where it is subjected to Y / C separation. The color signal component (burst signal) from the band pass filter 4a is provided to the phase comparator 4b. The composite color video signal is also provided to the sync separation circuit 4c.
The burst gate pulse generation circuit 4d creates a burst gate pulse based on the horizontal synchronization signal output from the synchronization separation circuit 4c, and the burst gate pulse activates the phase comparator 4b. Therefore, during the burst gate pulse period, the phase comparator 4b outputs the oscillation signal of the voltage controlled oscillator (VCO) 4e having the oscillation frequency of 4Fsc to 1
The phase of the output of the frequency dividing circuit 4f for dividing the frequency by / N (for example, 1/4) is compared with the burst signal. Phase comparator 4
The output of b is supplied to the voltage-controlled oscillator 4f via the low-pass filter 4g. Thus, the burst PL
L4 is configured.

The output of the A / D converter 3 is processed in a digital signal processor (DSP) 5 by a three-dimensional Y / C separation circuit 5a and the like, and then processed by a D / A converter 6a.
And 6b, and converted again into an analog luminance signal and an analog color signal. D / A converters 6a and 6
The output of b is further provided to a demodulation circuit (not shown) and demodulated by analog signal processing.

In the prior art shown in FIG. 3, an uncertain phase between the sampling clock and the burst signal supplied to the A / D converter 3 due to the temperature drift of the band-pass filter 4a and the pedestal clamp circuit 2 and the like. An error may occur. For this reason, color demodulation by digital signal processing cannot be performed well, and as shown in FIG.
Since the color demodulation is performed after the conversion into the analog color signal by the converter 6b, the circuit configuration is complicated and the signal processing efficiency is low.

The disadvantage of the prior art in FIG. 3 that an uncertain phase error occurs between the sampling clock and the burst signal can be eliminated by the prior art in FIG. In the prior art shown in FIG. 4, the DSP 5 is provided with a phase comparator 7 and a phase shifter 8, and a burst signal (burst data) converted into a digital signal by the A / D converter 3 and a sampling clock from the voltage controlled oscillator 4e. Is detected by the phase comparator 7, and the phase of the sampling clock from the voltage controlled oscillator 4e is changed by the phase shifter 8 in accordance with the phase error, and is supplied to the three-dimensional Y / C separation circuit 5a.

[0007]

In the prior art shown in FIG. 4, it is necessary to average burst data in one field, for example, in order to remove the influence of noise. Therefore, a large amount of burst data is stored. However, there is a disadvantage that a large capacity memory is required. Hence,
A main object of the present invention is to provide a clock recovery circuit capable of obtaining a clock signal synchronized with a digitized burst signal with a simple circuit configuration.

[0008]

SUMMARY OF THE INVENTION The present invention provides a variable frequency oscillator whose oscillation frequency is changed by a control signal,
A / D converter for A / D converting at least an intermittent reference frequency signal of a television signal based on an oscillation signal from a variable frequency oscillator, and sample data obtained by sampling an output from the A / D converter at a reference frequency , Pedestal data generating means for generating reference pedestal data, comparing means for comparing sampled data with pedestal data, and a control signal variable during the reference frequency signal period based on the output of the comparing means. a control signal generating means for supplying to the frequency oscillator, the control signal generation hands
The stage is an analog low-pass filter that integrates the output of the comparing means.
Filter, the output of the comparison means and the analog low-pass filter.
Between the three-state switch and the reference frequency signal
During the period, the three-state switch is controlled according to the output of the comparing means.
And a switch control means .

[0009]

The A / D converter performs A / D conversion of an intermittent reference frequency signal (burst signal) of a television signal with an oscillation signal of a variable frequency oscillator, and outputs burst data.
In comparison means, bar - Sutode - data and sample data (SI) sampled at the reference frequency or the subcarrier frequency (F _SC) and Pedesutarude - Pedesutarude reference from data generating means - data (REF) is compared with .

When the pedestal data (REF) is larger (leading phase) than the sample data (SI), the comparing means outputs, for example, a high-level signal. The control signal is provided to the variable frequency oscillator as a control signal by control voltage generating means including a pass filter. Specifically, the capacitor of the low-pass filter is charged by the high-level signal, and a control signal for reducing the oscillation frequency of the variable frequency oscillator is output.

On the other hand, when the pedestal data (REF) is smaller (slower) than the sample data (SI), for example, a low level signal is output from the comparing means, and The capacitor of the pass filter is discharged; As a result, a control signal for increasing the oscillation frequency of the variable frequency oscillator is output from the low-pass filter.

[0012]

According to the present invention, a clock signal having a fixed phase relationship with respect to a digitized reference frequency signal can be generated with a simple circuit configuration. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0013]

Referring to FIG. 1, a clock recovery circuit 10 of this embodiment includes a PLL 12 and a DSP 14. The composite color video signal input from the input terminal 16 is supplied to a low-pass filter 18, where the composite color video signal has a frequency lower than half the sampling frequency (Nyquist frequency) in order to prevent aliasing that occurs when an analog signal is converted into a digital signal. High frequency video signals are removed. That is, the low-pass filter 18 corresponds to a Y / C separation circuit,
The low-pass filter 18 outputs a luminance signal component of the input video signal and supplies the same to the clamp circuit 20.

The clamp circuit 20 is a so-called pedestal clamp for clamping at a pedestal level, and adjusts a black level of an input video signal. The video signal (luminance signal) whose pedestal level is fixed is A /
Given to D converter 22 is digitally converted in accordance with a sampling clock having a frequency of 4F _SC from the voltage controlled oscillator 24 included in therein PLL 12.

The digitally converted video signal (video data) is applied to a three-dimensional Y / C separation circuit 26 included in the DSP 14, and to a sample circuit 28 and a band elimination filter (BEF) 30 in the same DSP 14. Can be In the three-dimensional Y / C separation circuit 26, the video data is a clock signal (4
F _SC = 14.3 MHz). Y
The luminance signal (Y) and the chrominance signal (C) from the / C separation circuit 26 are supplied to D / A converters 31a and 31b, and are subjected to analog conversion.

The digital video signal input to the sample circuit 28 is sampled at a subcarrier cycle (F _SC ), and the sample circuit 28 outputs sample data (SI) to the comparator 32. The comparator 32 compares the sample data (SI) with the reference pedestal data (REF) output from the pedestal data generation circuit 34.

The pedestal data (REF) is fixed (reference) data preset in the ROM of the pedestal data generation circuit 34, and is provided to comparators 32 and 36. The comparator 36 has the pedestal data (R
In addition to EF), luminance signal data from the band elimination filter (BEF) 30 is input, and these two data are compared. The comparator 36 outputs a signal responsive to the difference between the luminance signal data and the reference pedestal data (REF).

The signal from the comparator 36 is supplied to a feedback circuit 38, and the output from the comparator 36 is supplied to the clamp circuit 20 only during the burst period. That is, the feedback circuit 38
Are AND gates 40a and 40, to which the burst gate pulse (BGP) from the burst gate pulse generating circuit 46 and the inversion of the signal from the comparator 36 are input.
A three-state switch 42 in which three states can be switched by the output of a
The three-state switch 42a is turned on only during the burst period when a difference is generated between the luminance signal data and the reference pedestal data (REF). And
The output signal from the comparator 36 is negatively fed back to the clamp circuit 20.

More specifically, the comparator 36 compares the luminance signal data from the band elimination filter 30 with the pedestal data (REF) and generates a difference (voltage difference) between the two data. , The comparator 36 outputs a signal of, for example, a high level or a low level in response to the difference. This signal is given to the clamp circuit 20 via the three-state switch 42a. With this signal, the capacitor of the clamp circuit 20 is charged or discharged. That is, as shown in FIG. 1, the clamp circuit 20 includes a capacitor, and the clamp level of the clamp circuit 20 changes due to such negative feedback. Therefore,
The pedestal data of the video data after the A / D conversion is fixed to the reference pedestal data (REF). As described above, since the pedestal level after the digital conversion can be accurately set, most of the clock generation circuit can be digitized, and the reproduction phase of the sampling clock can be strictly set.

The luminance signal data processed by the band elimination filter 30 is supplied to a sync separation circuit 44. A burst gate pulse generating circuit 46 generates a burst gate pulse based on the horizontal synchronizing signal from the sync separation circuit 44. That is, the burst gate pulse generation circuit 46
Includes a counter (not shown) for counting the time from the horizontal synchronizing signal, and a decoder (not shown) for decoding the output from the counter.

The burst gate pulse (BGP) output from the burst gate pulse generation circuit 46 is applied to the feedback circuit 38 and the control signal generation circuit 39 as described above. Thus, the output from the comparator 32 is supplied to the PLL 12 only during the burst period. That is, the control signal generation circuit 39 has a circuit configuration similar to that of the feedback circuit 38, and receives the inversion of the output signal from the comparator 32 and the burst gate pulse from the burst gate pulse generation circuit 46. And a three-state switch 42b. Sample data (SI) from sample circuit 28 and pedestal data generation circuit 34
The tri-state switch 42b is turned on only during the burst period when there is a difference (phase difference) between the data and the pedestal data (REF). At that time, the output signal from the comparator 32 is supplied to the low-pass filter 48 via the three-state switch 42b.

The low-pass filter 48 includes a capacitor (not shown), and outputs both signal data (S
A voltage corresponding to the phase error between (I, REF) is output and supplied to the voltage controlled oscillator 24. More specifically, FIG.
(A) shows an input burst signal. And the comparator 32
At the time, the pedestal data (REF) from the pedestal data generation circuit 34 shown in FIG. 2D is compared with the sample data (SI) from the sample circuit 28.
The reference pedestal data (REF) is shown in FIG.
As shown in (B), when it is larger than the sample data (SI) (SI-REF =-. DELTA.E), that is, the pedestal data (REF) is advanced with respect to the sample data (SI). If there is, the comparator 32 outputs, for example, a high-level signal (H) to the three-state switch 42b.

At this time, the comparator 32 also outputs AN
For example, a low level switching signal (L ') is output to D gate 40b. This switching signal (L ') is output when there is a phase error between the two data (SI and REF) input to the comparator 32 (SI ≠ REF).
By this switching signal (L ') and the burst gate pulse (BGP) from the burst gate pulse generating circuit 46, the three-state switch 42b becomes conductive, and the comparator 3
2 is a low-pass filter 4
8 given. With this signal (H), the capacitor (not shown) of the low-pass filter 48 is charged. Therefore, a control signal for reducing the oscillation frequency of the voltage controlled oscillator 24 is output from the low-pass filter 48.

On the other hand, as shown in FIG. 2C, when the reference pedestal data (REF) is smaller (slower) than the sample data (SI) (SI-REF = ΔE).
, A low level signal (L) is output from the comparator 32, for example. As described above, the control signal generation circuit 38 is turned on during the burst period when both signals (SI and REF) input to the comparator 32 have a phase difference (SI ≠ REF), The low-level signal (L) from 32 is supplied to a low-pass filter 48,
The capacitor of the low-pass filter 48 is discharged. Therefore, the low-pass filter 48 outputs a control signal for increasing the oscillation frequency of the voltage controlled oscillator 24.

In response to the control signal output from the low-pass filter 48, the voltage controlled oscillator 24 outputs a clock signal whose oscillation frequency has changed according to the phase error data. That is, the low-pass filter 48 averages the phase error data generated between the two signals (SI and REF). Therefore, from the voltage controlled oscillator 24,
A clock signal having a fixed phase relationship with respect to a reference frequency signal (input burst signal) is supplied to the A / D converter 2.
2 is output.

According to the above-described embodiment, most of the components constituting the clock recovery circuit can be implemented by the digital signal processing circuit. Therefore, these digital signal processing circuits are incorporated in one DSP 14 to form one chip. can do. As a means for removing a color signal component from video data, the above-described band elimination filter (BEF) is used.
A low-pass filter (LPF) may be used instead of 30.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram showing a phase comparison in the comparator of FIG. 1 embodiment.

FIG. 3 is a block diagram showing a conventional technique.

FIG. 4 is a block diagram showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 10 clock recovery circuit 12 PLL 14 DSP 22 A / D converter 24 voltage controlled oscillator 28 sample circuit 30 band elimination filter (BEF) 32, 36 comparator 38 feedback circuit 39 control signal generation Circuit 48… Low-pass filter

Claims (2)

(57) [Claims] 1. A variable frequency oscillator whose oscillation frequency is changed by a control signal, wherein at least an intermittent reference frequency signal of a television signal is A / O based on an oscillation signal from the variable frequency oscillator.
A / D converter for performing D conversion, sampling means for sampling the output from the A / D converter at a reference frequency and outputting sample data, pedestal data generating means for generating reference pedestal data, the sample data said Pedesutarude - comparing means for comparing the data, and a control signal generating means for supplying to said variable frequency oscillator to the control signal in the reference frequency signal period on the basis of the output of said comparator means, said control signal generating means Integrates the output of the comparing means
An analog low-pass filter, and an output of the comparing means.
3 states inserted between the analog low-pass filter
Status switch and the comparator during the period of the reference frequency signal.
A switch for controlling the three-state switch according to the output of the stage.
And a clock recovery circuit. 2. The clock recovery circuit according to claim 1, wherein said reference frequency is a subcarrier frequency of said television signal.