JP3022729B2 - Burst lock PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst lock PLL (Phase Lo PLL) for a video signal such as an NTSC signal.
In particular, the present invention relates to a burst locked PL which is suitable for use as a system clock for an EDTV-2 receiver or a color demodulation circuit for performing double-density conversion processing of a scanning line.
It relates to an L circuit.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing an example of a conventional burst lock PLL circuit. The burst lock PLL is NT
This is one type of PLL that performs feedback control so that the phase of a burst superimposed on a video signal such as an SC signal and the phase of a color subcarrier (subcarrier signal) frequency match.

In FIG. 4, a video signal input to an input terminal 101 is an ACC (Automatic Color).
(Control) amplifier 102, terminal 105
During the period of the gate pulse indicating the burst position supplied from the ACC detection circuit 103, the amplitude of the signal subjected to ACC detection and the amplitude of the burst of the video signal are compared, and the amplitude of the burst of the video signal is kept constant. Output as

[0006] Next, in the phase comparison circuit 104, a clock having a subcarrier frequency obtained by dividing a 2n clock (for example, 8 fsc which is eight times as large) as the subcarrier frequency fsc by the frequency dividing circuit 108 (hereinafter referred to as a subcarrier clock). ) The phase of fsc is compared with the burst of the video signal output from the ACC amplifier 102 during the burst gate pulse period, and a phase error signal is output. This phase error signal is input to the voltage controlled oscillation circuit 107 via the loop filter 106 that limits the band. The voltage controlled oscillation circuit 107 controls the subcarrier signal so as to coincide with the burst phase, and outputs a 2n times clock (8 fsc) of the subcarrier frequency to the frequency dividing circuit 108 and the output terminal 109.

[0005] The frequency dividing circuit 108 converts the subcarrier signal 2
The n-fold clock (8 fsc) is frequency-divided, and the subcarrier clock fsc is supplied to the phase comparison circuit 104, and for example, the quadrupled clock 4 fsc is supplied to the output terminal 110. Although an example of the conventional burst lock PLL circuit has been described above, it is a well-known fact that various systems have been conventionally proposed regardless of the circuit configuration in each block, whether digital or analog.

[0006] FIG. 5 shows an EDTV-EDTV which performs a double-density conversion process for converting an interlace signal into a non-interlace signal.
FIG. 6 is a diagram showing a case where a digital burst lock PLL circuit is used for the two receivers, and FIG. 6 is a waveform diagram for explaining the operation of the burst lock PLL circuit in FIG. 6 shows operation waveforms when the clock frequency of 2n times the subcarrier frequency is 8 fsc, and FIG. 5 will be described as a configuration of the PLL circuit 504 in FIG. 5 as a circuit shown in FIG.

In FIG. 5, a video signal input to an input terminal 501 is input to an A / D converter 502, digitized, and output as a digital video signal. The digital video signal is supplied to a Y / C separation circuit 503 and a PLL.
The signal is supplied to the circuit 504. The PLL circuit 504 has the configuration shown in FIG. 4 as described above, and outputs an 8 fsc clock whose phase matches that of the burst and a 4 fsc clock obtained by dividing the frequency of the 8 fsc clock.

The 8 fsc clock is supplied to the double-density conversion processing circuit 5.
It is used as a system clock for the signal double-densified at 06 (hereinafter referred to as double-density signal). The 4 fsc clock is supplied to the A / D converter 502 and the Y / C separation circuit 50.
3. Each block of the color demodulation circuit 505 and the double-density conversion processing circuit 506 is used as a system clock for a signal before double-speed conversion (hereinafter referred to as a single-density signal).

On the other hand, a Y / C separation circuit 503 separates the digital video signal into a luminance (Y) signal and a chrominance (C) signal, and outputs the separated signals. The C signal output is demodulated by a color demodulation circuit 505 into color difference signals RY and BY. And Y /
The Y signal separated by the C separation circuit 503 and the color difference signals RY and BY demodulated by the color demodulation circuit 505.
Are input to the double-density conversion processing circuit 506, respectively. The double-density conversion processing circuit 506 converts the single-dense signal Y signal and the color difference signals RY and BY into double-density signals and outputs the double-density signals to the output terminal 507.

[0010]

The circuit configuration of the conventional burst lock PLL is as described above. However, for example, as shown in FIG. 5, as a system clock used in an EDTV-2 receiver for performing double-density signal processing, an n-times clock (for example, 4fsc) of a subcarrier frequency which is in phase with a burst of a video signal and 2n is used. Double clock (for example, 8
When the two types of clocks of fsc) are required, the following problems occur when realized by a conventional circuit configuration.

In the PLL circuit shown in FIG. 4, an output clock (4 fs) obtained by frequency-dividing a 2n-times clock (8 fsc) of the obtained subcarrier frequency by a frequency dividing circuit 108 is used.
fsc) does not directly control the burst and the phase. Therefore, when the power is turned on or the input signal is switched such as when the receiving channel is switched, the phase of the subcarrier clock (fsc) and the phase of the 8fsc clock are completely the same, but the phase of the fsc and the phase of the 4fsc clock are as shown in FIG. As shown in FIG. 6, eight types of states from 4fsc1 to 4fsc8 occur.

In practice, the phase of fsc and 4fsc is
4fsc 1, 3, 5, 7 or 4fsc
One of the states is shifted by 180 degrees as in sc2, 4, 6, and 8. The reason why such a state occurs is that 4 fsc obtained by dividing the 8 fsc clock by 前 before the phases of fsc and 8 fsc are matched by the PLL.
This is because a clock is output.

When this state occurs, as shown in FIG.
As a system clock of the DTV-2 receiver, an 8 fsc clock whose phase matches that of the burst is used for double-density conversion processing (double-density conversion processing circuit 506), and the 4 fsc clock is divided by the above-described method to generate a single-density signal. For processing (Y / C
When used as the separation circuit 503 or the color demodulation circuit 505), there is a possibility that a synchronization system or a timing system malfunctions when converting an input video signal which is a single-density signal into a signal subjected to double-density conversion processing. , The screen may be significantly disturbed.

Although not shown in FIG. 5, the color demodulation circuit 505 receives a 2 fsc clock in addition to the 4 fsc clock, and the 4 fsc and 2 fsc clocks have the same phase as the burst, respectively, as described above. If not, there is a problem that a malfunction occurs and the hue changes.

As described above, the conventional PLL circuit requires two types of clocks: an n-times clock (for example, 4 fsc) and a 2n-times clock (for example, 8 fsc) of the subcarrier frequency whose phase matches the burst. In this case, there is a problem that a burst lock PLL must be provided for each of them, and a single system of burst lock PLL circuit cannot be used.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention compares the phase of a subcarrier with a burst of a video signal in a burst gate pulse period and outputs a phase error signal. A comparison circuit, a loop filter for limiting the band of the phase error signal, and an output of the loop filter are input, and 2n (n is 1 ) of a subcarrier frequency controlled so that the burst and the phase match.
A burst-locked PLL circuit comprising: a voltage-controlled oscillation circuit that outputs a clock multiplied by the above (integer) times; and a frequency divider that divides a clock of 2n times the subcarrier frequency and outputs the subcarrier. And a subcarrier frequency output from the voltage control circuit and a clock of 2n times the subcarrier frequency output from the voltage control circuit, and controls the phase of the subcarrier so as to match each subcarrier frequency cycle. It is an object of the present invention to provide a burst lock PLL circuit including a frequency division phase control circuit that outputs a clock n times the carrier frequency.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A burst lock PLL circuit according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing one embodiment of a burst lock PLL circuit of the present invention, FIG. 2 is a diagram showing one embodiment of a frequency dividing phase control circuit of the burst lock PLL circuit of the present invention, and FIG. FIG. 4 is a waveform chart for explaining the operation of the peripheral phase control circuit. In FIG. 1, the same portions as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, a video signal input from an input terminal 101 is supplied to an ACC amplifier 102 for a period of a gate pulse indicating a burst position during an ACC detection circuit 103.
And compares the amplitude of the signal subjected to ACC detection with the burst of the video signal, and outputs the signal so that the amplitude of the burst of the video signal is kept constant. Next, the phase comparison circuit 104
At 2n times the clock of the subcarrier frequency (8f
The sub-carrier clock fsc obtained by dividing the signal sc) by the frequency dividing circuit 108 is compared with a burst of a video signal output from the ACC amplifier 102 in a burst gate pulse period, and a phase error signal is output.

This phase error signal is supplied to the loop filter 106
Is input to the voltage-controlled oscillation circuit 107 via the The voltage controlled oscillation circuit 107 controls the burst so that the phase matches the burst, and generates a 2n times clock (8 fs
c) to the frequency dividing circuit 108, the output terminal 109, and the frequency dividing phase control circuit 111. This divided phase control circuit 11
Reference numeral 1 denotes a subcarrier frequency clock fsc divided by the frequency dividing circuit 108 and a clock (4) obtained by dividing the subcarrier frequency 2n clock (8fsc) by half.
fsc) is made to coincide with each other for each subcarrier frequency cycle, and output to the output terminal 110.

Next, the frequency dividing phase control circuit 111 shown in FIG.
An embodiment will be described with reference to FIGS. 2 and 3. FIG.
FIG. 3 shows a clock of 2n times the subcarrier frequency of 8
The operation waveform when fsc is set is shown. In FIG. 2, the subcarrier clock fsc shown in FIG.
The data is input to the data input (D) of the D-type flip-flop 201 (first D-type flip-flop), and a 2n-times clock (8 fsc) of the subcarrier frequency shown in FIG.
Input (CLK) of the flip-flop 201,
Inverter circuit 202 and D-type flip-flop 20
5 (third D-type flip-flop).

The D-type flip-flop 201 shown in FIG.
As shown in (c), the subcarrier clock fsc is set to 2
It is delayed by one cycle by the n-fold clock (8 fsc). The subcarrier clock fs delayed by one cycle
c is supplied to the data input of the D-type flip-flop 203 (second D-type flip-flop) and the NAND circuit 204. The clock input of the D-type flip-flop 203 is connected to an inverter circuit 202 as shown in FIG.
Supplies an inverted clock. The D-type flip-flop 203 delays the subcarrier clock fsc delayed by one cycle by a further half cycle, and from the inverting terminal, delays the subcarrier clock fsc by a half cycle as shown in FIG. A carrier clock fsc is obtained.

By the D-type flip-flop 201, 1
The output delayed by the period (FIG. 3C) and the output from the inverting terminal of the D-type flip-flop 203 (FIG. 3E)
Each is input to the NAND circuit 204. The NAND circuit 204 outputs a pulse having a subcarrier frequency fsc cycle and a half cycle width of a clock (8 fsc) which is 2n times the subcarrier frequency as shown in FIG. A pulse having a cycle of fsc and a half cycle width of a clock 2n times the subcarrier frequency is supplied to the D-type flip-flop 2.
05 is supplied to a preset terminal (PR).

The D-type flip-flop 205 receives its inverted output as data, inputs a clock (FIG. 3A) having a frequency of 2n times the subcarrier frequency to a clock input, and operates the D-type flip-flop 205 as shown in FIG. As shown in g), a clock (4 fsc) obtained by dividing the clock (8 fsc) 2n times the subcarrier frequency by half is output. Since the D-type flip-flop 205 receives the above-described pulse having the fsc cycle (FIG. 3F) at the preset terminal, the D-type flip-flop 205 is constantly controlled in phase by the fsc cycle, and the sub-flip shown in FIG. A clock (4fsc) obtained by dividing the clock (8fsc) by 2n times the subcarrier frequency, which is always phase-locked with the carrier, by half is output.

[0024]

As described in detail above, the burst lock PLL circuit of the present invention uses the subcarrier frequency fsc as the phase of the divided subcarrier clock and the clock obtained by dividing the clock of 2n times the subcarrier. Since the divided phase control circuit is provided so as to match each subcarrier frequency, the subcarrier frequency (f
sc) and 2n times the clock of the subcarrier (for example, 8f
sc) and the phase of the clock (4fsc) obtained by dividing the clock of 2n times the subcarrier always match the phase of the burst, and the phase matching state can be maintained.

Therefore, the burst lock PL of the present invention
When the L circuit is used as a system clock in an EDTV-2 receiver or a color demodulation circuit that performs double-density signal processing, a screen may be disturbed due to malfunction of a synchronous system or a timing system during double-density conversion processing. There is a practically excellent effect that no hue change occurs even in color demodulation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a burst lock PLL circuit of the present invention.

FIG. 2 is a diagram showing one embodiment of a frequency division phase control circuit section of the burst lock PLL circuit of the present invention.

FIG. 3 is a waveform chart for explaining an operation of the frequency division phase control circuit shown in FIG. 2;

FIG. 4 is a diagram showing one embodiment of a conventional burst lock PLL circuit.

FIG. 5 is a diagram showing an example of the PLL circuit shown in FIG.
It is a figure showing the case where it is used for a DTV-2 receiver.

FIG. 6 is a waveform chart for explaining an operation of the burst lock PLL circuit shown in FIG. 4;

[Explanation of symbols]

Reference Signs List 102 ACC amplifier 103 ACC detection 104 Phase comparator circuit 106 Loop filter 107 Voltage controlled oscillator circuit 108 Divider circuit 111 Divided phase control circuit 201 D-type flip-flop (first D-type flip-flop) 203 D-type flip-flop (second-type) D-type flip-flop) 205 D-type flip-flop (third D-type flip-flop) 202 Inverter circuit 204 NAND circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/45 H04N 9/44

Claims (2)

(57) [Claims] A phase comparison circuit for comparing a phase of a subcarrier with a burst of a video signal during a burst gate pulse period and outputting a phase error signal; a loop filter for limiting a band of the phase error signal; 2n of the subcarrier frequency controlled so that the phase matches the burst
(n is an integer of 1 or more) A burst-locked PLL circuit including a voltage-controlled oscillation circuit that outputs a multiplied clock and a frequency divider that divides a clock of 2n times the subcarrier frequency and outputs the subcarrier A sub-carrier output from the frequency divider circuit and a 2n-times clock of a sub-carrier frequency output from the voltage control circuit are input, and a control is performed so that the phase of the sub-carrier coincides with each sub-carrier frequency cycle. A burst-locked phase-locked loop (PLL) circuit comprising a frequency-divided phase control circuit that outputs a clock n times the subcarrier frequency. 2. The frequency division phase control circuit receives the subcarrier and inputs a subcarrier frequency of 2n.
A first D-type flip-flop that outputs a signal delayed by one cycle with a double clock, and a clock that is 2n times the subcarrier frequency,
An inverting element that outputs an inverted clock, and an output that receives an output of the first D-type flip-flop, outputs a signal that is delayed by half a cycle and inverted by the clock output from the inverting element. 2 D-type flip-flops, and outputs of the first and second D-type flip-flops, respectively, and output a pulse having a sub-carrier frequency cycle and a half cycle width of 2n times the clock of the sub-carrier frequency. And an inverted output of the NAND circuit is input to a preset terminal, an inverted output of the NAND circuit is input as data, and a clock of 2n times the subcarrier frequency is reduced by half with a clock of 2n times the subcarrier frequency. 2. A burst lock P according to claim 1, further comprising a third D-type flip-flop for outputting a frequency-divided clock. L circuit.