JPH07336711A - Burst lock pll circuit - Google Patents

Abstract

PURPOSE:To obtain a burst lock PLL circuit of only one system in which a clock whose frequency is an integral multiple of two kinds of subcarrier frequencies whose phase is matched with the phase of a burst signal. CONSTITUTION:A frequency division phase control circuit 111 provided on a next-stage to a voltage controlled oscillator 107 matches the phase of a clock (fsc) of a subcarrier frequency with the phase of a clock (4fsc) resulting from 1/2-frequency dividing a 2n-multiple of clock (8fsc) of the subcarrier frequency for each frequency fsc. As a result, the phase of the subcarrier clock (fsc), a 2n-multiple clock (8fsc) of the subcarrier, a clock (4fsc) applying 1/2-frequency dividing a 2n-multiple clock of the subcarrier is in matching with the phase of a burst signal without fail to keep a stable phase lock state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst lock PLL (Phase Lo) for video signals such as NTSC signals.
CLOCKED LOOP) circuit, and in particular, a burst lock PL suitable for use as a system clock of an EDTV-2 receiver for performing a double-density conversion processing of scanning lines, a color demodulation circuit, or the like.
Regarding the L circuit.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing an example of a conventional burst lock PLL circuit. Burst Lock PLL is NT
This is a PLL system that performs feedback control so that the phase of a burst superimposed on a video signal such as an SC signal and the phase of a color subcarrier (subcarrier signal) frequency match.

In FIG. 4, a video signal input to the input terminal 101 is an ACC (Automatic Color).
Control) In the amplifier 102, the terminal 105
The amplitude of the burst of the video signal is kept constant by comparing the amplitude of the signal subjected to ACC detection by the ACC detection circuit 103 and the burst of the video signal during the period of the gate pulse supplied from Output as follows.

Next, in the phase comparison circuit 104, a clock of 2n times the subcarrier frequency fsc (for example, 8fsc of 8 times) is divided by the frequency dividing circuit 108 to have a subcarrier frequency (hereinafter referred to as a subcarrier clock). ) Fsc and the burst of the video signal output from the ACC amplifier 102 are phase-compared during the burst gate pulse period, and the phase error signal is output. This phase error signal is input to the voltage controlled oscillator circuit 107 via the loop filter 106 that limits the band. The voltage controlled oscillator circuit 107 controls the subcarrier signal so that it matches the phase of the burst, and outputs a clock (8 fsc) that is 2n times the subcarrier frequency to the frequency divider circuit 108 and the output terminal 109.

The frequency dividing circuit 108 divides the subcarrier signal into two.
The n-fold clock (8 fsc) is divided, and the sub-carrier clock fsc is supplied to the phase comparison circuit 104, and, for example, the 4-fold clock 4 fsc is supplied to the output terminal 110. Although an example of the conventional burst lock PLL circuit has been described above, it is a well-known fact that various types of conventional circuits have been proposed regardless of whether the circuit configuration in each block is digital or analog.

FIG. 5 shows an EDTV- which performs a double-density conversion process for converting an interlaced signal into a non-interlaced signal.
FIG. 7 is a diagram showing a case where a digital burst lock PLL circuit is used in the two-image receiver, and FIG. 6 is a waveform diagram for explaining the operation of the burst lock PLL circuit in FIG. 4. Note that FIG. 6 shows operation waveforms when the clock of 2n times the subcarrier frequency is 8 fsc, and FIG. 5 will be described with the configuration of the PLL circuit 504 in FIG. 5 as the circuit shown in FIG.

In FIG. 5, the video signal input to the input terminal 501 is input to the A / D converter 502, digitized and output as a digital video signal. The digital video signal is supplied to the Y / C separation circuit 503 and the PLL.
It is supplied to the circuit 504. As described above, the PLL circuit 504 has the configuration shown in FIG. 4, and outputs the 8fsc clock whose phase matches that of the burst and the 4fsc clock obtained by dividing the 8fsc clock.

The 8 fsc clock is supplied to the double-density conversion processing circuit 5
It is used as a system clock for a signal that has been double-density converted in 06 (hereinafter referred to as a double-density signal). The 4fsc clock is generated by the A / D converter 502 and the Y / C separation circuit 50.
3, used in each block of the color demodulation circuit 505 and the double-density conversion processing circuit 506 as a system clock for a signal before being subjected to double-speed conversion (hereinafter referred to as a single-density signal).

On the other hand, the Y / C separation circuit 503 separates the digital video signal into a luminance (Y) signal and a color (C) signal and outputs the signal. The C signal output is demodulated in the color demodulation circuit 505 into color difference signals RY and BY. And Y /
The Y signal separated by the C separation circuit 503 and the color difference signals RY and BY which are demodulated by the color demodulation circuit 505.
Are input to the double-density conversion processing circuit 506. The double-density conversion processing circuit 506 converts the Y signal, which is a single-density signal, and the color difference signals R-Y and B-Y into double-density signals and outputs them to the output terminal 507.

[0010]

The circuit configuration of the conventional burst lock PLL is as described above. However, for example, as shown in FIG. 5, as system clocks used in an EDTV-2 receiver for double-density signal processing, n times the subcarrier frequency clock (for example, 4 fsc) and 2n, which are in phase with the burst of the video signal. Double clock (for example, 8
When two types of clocks (fsc) are required, the following problems will occur if the conventional circuit configuration is used.

In the PLL circuit shown in FIG. 4, an output clock (4) obtained by dividing the clock (8 fsc), which is 2n times the obtained subcarrier frequency, by half by the frequency dividing circuit 108 is used.
fsc) does not directly perform burst and phase control. Therefore, when the power is turned on or when the input signal is switched such as when the receiving channel is switched, the subcarrier clock (fsc) and the 8fsc clock are completely in phase with each other. As shown in FIG. 6, eight kinds of states from 4fsc1 to 4fsc8 occur.

In practice, the phases of fsc and 4fsc are
4fsc 1,3,5,7 match or 4f
One of the two states is shifted by 180 degrees like sc2, 4, 6, and 8. The reason why such a state occurs is that 4 fsc is obtained by dividing the 8 fsc clock by half before fsc and 8 fsc are in phase with each other by the PLL.
This is because the clock is output.

When this state occurs, as shown in FIG.
As the system clock of the DTV-2 receiver, an 8fsc clock whose phase matches that of the burst is used for the double-density conversion processing (double-density conversion processing circuit 506), and the 4fsc clock is frequency-divided by the above method to obtain a single density signal. For processing (Y / C
When it is used as the separation circuit 503 or the color demodulation circuit 505), there is a possibility that the synchronization system or the timing system malfunctions when the input video signal, which is a single density signal, is converted into the double-density converted signal. , The screen may be significantly disturbed.

Although not shown in FIG. 5, the color demodulation circuit 505 inputs a 2fsc clock in addition to the 4fsc clock, and the 4fsc and 2fsc clocks are in phase with the burst, respectively, as described above. Even if it is not, there is a problem that a malfunction occurs and the hue changes.

As described above, the conventional PLL circuit requires two types of clocks, that is, an n-times clock (for example, 4fsc) and a 2n-times clock (for example, 8fsc) of a subcarrier frequency that is in phase with the burst. In such a case, a burst lock PLL has to be provided for each, and there is a problem that it is not possible to deal with the burst lock PLL circuit of one system alone.

[0016]

In order to solve the above-mentioned problems of the prior art, the present invention compares the phases of a subcarrier and a burst of a video signal in a burst gate pulse period and outputs a phase error signal. A comparator circuit, a loop filter that limits the band of the phase error signal, and a voltage control that inputs the output of the loop filter and outputs a 2n-times clock of the subcarrier frequency, which is controlled so that the phase matches the burst. In a burst lock PLL circuit including an oscillation circuit and a frequency dividing circuit that divides a 2n-times clock of the subcarrier frequency and outputs the subcarrier, the subcarrier output from the frequency dividing circuit,
A clock of 2n times the subcarrier frequency output from the voltage control circuit is input, and the phase of the subcarrier and
A burst lock PLL circuit is provided, which is provided with a frequency division phase control circuit that outputs a clock that is n times the subcarrier frequency and is controlled so as to match each subcarrier frequency cycle.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A burst lock PLL circuit according to the present invention will be described below with reference to the accompanying drawings. 1 is a diagram showing an embodiment of a burst lock PLL circuit of the present invention, FIG. 2 is a diagram showing an embodiment of a frequency division phase control circuit of the burst lock PLL circuit of the present invention, and FIG. 3 is a diagram shown in FIG. It is a waveform diagram for explaining the operation of the circumferential phase control circuit. In FIG. 1, the same parts as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, the video signal input from the input terminal 101 is supplied to the ACC amplifier 102 during the period of the gate pulse indicating the burst position and the ACC detection circuit 103.
By comparing the amplitudes of the ACC-detected signal and the burst of the video signal, the output is performed so that the amplitude of the burst of the video signal is kept constant. Next, the phase comparison circuit 104
At 2n times the subcarrier frequency (8f
The sub-carrier clock fsc obtained by frequency-dividing (sc) by the frequency dividing circuit 108 and the burst of the video signal output from the ACC amplifier 102 are phase-compared in the burst gate pulse period, and a phase error signal is output.

This phase error signal is used as a loop filter 106.
Is input to the voltage controlled oscillation circuit 107 via. The voltage-controlled oscillator circuit 107 controls so that the burst and the phase match each other, and a clock 2n times the subcarrier frequency (8fs) is used.
c) is output to the frequency dividing circuit 108, the output terminal 109, and the frequency dividing phase control circuit 111. This frequency division phase control circuit 11
1 is a subcarrier frequency clock fsc divided by the frequency dividing circuit 108 and a clock (4
The phase with fsc) is matched for each subcarrier frequency period and output to the output terminal 110.

Next, the frequency division phase control circuit 111 shown in FIG.
One embodiment will be described with reference to FIGS. 2 and 3.
It should be noted that in FIG.
The operation waveform when fsc is shown. In FIG. 2, the subcarrier clock fsc shown in FIG.
The data input (D) of the D-type flip-flop 201 (first D-type flip-flop) is input, and the 2n times clock (8fsc) of the subcarrier frequency shown in FIG.
Type flip-flop 201 clock input (CLK),
Inverter circuit 202 and D-type flip-flop 20
5 (third D-type flip-flop).

The D-type flip-flop 201 is shown in FIG.
As shown in (c), the subcarrier clock fsc is set to 2
The n times clock (8 fsc) is used to delay for one cycle. Subcarrier clock fs delayed by one cycle
c is supplied to the data input of the D-type flip-flop 203 (second D-type flip-flop) and the NAND circuit 204. The clock input to the D-type flip-flop 203 is the inverter circuit 202 as shown in FIG.
The inverted clock is supplied by. The D-type flip-flop 203 further delays the subcarrier clock fsc delayed by one cycle by a half cycle, and from the inverting terminal, delays by a half cycle as shown in FIG. The carrier clock fsc is obtained.

1 by the D-type flip-flop 201
The output delayed by the period (FIG. 3C) and the output from the inverting terminal of the D-type flip-flop 203 (FIG. 3E) are
Each is input to the NAND circuit 204. The NAND circuit 204 outputs a pulse having a half cycle width of a clock (8 fsc) that is 2n times the sub carrier frequency and has a sub carrier frequency fsc cycle as shown in FIG. A pulse having a half cycle width of the clock that is 2n times the subcarrier frequency is generated in the D-type flip-flop 2 in this fsc cycle.
05 preset terminal (PR).

The D-type flip-flop 205 receives the inverted output of itself as data, inputs the clock of 2n times the subcarrier frequency (FIG. 3 (a)) to the clock input, and operates to operate as shown in FIG. As shown in (g), a clock (4fsc) obtained by dividing the clock (8fsc) 2n times the subcarrier frequency by half is output. Since the pulse of the above-mentioned fsc cycle (FIG. 3 (f)) is input to the preset terminal of the D-type flip-flop 205, the phase is constantly controlled at the fsc cycle, and the sub-channel as shown in FIG. A clock (4fsc), which is phase-locked with the carrier, is obtained by dividing the clock (8fsc) 2n times the subcarrier frequency by half.

[0024]

As described in detail above, in the burst lock PLL circuit of the present invention, the phase of the divided subcarrier clock and the clock obtained by dividing the subcarrier clock of 2n times the subcarrier frequency fsc. Since the frequency division phase control circuit is provided to match each sub-carrier frequency (f
sc) and a clock of 2n times the subcarrier (for example, 8f
sc) and the clock (4 fsc) obtained by dividing the 2n-times clock of the subcarrier, always match the phase of the burst, and the phase matching state can be maintained.

Therefore, the burst lock PL of the present invention
When the L circuit is used as a system clock in an EDTV-2 receiver that performs double-density signal processing, a color demodulation circuit, or the like, the synchronization system or the timing system malfunctions during double-density conversion processing, and the screen is disturbed. In addition, there is no effect, and there is no hue change even in color demodulation, which is an extremely excellent effect in practical use.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a burst lock PLL circuit of the present invention.

FIG. 2 is a diagram showing an embodiment of a frequency division phase control circuit section of a burst lock PLL circuit of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the frequency division phase control circuit shown in FIG.

FIG. 4 is a diagram showing an embodiment of a conventional burst lock PLL circuit.

5 is an E circuit for performing double-density signal processing on the PLL circuit shown in FIG.
It is a figure which shows the case where it uses for a DTV-2 receiver.

FIG. 6 is a waveform diagram for explaining the operation of the burst lock PLL circuit shown in FIG.

[Explanation of symbols]

102 ACC Amplifier 103 ACC Detection 104 Phase Comparing Circuit 106 Loop Filter 107 Voltage Control Oscillation Circuit 108 Frequency Dividing Circuit 111 Frequency Dividing Phase Control Circuit 201 D Type Flip Flop (First D Type Flip Flop) 203 D Type Flip Flop (Second D-type flip-flop) 205 D-type flip-flop (third D-type flip-flop) 202 Inverter circuit 204 NAND circuit

Claims (2)

[Claims] 1. A phase comparison circuit for phase-comparing a subcarrier and a burst of a video signal in a burst gate pulse period to output a phase error signal, a loop filter for limiting a band of the phase error signal, and the loop filter. 2n of the sub-carrier frequency, which is controlled to match the phase with the burst.
In a burst lock PLL circuit including a voltage controlled oscillator circuit that outputs a double clock and a frequency divider circuit that divides a 2n-fold clock of the subcarrier frequency and outputs the subcarrier, The subcarrier and a clock of 2n times the subcarrier frequency output from the voltage control circuit are input, and the phase of the subcarrier is controlled so as to match each subcarrier frequency cycle, and the subcarrier frequency n A burst lock PLL circuit comprising a frequency division phase control circuit for outputting a doubled clock. 2. The frequency division phase control circuit inputs the subcarrier and outputs a subcarrier frequency of 2n.
A first D-type flip-flop that outputs a signal delayed by one cycle by a double clock and a clock that is 2n times the subcarrier frequency are input.
An inverting element that outputs an inverted clock; and an output that receives the output of the first D-type flip-flop, delays a half cycle by the clock output from the inverting element, and outputs an inverted signal. Two D-type flip-flops and the outputs of the first and second D-type flip-flops are respectively input, and a pulse having a half cycle width of the subcarrier frequency period and a 2n times clock of the subcarrier frequency is output. And the output of the NAND circuit is input to a preset terminal, the inverted output of itself is input as data, and the 2n times clock of the subcarrier frequency is halved by the 2n times clock of the subcarrier frequency. The burst lock P according to claim 1, comprising a third D-type flip-flop for outputting a divided clock. L circuit.