JP3308143B2 - Clock rate conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock rate conversion circuit, and more particularly to a clock rate conversion circuit capable of converting an input signal of a predetermined clock frequency to an arbitrary clock frequency with a simple logic circuit. The present invention relates to a conversion circuit.

[0002]

2. Description of the Related Art In television signal processing, in scanning line double-density interpolation processing, vertical expansion / compression processing, vertical filter processing, and the like, the clock frequency is a frequency that is an integral multiple of the horizontal synchronization frequency (hereinafter referred to as the line lock frequency). ) Is desirable. On the other hand, in the preceding stage, for example, a three-dimensional Y / C separation circuit, a color demodulation circuit, and the like, a clock frequency (hereinafter, 4Fsc) that is four times the color subcarrier is very advantageous for signal processing and for improving performance. The frequency of 4Fsc is NTSC
Although the standard signal is line-locked, it is a non-standard signal for package media such as VTRs and video signals from game machines and the like, and is often not line-locked. Therefore, in such a case, a function of rate-converting the 4Fsc clock to the line lock frequency is required.

Here, a conventional clock rate conversion circuit will be described. In the case of converting the clock rate from the signal train of the clock frequency f1 to the signal train of the clock frequency f2, when the frequency f1 and the frequency f2 have a relatively simple integer ratio, a method of performing linear interpolation has been conventionally performed. . FIG. 5 shows this first conventional example. In FIG. 5, (A) shows a signal having a clock frequency f1 composed of signal trains X1, X2, X3, X4..., And (B) shows a signal train Y1, Y2, Y3, Y4.
.. At a clock frequency f2. Frequency f
The ratio between 1 and the frequency f2 is 2: 3. The signal sequences Y1, Y2, Y3,... After the linear interpolation have the following values.

Y1 = X1 Y2 = (1/3) × X1 + (2/3) × X2 Y3 = (2/3) × X2 + (1/3) × X3 Y4 = X3 Y4 and below, the above equation is repeated. . This linear interpolation method is effective when the ratio between the frequency f1 and the frequency f2 is a relatively simple integer ratio.

FIG. 6 shows a second conventional example in which the ratio between the frequency f1 and the frequency f2 is not a relatively simple integer ratio. In FIG. 6, a signal sequence X at a rate of a clock CK1 is input to an input terminal 1 and is converted into an analog signal by a D / A converter 2. Further, the signal from which harmonic components have been removed by the low-pass filter (LPF) 3 is A
The signal is again converted into a digital signal at the rate of the clock CK2 by the / D converter 4 and output from the output terminal 5. In this case, the relationship between the respective frequency ratios of the clock CK1 and the clock CK2 may be arbitrary.

[0006]

The first conventional example described above is limited to the case where the ratio between the clock frequency f1 and the clock frequency f2 is a relatively simple integer ratio. Frequency f1
When the frequency f2 and the frequency f2 are close to each other, the ratio becomes an integer ratio of a relatively large value, the operation cycle of one cycle increases, and the coefficient to be multiplied becomes large, which makes implementation difficult. In the second conventional example described above, the D / A converters 2 and L
The PF 3 and the A / D converter 4 are required. When a clock rate conversion circuit is configured in an LSI circuit, the number of input / output terminals increases and the number of LSI external components increases. In addition, LSI
Even if the A / D converter 2 and the D / A converter 4 can be built therein, the chip size is larger than that of ordinary logic. In particular, the greater the number of clock rate conversion circuits, the greater their disadvantages and the higher the cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a circuit configuration using a simple logic circuit, which can convert an input signal having a predetermined clock frequency into an arbitrary clock frequency. It is an object to provide a rate conversion circuit.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention provides a first frequency of a first frequency.
A clock rate conversion circuit for converting a clock rate of a television signal sampled by the clock of the second embodiment into a second clock having a second frequency which is an integral multiple of the horizontal synchronization frequency. , The signal level of two sample points closest to the horizontal synchronization level in the horizontal synchronization signal, with the horizontal synchronization level set between
From the level, the said located between the two sample points
The position of the horizontal sync level is determined by any of the two sample points.
Shift factor k , expressed as the ratio of the position from one of the points
, A shift coefficient k obtained by the coefficient detection circuit, and two adjacent coefficients in the video signal.
From the pixel data S1 and S2, k × S1 + (1−k) ×
Writing the interpolated value generating circuit for generating an interpolated value represented by S2, a video signal to be input to the interpolated value generated video signal or the interpolation value generating circuit is output from the circuit, as a clock write the first clock And a memory for reading out the second clock as a readout clock.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock rate conversion circuit according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the clock rate conversion circuit of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the clock rate conversion circuit of the present invention, and FIG. 3 is a coefficient detection circuit 18 in FIG. FIG. 4 is a diagram for explaining a clock rate conversion circuit according to the present invention.

As an example, a horizontal synchronizing frequency (hereinafter, Fh)
A description will be given of a case where the clock frequency of 912.25 times the clock frequency is converted to the clock frequency of 910 times the Fh. FIG. 4 shows a pixel pattern sampled by a clock having a frequency of 912.25 × Fh. The horizontal lines are scanning lines, and the phase shifts by 0.25 times the clock cycle for each scanning line. This 912.2
The signal sampled by the 5 × Fh clock is
If conversion can be made to a line-locked rate of a frequency of 910 × Fh, the sampling patterns will be aligned vertically.

In order to realize this, the difference in the number of clocks in one scanning line period may be processed as follows. Processing is performed so as to shift the decimal point difference of the number of clocks less than or equal to the decimal point (0.25 samples in the above example) and to shift the integer part of the clock number difference (two samples in the above example). .

Here, the clock rate conversion circuit of the present invention based on the above principle will be described. In FIG. 1, a television signal is supplied to an input terminal 10 at a rate of a clock CK1 having a frequency of 912.25 × Fh without line locking. Note that the television signal also includes a package medium such as a VTR and a video signal of a game machine and the like. This television signal is input to the interpolation value generation circuit 15. The interpolation value generation circuit 15 includes a D flip-flop 11, a subtractor 12, a multiplier 13, and an adder 14.

The television signal input to the interpolation value generation circuit 15 is input to a D flip-flop 11 and a subtractor 12. The clock CK1 is supplied to the D flip-flop 11.
Is supplied. The input of the D flip-flop 11 is connected to the signal S
1. Assuming that the output is a signal S2, the subtractor 12 subtracts the signal S2 from the signal S1 and inputs the signal S2 to the multiplier 13. Multiplier 13
Is supplied with a shift coefficient k, which will be described in detail later , from the coefficient detection circuit 18. The multiplier 13 multiplies the multiplier 13 by the shift coefficient k and inputs the result to the adder 14. The adder 14 adds the output of the multiplier 13 and the signal S2 output from the D flip-flop 11 and outputs the result. As described above, the interpolation value generation circuit 15
Multiplies the signal S1 by k, multiplies the signal S2 by (1-k), and outputs the sum.

The television signal input to the input terminal 10 is also input to a low-pass filter (LPF) 17.
The LPF 17 removes high frequency components of the input television signal and inputs the same to the coefficient detection circuit 18. Coefficient detection circuit 1
A horizontal synchronization level Th, which will be described later, is also input to the terminal 8 from the terminal 26. The coefficient detection circuit 18 detects the shift coefficient k using the horizontal synchronization signal as follows.

FIG. 2 is an enlarged view of the leading edge portion of the horizontal synchronizing signal (negative polarity). An intermediate value between the pedestal level and the leading edge level of the horizontal synchronizing signal is set to the horizontal synchronizing level Th. The horizontal synchronization level Th needs to be smaller than the pedestal level and larger than the leading level of the horizontal synchronization signal. The level may be arbitrary as long as it is a value between the pedestal level and the leading level of the horizontal synchronization signal. , The value at or near the center between the pedestal level and the leading level of the horizontal synchronization signal is more desirable. P0 to P3 in FIG. 2 indicate sample points of the horizontal synchronization signal sampled by the clock CK1. As shown in the figure, the shift coefficient k is a value a / b obtained by dividing the distance a from the horizontal synchronization level Th to the sample point P1 by the distance b between the sample points P1 and P2. 4 bits after decimal point (5
If bits are truncated, the range of the shift coefficient k is from 0 to 15/16.

Assuming that the input / output signals S1 and S2 of the D flip-flop 11 in FIG. 1 are at the positions shown in FIG. 4, the interpolation value generating circuit 15 calculates k × S1 +
By generating (1−k) × S2, a linear interpolation value Sx shown in FIG. 4 is obtained. For example, if k is 0.25, the signal S1 is multiplied by 0.25, the signal S2 is multiplied by 0.75,
These are added. In this way, the sample points of the video signal are processed by generating an interpolated value at a position corresponding to the shift of the difference of the number of clocks below the decimal point.

Here, a specific configuration of the coefficient detecting circuit 18 will be described. In FIG. 3, the input terminal 180 has L
The output of the PF 17 is input. The output of the LPF 17 has a high-frequency component removed, thereby improving noise immunity, and the leading edge of the horizontal synchronizing signal has a slope as described with reference to FIG. The signal input to the input terminal 180 is D
The signals are input to a flip-flop 181, a comparator 182, and a D flip-flop 185. D flip-flop 181
Is the input of P2 shown in FIG. 2 and the output is P1, the output signal P1 of the D flip-flop 181 is
The signal is input to the flip-flop 186.

The terminal A of the comparator 182 receives the horizontal synchronizing level Th, the terminal B receives the signal P2 as an input signal from the input terminal 180, and the terminal A of the comparator 182
Outputs 1 when greater than. A terminal A of the comparator 183 has a signal P1 which is an output signal of the D flip-flop 181.
However, the horizontal synchronization level Th is input to the terminal B, and the terminal A
Is output when terminal B is equal to or greater than terminal B. The outputs of the comparators 182 and 183 are input to the NAND gate 184, and when both are 1, they output 0. That is, P
The condition of 1 ≧ Th> P2 is detected. If a D flip-flop and a comparator are added, P0> P1 ≧ Th>
It is possible to detect the condition of P2> P3, and it is also possible to improve the prevention of malfunction by making the condition stricter.

The output signal of the NAND gate 184 is output from an output terminal 1811 and supplied to D flip-flops 185 and 186 as a clock. NAND
The output signal of the gate 184 is a write reset pulse W
It is supplied to the memory 16 as RST. D flip-flops 185 and 186 latch and output signals P2 and P1, respectively. The subtractor 187 is a D flip-flop 18
6, the output of the D flip-flop 185 is subtracted from the output of 6,
The signal (P1-P2) is obtained and input to the terminal B of the divider 189. The subtracter 188 subtracts the horizontal synchronization level Th from the output of the D flip-flop 186, and outputs a signal (P1-Th).
And input it to the terminal A of the divider 189. Divider 1
Reference numeral 89 denotes a signal (P1-Th) of the terminal A, and a signal (P
1-P2) to obtain a shift coefficient k. In this embodiment, since the shift coefficient k is 4 bits after the decimal point,
Actually, a 4-bit signal multiplied by 16 is input to the multiplier 13, and the multiplier 13 multiplies the multiplication result by 1/16.

The divider 189 takes a signal to the terminals A and B as an address and outputs data from a ROM in which the division result is written by the address.
16 times the signal to terminal A (0 is added to the lower 4 bits)
Then, a signal value to the terminal B is cumulatively subtracted from the signal, and the signal value is subtracted until the value becomes negative.

In summary, the coefficient detecting circuit 18 interposes the horizontal synchronizing level Th at the leading edge of the horizontal synchronizing signal shown in FIG. 2 and uses the two sample points P1 and P2 closest to the horizontal synchronizing level. A linear equation is created, and a position corresponding to the horizontal synchronization level Th is calculated as a shift from the sample point P1. Of course, it may be calculated as a shift from the sample point P2. Then, the interpolation value generation circuit 1
5 generates a linear expression from a sample signal of two consecutive video signals in the video signal period,
This means that the signal level corresponding to the shift calculated by the above is estimated to generate the interpolation value.

In the above embodiment, the estimation of the shift of the horizontal synchronizing level Th is performed at the sample points P1 and P2. However, the quadratic expression is obtained by the sample points P1, P2 and P3 or the sample points P0, P1 and P2. May be created and calculated, or a cubic equation may be created and calculated from the sample points P0, P1, P2 and P3. Since the leading edge of the horizontal synchronizing signal is close to a straight line, there is no effect even if a higher-order equation is used. If the signal level in the section is interpolated, the hardware increases but the accuracy improves. In the present embodiment, a linear expression is used instead of small-scale hardware.
The configuration based on the above high-order equation can be easily configured.

Here, returning to FIG. 1, the PLL circuit 24 generates a line lock clock based on the horizontal synchronization pulse HD. The PLL circuit 24 includes a phase comparator 20, a low-pass filter (LPF) 21, and a voltage-controlled oscillator (VCO).
22 and a frequency divider 23. The phase comparator 20 compares the phase of the horizontal synchronization pulse HD input from the terminal 19 with the output of the frequency divider 23. The output of the phase comparator 20 is input to the VCO 22 via the LPF 21. VCO2
2 oscillates according to the output value of the LPF 21. Divider 2
3 divides the output of the VCO 22 by 1/910. By the operation of the well-known PLL circuit 24, VCO2
2 generates a line-locked clock CK2 having a frequency of 910 × Fh and supplies it to the memory 16 as a read clock.

The clock CK1 is supplied to the memory 16 as a write clock. On the write side, the address of the memory 16 is incremented every write operation, and the write reset pulse W
When RST is input, the address is forcibly set to 0. On the read side, the line lock clock CK2 is supplied to the memory 16 and the address is incremented every read operation. When a read reset pulse RRST is input to the read reset terminal, the address is forcibly set to 0. This two-port asynchronous memory in which writing and reading are independent is general and general-purpose.

Incidentally, the difference between the number of clocks for writing and reading during one horizontal scanning period is usually about several clocks.
If the address is set to 0 when incrementing from 15 (that is, if the ring count operation is performed), 1
About 6 bytes is sufficient, and a very small capacity is sufficient.

The output of the frequency divider 23 is delayed by eight clocks from the write reset pulse WRST by the delay unit 25, and is output as a read reset pulse RRST to the memory 16 as a read reset pulse RRST.
Supplied to Thus, the difference in the number of clocks within one horizontal scanning period is allowed within ± 7 clocks. Delay device 2
5 may be set appropriately according to the capacity of the memory 16. In the present embodiment, the clock on the write side is two clocks more than the clock on the read side.
No. 6 prevents reading of the last two clocks. On the other hand, if the clock on the writing side is smaller than the clock on the reading side, data that is not originally written is read accordingly. This memory 1
The write reset and read reset operations of No. 6 are performed within the horizontal blanking, and can be switched to the pedestal level in the subsequent stage, so that there is no problem at all.

The start data of horizontal scanning is determined by the coefficient detection circuit 1
8 is determined by the write reset pulse WRST outputted from That is, it is determined at the timing of the horizontal synchronization level Th. Therefore, the processing of the integer part of the difference in the number of clocks can be solved by the operation of the small-capacity memory 16 described above. The television signal converted to the line-locked rate of 910 × Fh in this manner is output from the output terminal 27. In the clock rate conversion circuit of the present invention, the video signal data that is not line-locked is converted into line-locked data by a small-scale circuit by an operation in combination with the processing of the integer part and the processing of the decimal part described above. be able to. If the number of signal channels is three, such as R, G, and B, three sets of the interpolation value generation circuit 15 and the small-capacity memory 16 may be provided, and the increase in hardware is small. .

In the present embodiment shown in FIG. 1, an interpolation value generation circuit 15 for generating an interpolation value from at least two consecutive sample points in a video signal using the shift coefficient obtained by the coefficient detection circuit 18. At the subsequent stage, the television signal is written using the first clock CK1 as the write clock, and the memory 16 that reads the second clock CK2 as the read clock is provided. A memory 16 may be provided. That is, after the process of shifting the decimal part of the difference of the number of clocks, the process of shifting the integer part of the difference of the number of clocks may be performed, or after the process of shifting the integer part of the difference of the number of clocks, A process of shifting the decimal difference of the number difference or less may be performed.

[0029]

As described in detail above, the clock rate conversion circuit of the present invention sandwiches the horizontal synchronization level set between the pedestal level and the leading end level of the horizontal synchronization signal, and sets the horizontal synchronization signal in the horizontal synchronization signal. The signal level of the two sample points closest to the sync level and the horizontal sync level
From the horizontal sync level located between the two sample points
Position from either of the two sample points
A coefficient detecting circuit for calculating a shift coefficient k expressed as the ratio of the position, the shift coefficient k obtained by the coefficient detection circuit
And two adjacent pixel data S1,
From S2, an interpolation value generation circuit for generating an interpolation value represented by k × S1 + (1−k) × S2, a video signal output from the interpolation value generation circuit or a video signal input to the interpolation value generation circuit And a memory for writing the first clock, which is the rate of the input signal, as the write clock, and reading the second clock of the other rate as the read clock. The clock rate of an input signal having a predetermined clock frequency can be converted to an arbitrary clock frequency. The configuration of the present invention also has the advantage that the scale of hardware increase is small even if the number of signals to be rate-converted increases.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

FIG. 3 is a block diagram showing a specific configuration of a coefficient detection circuit 18 in FIG.

FIG. 4 is a diagram for explaining the present invention.

FIG. 5 is a diagram showing a first conventional example.

FIG. 6 is a block diagram showing a second conventional example.

[Explanation of symbols]

 Reference Signs List 11 D flip-flop 12 Subtractor 13 Multiplier 14 Adder 15 Interpolated value generation circuit 16 Memory 17, 21 Low-pass filter 18 Coefficient detection circuit 20 Phase comparator 22 Voltage controlled oscillator 23 Divider 24 PLL circuit 25 Delayer

Claims (1)

(57) [Claims] 1. A clock rate converter for converting a television signal sampled by a first clock having a first frequency into a second clock having a second frequency which is an integral multiple of a horizontal synchronization frequency. In the circuit, two sample points closest to the horizontal sync level in the horizontal sync signal with the horizontal sync level set between the pedestal level and the leading level of the horizontal sync signal
From the signal level and the horizontal synchronization level,
Of the horizontal synchronization level located between the sample points of
Is the position from one of the two sample points.
A coefficient detection circuit for calculating a shift coefficient k expressed as a ratio of the position; a shift coefficient k obtained by the coefficient detection circuit ;
The two adjacent pixel data S1 and S2 in the signal
An interpolation value generation circuit for generating an interpolation value represented by k × S1 + (1−k) × S2; and a video signal output from the interpolation value generation circuit or a video signal input to the interpolation value generation circuit. And a memory for writing the first clock as a write clock and for reading the second clock as a read clock.