JP3158003B2 - Digital sync separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital sync separation circuit for separating a sync signal from a digital video signal.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional synchronous separation circuit of this kind. In FIG. 1, an input circuit 1 converts an analog video signal Va into a digital video signal Vd, converts an analog signal to an appropriate level by a built-in amplifier circuit and a clamp circuit, and then converts a system clock by an analog / digital conversion circuit. The digital signal is converted into a digital signal at the sampling cycle of Fck and output as a digital video signal Vd.

A low-pass filter (LPF) 2 removes a chroma signal and a noise component from a video signal and extracts only a luminance signal Yd so as not to affect the separation of the synchronization signal. The comparison circuit 3 compares the level of the luminance signal Yd with a threshold Th output from the data generation circuit 4 and
When the level of d is larger than the threshold value Th, a binary level “H” is output, and when the level is smaller, a binary level “L” is output.

The D-type flip-flop 5 latches the output of the comparison circuit 4 at the timing of the rising edge of the system clock Fck. Since the threshold value Th output from the data generation circuit 4 is set to a level near the center of the synchronization signal portion of the luminance signal Yd, the flip-flop 5 outputs the synchronization signal Sy having a negative polarity. .

[0005]

By the way, since the video signal is not always a standard signal, a VTR (video tape tape) is required.
As in the case of a reproduced signal of a recorder, there are a video signal (so-called non-standard signal) whose time axis changes and a signal whose amplitude value is unstable. Further, depending on the performance of the amplifier circuit and the clamp circuit in the input circuit 1, the DC voltage of the video signal fluctuates, and field time distortion (V sag) and line time distortion (H sag) occur.

Here, the operation of the conventional synchronization separation circuit when such an unstable signal is input will be described with reference to FIGS . 6 to 8 (in FIG. 6 to FIG. Easy
Yd is expressed in an analog form to make LPF
When the luminance signal Yd which is the output of No. 2 has jitter,
The sync separation output Sy fluctuates according to the jitter (FIG. 6). Although there is no inconvenience to the extent that the output synchronization signal moves in the same manner as the jitter, in the case of digital signal processing, the jitter is amplified in some cases because the signal is processed in clock units.

FIGS. 7 and 8 are diagrams in which a luminance signal is enlarged to a clock level. FIG. 7 shows a luminance signal Y with jitter.
d (Yd1, Yd2) is n-1 of the system clock Fck
Since it changes between the nth clock and the nth clock, the separated output Sy acts in a direction to absorb jitter.

FIG. 8 shows a luminance signal Yd (Yd
1, Yd2) changes from the (n-1) th clock to the (n + 1) th clock around the nth clock of the system clock Fck, so that only about 1/4 clock jitter is applied to the signals Sy1 and Sy2. In this case, it is expanded to one clock. Although there is a signal processing technique called TBC (Time Base Collector) for the fluctuation of the time axis, such a process has a disadvantage that the circuit scale becomes large and the device becomes expensive.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital type synchronous separation circuit capable of reducing jitter to a practically allowable range with a simple circuit configuration.

[0010]

A digital synchronization separation circuit according to the present invention compares a digital video signal with different first and second thresholds to separate the first and second synchronization signals; A delay amount determining circuit that determines a relative delay amount between the first and second synchronization signals, a delay circuit that delays the first synchronization signal by ク ロック clock, and a delay that is delayed by the first synchronization signal or the delay circuit A selection circuit for selecting one of the synchronization signals as an output synchronization signal, wherein the selection circuit delays when the delay amount determination circuit determines that the delay amount between the first and second synchronization signals exceeds one clock. The configuration is such that the synchronization signal delayed by the circuit is selected, and otherwise, the first synchronization signal is selected.

In this case, the delay amount discriminating circuit includes a first and second latch circuit for latching the first and second synchronization signals at the same timing, and a relative output between the outputs of the first and second latch circuits. And a jitter amount discriminating circuit for discriminating the actual delay amount.

[0012]

In the structure of the present invention, a digital video signal is separated into two types of synchronization signals by a comparison circuit. With the first synchronizing signal separated by the threshold of the higher levels of the separated two kinds of sync signals are input to one of the selection circuit, after being cast 1/2 clock late in the delay circuit, The third synchronization signal is input to the other of the selection circuits.

[0013] The two kinds of synchronization signals separated by the comparison circuit have their relative delays determined by a delay determination circuit.
If the delay exceeds one clock controls the selection circuit to select a third synchronization signal, first at all other times
The selection circuit is controlled so as to select the synchronization signal.

Thus, an error of one clock which can occur in the operation of the digital synchronization separation circuit can be reduced to an error of ク ロ ッ ク clock, and a range practically permissible for a subsequent digital circuit operating in units of one clock. Can be reduced to

[0015]

FIG. 1 is a block diagram showing an embodiment of the present invention. The same components as those of the conventional example shown in FIG. In this embodiment, the input circuit 1 converts the analog video signal Va from 8 to 1 with the system clock Fck .
The signal is converted into a digital video signal Vd of the 0th bit and output.

When separating the synchronization signal from the video signal, the LPF 2 removes a chroma signal and a noise component from the video signal and extracts only the luminance signal Yd so as not to affect the circuit at the subsequent stage. It is a pass filter.
The first and second comparison circuits 3a and 3b change the level of the luminance signal Yd to the first and second data generation circuits 4a and 3b.
a and 4b output from first and second thresholds Th
a and Thb, when the level of the luminance signal Yd is larger than the threshold value, it is “H” in a binary level;
A signal of "L" is output at the value level.

Since the two thresholds Tha and Thb are both set at a level near the center of the synchronization signal portion of the luminance signal, and the jitter in clock units must be determined, the level difference is determined by the synchronization portion of the luminance signal Yd. Is set to be about half the level of one clock (between the (n-1) th and nth). In this embodiment, T
ha> Thb.

First and second comparison circuits 3a and 3b
Are latched by the D-type flip-flops 5a and 5b constituting the first and second latch circuits, respectively, at the timing of the rising edge of the system clock Fck. As a result, two types of negative synchronization signals Sya and Syb are output from the flip-flops 5a and 5b.

The first negative polarity synchronizing signal Sya is supplied to a third flip-flop 5c, one input of a jitter amount discriminating circuit 6,
The signals are output to one input of the selection circuit 7, respectively. The flip-flop 5c latches the negative synchronizing signal Sya at the rising edge of the clock Fck bar obtained by inverting the system clock Fck by the inverting circuit 8, so that the output Syc is delayed by 1/2 clock from the output of the flip-flop 5a. It is output to the other side of the selection circuit 7 in the state.
A delay circuit is configured by the flip-flop 5c and the inverting circuit 8.

The second negative synchronizing signal Syb is output to the other input of the jitter amount discriminating circuit 6. The jitter amount discriminating circuit 6 is constituted by a circuit including an exclusive OR circuit. When the two signals Sya and Syb are of the same value, the signal is "L" at the binary level. Is output. Therefore, when the two signals Sya and Syb are separated by one clock or more, "H" is output, and when they are within one clock, "L" is output. The output of the jitter amount discriminating circuit 6 is used as a switching signal of the selecting circuit 7. The flip-flops 5a and 5b and the jitter amount determination circuit 6
Constitutes a delay amount determination circuit.

Next, the operation will be described (FIGS. 2 to 4).
In order to facilitate understanding, Yd is represented in analog form.
It is) . As described above, the luminance signal Yd output from the LPF 2 may have jitter due to time axis fluctuation, DC fluctuation, or the like, and the synchronization separation output Sy fluctuates in accordance with the jitter (FIG. 6). FIG. 2 shows the luminance signal Y
FIG. 8 is a diagram in which d is enlarged to the clock level, and in the conventional example, the sync separation output emphasizes jitter (FIG. 8). That is, this is an example in which the luminance signal Yd (Yd1, Yd2) with jitter changes between the (n-1) th clock and the nth clock of the system clock Fck.

In the case of the luminance signal Yd1, as shown in FIG. 3, the intersection with the thresholds Tha and Thb is the system clock F.
Since ck is between the (n-1) th clock and the nth clock, the negative synchronization signals Sya and Syb have the same value. Therefore, the output of the jitter amount discriminating circuit 6 becomes "L", and the selecting circuit 7 selects the synchronizing signal Sya and outputs this signal as the synchronizing separation signal Sy. In this case, it acts in the direction of absorbing jitter.

In the case of the luminance signal Yd2, as shown in FIG. 4, the intersection with the thresholds Tha and Thb is the system clock F.
It changes over the (n-1) th clock and the (n + 1) th clock around the nth clock of ck. For this reason,
The negative synchronization signals Sya and Syb are shifted by one clock.

Therefore, the output of the jitter amount discriminating circuit 6 becomes "L" at the (n-1) th clock, "H" at the nth clock, and "L" at the (n + 1) th clock. The circuit 7 selects the synchronization signal Sync and outputs this signal as the synchronization separation signal Sy.

In this case, the synchronization signal Syc is
Since the signal a is delayed by 1/2 clock, the synchronizing signal Sy (FIG. 8), which was conventionally emphasized to one clock, could be reduced to 1/2 clock in this embodiment. . If the number of clocks is reduced to about ク ロ ッ ク clock, it is effective because it is not practically inconvenient in many cases for a subsequent circuit that operates in units of one clock.

[0026]

According to the present invention, in the case where a jitter component is present in an input video signal, one clock which is considered to be operable in a digital circuit when separating a synchronization signal from the video signal is considered. Can be reduced to an error of 1/2 clock, and can be realized with a simple circuit configuration without requiring a large-scale circuit such as TBC.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

FIG. 3 is a waveform chart for explaining the operation of the present invention.

FIG. 4 is a waveform chart for explaining the operation of the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a waveform chart for explaining the operation of the conventional example.

FIG. 7 is a waveform chart for explaining the operation of the conventional example.

FIG. 8 is a waveform chart for explaining the operation of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input circuit 2 Low-pass filter (LPF) 3a, 3b Comparison circuit 4a, 4b Data generation circuit 5a, 5b, 5c Flip-flop 6 Exclusive OR circuit 7 Switch circuit 8 Inversion circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-54-53818 (JP, A) JP-A-55-159683 (JP, A) JP-A-61-255169 (JP, A) JP-A-61-255169 255170 (JP, A) JP-A-61-255171 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/04-5/12 H04N 5/91-5/956

Claims (2)

(57) [Claims] 1. A comparison circuit for comparing a digital video signal with different first and second thresholds to separate first and second synchronization signals, and a relative circuit between the first and second synchronization signals. A delay amount determining circuit that determines a delay amount, a delay circuit that delays the first synchronization signal by ク ロック clock, and an output synchronization of one of the first synchronization signal and the synchronization signal delayed by the delay circuit A selection circuit for selecting a signal as a signal, wherein the selection circuit determines whether the delay amount between the first and second synchronization signals exceeds one clock by the delay amount determination circuit, and the synchronization circuit delayed by the delay circuit. A digital synchronization separation circuit configured to select a signal and otherwise select the first synchronization signal. 2. The delay amount determining circuit according to claim 1, wherein the first and second latch circuits latch the first and second synchronization signals at the same timing, and output between the first and second latch circuits. 2. The digital synchronization separation circuit according to claim 1, further comprising a jitter amount determination circuit for determining a relative delay amount of the digital synchronization signal.