JP3348308B2 - Frame synchronization signal separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronizing signal separating circuit suitable for detecting a frame synchronizing signal in a video disk player of the MUSE system.

[0002]

2. Description of the Related Art A video disk player of the MUSE system has been developed. On a MUSE video disk, a MUSE high-definition television signal is FM-modulated and recorded. The MUSE video disk player demodulates the reproduction signal of the MUSE video disk and outputs a MUSE high-definition television signal. The output of the MUSE video disk player is supplied to a MUSE decoder. The MUSE decoder decodes the high definition television signal and its audio.

In such a MUSE video disk player, a signal of a frame cycle of the MUSE signal is required as a reference signal of a spindle servo or a TBC (time base collector). As a signal of this frame period, the line number 1 of the first field in the MUSE system is used.
2 are used.

FIG. 4 shows the configuration of a MUSE transmission signal. As shown in FIG. 4, a VIT signal for equalization and a frame pulse are inserted into line numbers 1 and 2 of the first field. Audio data is assigned to the line numbers 3 to 46. Line numbers 43 to 558 have C
Signals are assigned to the line numbers 47 to 562, and Y signals are assigned to the line numbers 47 to 562, respectively. Transmission control signals are assigned to the line numbers 559 to 563. The line number 563 is a clamp level.

[0005] The line number 564 of the second field is allocated for transmission of a program transmission control signal or the like. Audio data is assigned to the line numbers 565 to 608 of the second field. Line numbers 605 to 1120 are C signals, and line numbers 1121 to 1125 are transmission control signals.

The frame pulses of the line numbers 1 and 2 in the first field have a pattern as shown in FIGS. 5A and 5B. FIG. 5A shows a pattern of a frame pulse inserted in line number 1. FIG. 5B
Indicates the pattern of the frame pulse inserted in line number 2. As shown in FIGS. 5A and 5B, the frame pulse has a unique pattern, and the frame pulse of line number 1 and the frame pulse of line number 2 are inverted.

Conventionally, a frame pulse separation circuit has a structure in which a line number 1 and a line number 2 are inverted, a frame synchronization signal and a signal obtained by inverting a signal obtained by delaying the frame synchronization signal by four transmission clocks. Are configured to detect a frame pulse by utilizing the coincidence.

That is, as shown in FIGS. 6A and 6B,
The binarized frame pulse of line number 1 (FIG. 6A) and the binarized frame pulse of line number 2 (FIG. 6B) are inverted. Then, as shown in FIGS. 7A and 7B, 2
The pattern of the digitized frame pulse (FIG. 7A) and the signal obtained by inverting the frame pulse (FIG. 7B) delayed by four transmission clocks (240 nsec) match.

FIG. 8 shows an example of a conventional frame synchronization signal separating circuit for detecting a frame pulse in this manner. In FIG. 8, a binarized MU is input to an input terminal 101.
An SE signal is provided. This binarized MUSE signal is EX
The signal is supplied to one end of the -OR gate 102 and supplied to the other end of the EX-OR gate 102 via the 1H delay circuit 103. Also, the binarized MU from the input terminal 101
The SE signal is supplied to one end of the EX-OR gate 104, and the EX-O gate is output via the 4-clock delay circuit 105.
It is supplied to the other end of the R gate 104. The outputs of the EX-OR gates 102 and 104 are supplied to an AND gate 107. The output of the AND gate 107 is output from the output terminal 108.

The EX-OR gate 102 detects whether the pattern of the line number 1 and the pattern of the line number 2 are inverted. EX-OR gate 104
Thereby, it is detected whether or not the input pattern matches the inversion of the pattern delayed by four transmission clocks. The output of the AND gate 107 is output from the output terminal 108 as a frame pulse detection signal.

[0011]

Particularly, in a MUSE video disk, noise may be included in a reproduced signal due to a defect of the disk or the like. In the above-described conventional frame synchronization signal detection circuit, if noise is included in the frame pulse, the detection of the frame synchronization signal becomes impossible.

Accordingly, an object of the present invention is to provide a frame synchronizing signal separation circuit capable of reliably detecting a frame pulse in a MUSE signal even when noise is included.

[0013] The invention provides a frame synchronizing signal separation circuit for separating the frame synchronization signal from the video signal including a frame synchronization signal of a predetermined pattern, is binarized, Den
A shift to which an input signal pulsed by the transmission clock is supplied
Frame register and the output of the shift register
An inverter that reverses according to the pattern of the signal
Adder circuit that adds the output of the register and the output of the inverter
From the output of the adder circuit.
A pattern mismatch detecting means that the so that the pattern non
The pattern mismatch amount output from the match detection means and the detection level
And a frame synchronization signal from this comparison output.
Detection and set the detection level to zero according to the amount of noise.
Arbitrarily configurable, frame sync signal larger than
A frame synchronization signal separation circuit comprising a detection unit .

[0014]

In the present invention, the comparator provided with the output of the adder circuit is provided, the comparator compares the pattern mismatch amount output from the adder circuit with the detection level, and detects the frame synchronization signal from the comparison output. , The detection level can be set arbitrarily.

[0016]

The frame synchronization signal is detected by comparing the pattern of the input signal with the pattern of the frame synchronization signal. Then, the pattern mismatch amount is compared with the detection level, and the detection level can be set arbitrarily. Therefore, even if noise occurs, the frame synchronization signal can be reliably detected.

[0017]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an outline of a video disc player to which the present invention can be applied. In FIG. 1, reference numeral 1 denotes a video disk. On the video disk 1, a high-definition television signal of the MUSE system is FM-modulated and recorded. The video disc 1 is rotated by a spindle motor 2.

An optical pickup 3 is provided for the video disk 1. The output of the optical pickup 3 is supplied to a demodulation circuit 4 via a reproduction amplifier (not shown) and to a clock generation circuit 5. The clock generation circuit 5 forms a transmission clock having a frequency of, for example, 16.2 MHz based on the reproduced pilot signal. This transmission clock is supplied to the frame synchronization signal separation circuit 7.

In the demodulation circuit 4, the output signal of the optical pickup 3 is FM-demodulated.
A high-definition television signal of the SE system is output. The output of this demodulation circuit 4 is TBC (time base collector)
The signal is supplied to the circuit 6 and to the frame synchronization signal separation circuit 7.

The frame synchronizing signal separation circuit 7 detects a frame pulse transmitted at the first line number 1 and 2 of each frame and forms a reproduced frame synchronizing signal. The reproduced frame synchronization signal is supplied to the TBC circuit 6 and also to the spindle servo circuit 8.

The reference frame synchronization signal generation circuit 9 forms a reference frame synchronization signal from a reference transmission clock having a frequency of, for example, 16.2 MHz. This reference frame synchronization signal is supplied to the TBC circuit 6 and also to the spindle servo circuit 8.

The TBC circuit 6 writes a reproduction signal to a memory by using a write address advanced based on the reproduction frame synchronization signal from the frame synchronization signal separation circuit 7,
By reading the signal stored in the memory by the read address advanced based on the reference frame synchronization signal from the reference frame synchronization signal generation circuit 9, the time axis fluctuation component is removed. The output of the TBC circuit 6 is output from the output terminal 10.

The spindle servo circuit 8 controls the phase of the reproduced frame synchronization signal from the frame synchronization signal separation circuit 7 and
The phase of the reference frame synchronization signal from the reference frame synchronization signal generation circuit 9 is compared, and a signal based on the comparison output is supplied to the spindle motor 2 to control the rotation of the spindle motor 2.

FIG. 2 shows a specific configuration of the frame sync separation circuit 7. Referring to FIG.
A USE signal is provided. This MUSE signal is supplied to the high-pass filter 22. In the high-pass filter 22,
DC fluctuation components are removed. The output of the high-pass filter 22 is supplied to the comparator 23. Comparator 23
, The input signal is binarized. The output of the comparator 23 is supplied to the D flip-flop 24. The D flip-flop 24 is connected to the terminal 25 from the terminal 25 by, for example, 16.2 MH.
A transmission clock of z is supplied.

The output of the D flip-flop 24 is supplied to a shift register 26. The shift register 26 is supplied from a terminal 27 with a clock having a cycle, for example, four times the frequency of a transmission clock having a frequency of 16.2 MHz. With this clock, the shift register 26 outputs sampling data of the binary MUSE signal every four samples.

In response to the output of the shift register 26, the inverters 28, 2
, 28,... Are provided. That is, the binarized frame pulse has a pattern as shown in FIG. In this case, in response to an output terminal of the sample value _{T 2, T 4 ~T 34,} T 36 ~T 39 is output, an inverter 28,
,... Are provided.

The output of the shift register 26 and the output of the shift register 26 via the inverters 28, 28, 28,. The output of each input terminal is added by the addition circuit 29.

The output of the adding circuit 29 is supplied to a digital comparator 30. The digital comparator 30 is supplied with a detection level set value A from an input terminal 31. The digital comparator 30 compares the output B of the adder circuit 29 with the set value A of the detection level from the input terminal 31. From the output of the digital comparator 30, a frame pulse detection signal is obtained. The detection signal of the frame pulse is output from the output terminal 32.

Inverters 28, 28, 28,... Are provided between the shift register 26 and the adder circuit 29 in correspondence with the frame pulse pattern. Therefore,
When the frame pulse pattern is input, the addition circuit 2
9 is input with "0". The output of the adder 29 indicates how close it is to the frame pulse pattern. The smaller the output of the adding circuit 29, the more the pattern closer to the frame pulse pattern is input. If a pattern that completely matches the frame pulse is input, all “0” s are input to the adder circuit 29, so that the output B of the adder circuit 29 becomes “0”. If the input pattern does not exactly match the frame pulse pattern, the output of the adder circuit 29 will be "41".

When the output B of the adding circuit 29 becomes smaller than the detection level set value A from the input terminal 31 (B ≧ A), the digital comparator 30 determines that a pattern close to the frame pulse pattern has been input, and Is output. If the detection level setting value A from the input terminal 31 is increased, the frame pulse can be detected even when the amount of noise included in the reproduced MUSE signal is large. However, if the detection level setting value A is too large, the possibility of erroneous detection of a frame pulse increases. This detection level setting value A is the value of the reproduced MU.
It can be set as appropriate according to the amount of noise included in the SE signal.

In this example, the frame pulse of line number 1 is detected.
When detecting the frame pulse of line number 2 and
An EX-OR gate may be provided at the input stage of the shift register 26. A signal that changes between “1” and “0” on the first and second lines is supplied to one end of the EX-OR gate. With this signal, the signal input to the shift register 26 is inverted between the first line and the second line.

[0032]

According to the present invention, the frame synchronization signal is detected by comparing the pattern of the input signal with the pattern of the frame synchronization signal. Then, the pattern mismatch amount is compared with the detection level, and the detection level can be set arbitrarily. Therefore, even if noise occurs, the frame synchronization signal can be reliably detected.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a video disc player to which the present invention has been applied.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a waveform chart used for describing one embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating a MUSE transmission format.

FIG. 5 is a waveform diagram used to describe a MUSE frame synchronization signal.

FIG. 6 is a waveform diagram used to explain a conventional frame synchronization signal separation circuit.

FIG. 7 is a waveform diagram used for describing a conventional frame synchronization signal separation circuit.

FIG. 8 is a block diagram of an example of a conventional frame synchronization signal separation circuit.

[Explanation of symbols]

 Reference Signs List 1 video disk 7 frame synchronization signal separation circuit 26 shift register 28 inverter 29 addition circuit 30 digital comparator

Claims (1)

(57) [Claims] 1. A frame synchronization signal separating circuit for separating a frame synchronization signal from a video signal including a frame synchronization signal of a predetermined pattern, wherein an input signal binarized and pulsed by a transmission clock is converted into
The supplied shift register and the output of the shift register
Invert the force according to the pattern of the frame synchronization signal
An inverter, the output of the shift register and the
And an addition circuit for adding the output of the inverter.
A pattern mismatch amount detecting means from the output of the circuit to obtain a pattern mismatch amount, not the pattern output from the pattern mismatch detecting means
Compare the amount of coincidence with the detection level.
The synchronization level, and set the detection level to
Can be set arbitrarily larger than zero according to the amount of noise.
And frame synchronization signal detecting means.
Frame synchronizing signal separation circuits.