JPH0654221A - Digital video processor for television signal - Google Patents

Abstract

PURPOSE:To prevent the adverse influence given to the detection of the horizontal phase due to the fluctuation of a synchronizing separator circuit and a clock reproducing circuit and the change of the phase relation between the synchronizing signal of an input signal and the burst with a digital video processor for TV signals without deteriorating the following performance against the change of an input phase at the time of the horizontal phase detection. CONSTITUTION:An LPF 26 of an input horizontal phase detecting circuit suppresses the random and sharp change of a sampling point due to the high band component of the sampling result of a horizontal position serving as the output of a flip-flop 25, i.e., the fluctuation of a synchronizing separator circuit and a clock reproducing circuit. Meanwhile, a recursive filter consisting of an amplitude synthesizer 27 and the flip-flops 28 and 29 has a time constant double as much as a horizontal scanning period reduces the fluctuation of the horizontal phase caused by the fluctuation of the synchronizing separator circuit and the clock reproducing circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to television signal processing, and more particularly to a television image digital image processing apparatus useful for composite digital image signal processing.

[0002]

2. Description of the Related Art As a conventional digital image processing apparatus for television signals, there is provided a first sync separation circuit for separating a first sync signal (hereinafter referred to as WSYNC) from an analog composite input video signal, and an analog composite input. A first clock reproduction circuit for reproducing a first clock signal (hereinafter referred to as WCK) and a first subcarrier signal (hereinafter referred to as WSC) from a burst signal in the video signal, and an analog composite input video signal A / D converter that quantizes and quantizes, an input horizontal phase detection circuit that detects a timing pulse (hereinafter, referred to as WH) that determines a horizontal phase of an analog composite input video signal from WSYNC, WCK, and WSC, and a composite reference From the input signal to the second sync signal (hereinafter referred to as RSYNC)
And a second sync separation circuit for separating the second clock signal (hereinafter referred to as RCK) and a second subcarrier signal (hereinafter referred to as RSC) from the burst signal in the composite reference input signal. Clock recovery circuit, a reference horizontal phase detection circuit that detects a timing pulse (hereinafter, referred to as RH) that determines a reference horizontal phase from RSYNC, RCK, and RSC, and a variable delay that determines a delay amount based on WH and RH. Circuit, digital signal processing circuit for digital signal processing, RSYNC, R
There is a digital image processing device for a television signal, which includes a blanking processing circuit that generates a blanking signal based on CK and RSC and adds blanking to the output of the digital signal processing circuit, and a D / A converter.

[0003]

However, in the above-described conventional digital image processing apparatus for television signals, since the signal to be handled is a composite signal, the phase of the blanking to be replaced and the phase of the processed image and their respective reference composites. There are severe restrictions on the relationship of the horizontal phase to the input signal. In the above-mentioned conventional digital signal processing apparatus for television signals, the horizontal phase is adjusted so that the color phase of the output does not change due to the fluctuation of the sync separation circuit and the clock recovery circuit and the phase relationship between the SYNC and the burst of the input signal. In the detection of some, special consideration is given to the input and the reference input. For example, there is one in which a dead band is provided for each subcarrier for horizontal phase detection. However, in such a method, there is a problem in followability with respect to a pure change in the input phase, and when switching to a signal having a clearly different phase in the input stage, the output does not follow, and image synthesis in the latter stage of the device, etc. However, there is a problem that the phase shift occurs.

The present invention has been made in view of the above problems, and in a digital image processing apparatus of a television signal useful for composite digital image signal processing, the followability to a change in input phase in horizontal phase detection is impaired. Without this, it is possible to prevent the horizontal phase detection from being adversely affected by the fluctuation of the sync separation circuit and the clock recovery circuit and the change of the phase relationship between the SYNC and the burst of the input signal. An object is to provide a processing device.

[0005]

A television signal digital video processing apparatus according to the present invention comprises a first sync separation circuit for separating a first sync signal from an analog video signal,
A first clock reproduction circuit for reproducing a first clock signal and a first subcarrier signal from a burst signal in the analog video signal; an A / D converter for sampling and quantizing the analog video signal; An input horizontal phase detection circuit that inputs a first synchronization signal, the first clock signal, and the first subcarrier signal and outputs a first timing pulse that determines a horizontal phase of the analog video signal, A second sync separation circuit for separating the second sync signal from the reference input signal; and a second clock recovery circuit for recovering the second clock signal and the second subcarrier signal from the burst signal in the reference input signal. A second timing pattern for determining a reference horizontal phase by inputting the second synchronization signal, the second clock signal, and the second subcarrier signal. A reference horizontal phase detection circuit for outputting a clock signal, a variable delay circuit for receiving the output of the A / D converter and delaying the output with a delay amount based on the first timing pulse and the second timing pulse, A digital signal processing circuit for inputting the output of the variable delay circuit to perform digital signal processing, the second synchronization signal and the second
A blanking processing circuit for inputting the clock signal and the second subcarrier signal etc. to generate a blanking signal and adding the blanking signal to the output of the digital signal processing circuit; and a blanking processing circuit of the blanking processing circuit. In a digital image processing device for a television signal, which comprises a D / A converter for inputting an output and performing D / A conversion, the input horizontal phase detection circuit uses the first subcarrier signal as a clock. A 2-bit counter that counts a clock signal, a counter with a self-clearing that repeats an operation of counting the first clock signal up to 455 times using the first subcarrier signal as a clock, and the first synchronization signal that counts the first synchronization signal. Horizontal position sample latched by one clock signal and output as a sample pulse with one clock width A pulse generator, a first flip-flop for inputting the outputs of the 2-bit counter and the counter with self-clear using the sample pulse as a clock, and a low-pass filter for removing high-frequency noise at the output of the first flip-flop An amplitude synthesizer for adding the output of the low-pass filter and the feedback signal by weighting with a controllable amplification degree; A third flip-flop that receives the output of the second flip-flop as an input and outputs the feedback signal using the sample pulse as a clock; a first amplitude limiter that limits the amplitude of the output of the second flip-flop; The second that limits the amplitude of the output of the third flip-flop And the amplitude limiter,
A first rounding circuit for rounding the output of the first amplitude limiter, a second rounding circuit for rounding the output of the second amplitude limiter, an output of the first rounding circuit and the A first comparator for comparing the outputs of the first and second counters, and a second comparator for comparing the outputs of the second rounding circuit and the outputs of the first and second counters, OR that takes the logical sum of the output of the first comparator and the output of the second comparator
And a circuit, and the reference horizontal phase detection circuit has a circuit configuration equivalent to that of the input horizontal phase detection circuit.

The low pass filter may be an IIR filter in a digital filter.

[0007]

In the digital image processing apparatus for a television signal according to the present invention, the input horizontal phase detection circuit and the reference horizontal phase detection circuit are the high-frequency components in the result of the horizontal position sample which is the output of the first flip-flop, that is, the first high frequency component. Horizontal scanning composed of a low-pass filter for suppressing random and sharp changes in sample points due to fluctuations in the first sync separation circuit and the first clock recovery circuit, an amplitude synthesizer, and first and second flip-flops By using a recursive filter having a time constant that is twice as long as the period, it is possible to reduce fluctuations in the horizontal phase due to fluctuations in the first and second synchronization separation circuits and the first and second clock recovery circuits.

As a result, the digital image processing apparatus for television signals according to the present invention uses the line system circuit,
The first and second synchronization separation circuits and the first synchronization separation circuit without impairing the followability to changes in the input phase in horizontal phase detection.
Also, it is possible to prevent the horizontal phase from changing due to fluctuations in the second clock recovery circuit and changes in the phase relationship between the synchronization signal of the input signal and the burst.

In the digital image processing apparatus for television signals according to the present invention, it is preferable that the low pass filter for suppressing the change of the sampling points is composed of an IIR filter which is a digital filter.

[0010]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a digital image processing apparatus for television signals according to an embodiment of the present invention. As shown in FIG. 1, the digital image processing apparatus for a television signal according to the present embodiment uses a sync signal WSY from an analog composite input image signal which is an input signal.
A sync separation circuit 3 for separating NC, a clock reproduction circuit 4 for reproducing WCK which is a clock signal and WSC which is a subcarrier signal from a burst signal in an analog composite input video signal, and an analog composite input video signal which is sampled and quantized. A / D converter 2 to be converted to W
An input horizontal phase detection circuit 5 that detects WH that is a timing pulse that determines the horizontal phase of the analog composite input video signal from SYNC, WCK, and WSC, and an RSYNC that is a sync signal from a composite reference input signal that is a reference sync input signal. A sync separation circuit 10 for separating, a burst signal in the composite reference input signal from the burst signal RCK, and a subcarrier signal RS
Clock recovery circuit 11 for recovering C and RSYNC, R
Reference horizontal phase detection circuit 12 for detecting RH which is a timing pulse for determining the reference horizontal phase from CK and RSC
, A variable delay circuit 6 that determines a delay amount based on WH and RH, a video signal processing circuit 7 that performs digital video signal processing, and a blanking signal that generates a blanking signal based on RSYNC, RCK, RSC, etc. It comprises a blanking processing circuit 8 for adding blanking to the output of the circuit 7, and a D / A converter for D / A converting the output of the blanking processing circuit 8.

FIG. 2 shows an input horizontal phase detecting circuit 5 in the digital image processing apparatus for television signals shown in FIG.
It is a block diagram showing an example. The reference horizontal phase detection circuit 12 is also a circuit similar to the input horizontal phase detection circuit 5. The input horizontal phase detection circuit shown in FIG.
2 bit counter 23 that is cleared by WSC using WCK, 9-bit counter 24 with self-clear that repeats the operation of counting WSC 455 times using WCK, and 9 bits of the output of counter 24 as upper bits A high-order 1 bit in the output of 23 is combined as a low-order bit to form a 10-bit horizontal address, and a flip-flop 25 that samples the outputs of the counters 23 and 24 with a horizontal sample pulse and a flip-flop that uses the horizontal sample pulse as a clock are added. A low-pass filter 26 for the vertical direction component of the video signal, which is composed of a multiplier and a multiplier, an input A which is an output of the low-pass filter 26, and an input B which is an output of a flip-flop 29 described later.
And a weighted input K for weighted averaging, a flip-flop 28 using the output of the amplitude synthesizer 27 as a clock and the horizontal sample pulse as a clock, and an output of the flip-flop 28 as an input and using the horizontal sample pulse as a clock. Flip-flop 29 and flip-flop 28
An amplitude limiter 30 that limits the amplitude of the output of the flip-flop 29, and an amplitude limiter 31 that limits the amplitude of the output of the flip-flop 29.
A rounding circuit 32 that rounds the output of the amplitude limiter 30, a rounding circuit 33 that rounds the output of the amplitude limiter 31, and a counter 23.
And a comparator 34 for comparing the output of the counter 24 and the output of the rounding circuit 32, and a comparator 35 for comparing the output of the counter 23 and the counter 24 with the output of the rounding circuit 33.
And an OR circuit 36 that takes the logical sum of the output of the comparator 34 and the output of the comparator 35, a flip-flop 39 that inputs WSYNC and uses WCK as a clock, and the logical product of the output of the flip-flop 39 and WSYNC. It is composed of an AND circuit 40 and a flip-flop 41 which receives the output of the AND circuit 40 as an input and uses WCK as a clock.

Next, the operation of the digital image processing apparatus for television signals according to the present embodiment, which is constructed as described above, will be explained. In FIG. 1, the analog composite input video signal input to the apparatus from the input terminal 1 is A
/ D converter 2, sync separation circuit 3 and clock recovery circuit 4
Entered in. In the sync separation circuit 3, the sync part in the analog composite input video signal is separated as WSYNC. The clock recovery circuit 4 forms a phase-locked loop based on the subcarrier component of the burst portion in the analog composite input video signal, and the clock signal WCK and the subcarrier signal WS.
C and are played. And WSYNC, WCK and W
SC is input to the input horizontal phase detection circuit 5 at the next stage, and the input horizontal phase detection circuit 5 determines the input phase. A / D
The video signal converted into a digital signal by the converter 2 is
It is held in the variable delay unit 6 only for a period based on WCK.

On the other hand, the reference sync input signal input to the apparatus from the input terminal 13 is extracted by the sync separation circuit 10 and the clock recovery circuit 11 into RSYNC, RCK and RSC. These RSYNC, RCK and RSC
Is input to the reference horizontal phase detection circuit 12 to detect RH which is a timing pulse for determining the reference phase. This RH is input to the variable delay unit 6 together with RCK, and the reference phase is determined.

Thereafter, the video signal output from the variable delay unit 6 is subjected to predetermined video processing by the video signal processing circuit 7. Further, for the output of the video signal processing circuit 7, blanking data is created in the blanking processing circuit 8 from RSYNC, RH, RSC and RCK, and the blanking period is replaced. The output of the blanking processing circuit 8 is D / A converted by the D / A converter 9 and output to the output terminal 14 as an output signal of this device.

Next, the operation of the input horizontal phase detection circuit 5, which is the main part of the present invention, will be described in more detail. The counters 23 and 24 have two WCK cycles as one unit.
It is a counter that repeatedly counts up to 455 units and determines the horizontal position of WSYNC. Where W
The two cycles of CK are set as one unit because the RS-170A standard that defines the standard of the NTSC composite signal defines the phase relationship between the rising edge of SYNC and the subcarrier of the burst signal every other clock. is there.

In the flip-flop 39, the AND circuit 40 and the flip-flop 41, the WSYNC input from the input terminal 38 is converted into a signal having a width of one clock cycle of WCK and output to the flip-flop 25. The flip-flop 25 inputs these signals, samples the horizontal position indicated by WSYNC, and outputs a horizontal sample pulse. This horizontal sample pulse does not become a stable pulse due to fluctuations of the sync separation circuit 3 and the clock recovery circuit 4 shown in FIG. 1, so that the horizontal sample pulse is a signal for controlling the delay amount of the variable delay circuit 6 in the subsequent stage. When used as, the phase variation occurs for each scanning line.

In order to prevent this phase fluctuation, the digital image processing apparatus for television signals according to the present embodiment,
As shown in FIG. 2, the vertical low-pass filter 26 suppresses random and sharp changes in sample points due to fluctuations of the high-frequency component in the horizontal position sampling result, that is, the sync separation circuit 3 and the clock recovery circuit 4. . Further, a recursive filter having a time constant twice as long as the horizontal scanning period constituted by the amplitude synthesizer 27 and the flip-flops 28, 29 delays the response to the change of the sample point and averages with the sample point of the previous line. By doing so, it is possible to reduce the fluctuation of the horizontal phase due to the fluctuations of the sync separation circuit 3 and the clock recovery circuit 4 described above. Of course, the digital image processing apparatus for a television signal according to the present embodiment surely follows a pure phase change in the input phase with respect to the reference phase only by delaying the response.

After that, the horizontal position sampling result is subjected to amplitude limiting and rounding by the amplitude limiters 30 and 31 and rounding circuits 32 and 33, and is compared with the horizontal address by the comparators 34 and 35 to be a horizontal detection pulse. . Comparator 3
Since the horizontal detection pulses output from Nos. 4 and 35 are the pulses whose horizontal phase is detected every other line, respectively, they are logically ORed by the OR circuit 36 and output to the output terminal 37 and input to the variable delay unit 6 in the subsequent stage. Then, the horizontal phase is stably determined.

[0020]

As described above, according to the digital image processing apparatus for a television signal according to the present invention, the horizontal phase detection is adversely affected in the digital image processing apparatus for a television signal useful for composite digital image signal processing. With respect to the fluctuations of the sync separation circuit and the clock recovery circuit which influence, and the change of the relationship between the SYNC and the burst signal in the input signal, a low-pass filter and By using a line system circuit such as an IIR filter, fluctuations of the sync separation circuit and the clock recovery circuit, and a phase relationship between the SYNC and the burst of the input signal are maintained without impairing the followability to the change of the input phase in the horizontal phase detection. It is possible to prevent the horizontal phase from changing due to the change of.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital image processing device of a television signal according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an input horizontal phase detection circuit in the digital image processing apparatus for television signals shown in FIG.

[Explanation of symbols]

 23, 24; counter 25, 28, 29, 39, 41; flip-flop 26; low-pass filter 27; amplitude synthesizer 30, 31; amplitude limiter 32, 33; rounding circuit 34, 35; comparator 36; OR circuit 40 ; AND circuit

Claims (2)

[Claims] 1. A first sync separation circuit for separating a first sync signal from an analog video signal, and a first clock signal and a first sync signal from a burst signal in the analog video signal.
Clock reproduction circuit for reproducing the subcarrier signal of A, and A / S for sampling and quantizing the analog video signal
A D converter, an input for inputting the first synchronization signal, the first clock signal, and the first subcarrier signal to output a first timing pulse for determining a horizontal phase of the analog video signal. A horizontal phase detection circuit; a second synchronization separation circuit for separating a second synchronization signal from a reference input signal; and a second synchronization separation circuit for reproducing a second clock signal and a second subcarrier signal from a burst signal in the reference input signal. And a reference horizontal phase for outputting the second timing pulse for determining the reference horizontal phase by inputting the second clock signal, the second synchronization signal, the second clock signal, and the second subcarrier signal. A detection circuit and a variable delay circuit that receives the output of the A / D converter and delays the output by a delay amount based on the first timing pulse and the second timing pulse. , A digital signal processing circuit for inputting the output of the variable delay circuit to perform digital signal processing, and a block for inputting the second synchronization signal, the second clock signal, the second subcarrier signal and the like. A blanking processing circuit that generates a ranking signal and adds the blanking signal to the output of the digital signal processing circuit;
In a digital image processing device for a television signal, which comprises a D / A converter for inputting the output of the blanking processing circuit and performing D / A conversion, the input horizontal phase detection circuit outputs the first subcarrier signal. A 2-bit counter that counts the first clock signal as a clock; a counter with a self-clearing that repeats an operation of counting the first clock signal up to 455 times using the first subcarrier signal as a clock; A horizontal position sample pulse generator which latches the synchronization signal of 1) by the first clock signal and outputs it as a sample pulse of 1 clock width, and inputs the outputs of the 2-bit counter and the counter with self-clear using the sample pulse as a clock And the first flip-flop A low-pass filter for removing high-frequency noise in the output of the loop, an amplitude synthesizer for adding the output of the low-pass filter and the feedback signal with a controllable amplification weight, and the output of this amplitude synthesizer as an input to the sample pulse. A second flip-flop used as a clock, a third flip-flop which receives the output of the second flip-flop as an input and outputs the feedback signal using the sample pulse as a clock, and an amplitude of the output of the second flip-flop. A first amplitude limiter for limiting, a second amplitude limiter for limiting the amplitude of the output of the third flip-flop, and a first rounding circuit for rounding the output of the first amplitude limiter A second rounding circuit for rounding the output of the second amplitude limiter; an output of the first rounding circuit; A first comparator for comparing the output of the second counter with the output of the second rounding circuit, and a second comparator for comparing the output of the second rounding circuit with the outputs of the first and second counters. An OR circuit for taking the logical sum of the output of the comparator and the output of the second comparator, and the reference horizontal phase detection circuit has a circuit configuration equivalent to that of the input horizontal phase detection circuit. Video signal processing device for television signals. 2. The digital image processing apparatus for television signals according to claim 1, wherein the low-pass filter is an IIR filter in a digital filter.