JPS6323486A - Video signal processor - Google Patents

Abstract

PURPOSE:To make a false contour phenomenon caused at the time of quantization inconspicuons visually by providing a clamp circuit clamping an input video signal to a voltage different by a voltage corresponding to a half of the least significant bit at the time of A/D conversion. CONSTITUTION:A horizontal synchronizing signal in an input video signal is separated by a horizontal synchronizing separator circuit 22, a clamp voltage control circuit 21 applies 1/2 frequency division to the horizontal synchronizing signal to generate a control pulse having a period twice the horizontal scanning period being at a high level at a 1st horizontal scanning period and at a low level at the next horizontal scanning period. The video signal is clamped by the clamp circuit 23 with a DC voltage difference corresponding to a half of the least significant bit (LSB) at each horizontal scanning period and the result is fed to an A/D converter 4. Thus, the threshold level at the time of A/D conversion is increased/decreased by the voltage corresponding to the 1/2 LSB at each horizontal scanning period, and the location for production of false countour is changed alternately at each horizontal scanning period, the production of false countour of the video signal after D/A conversion 9 is made twice so as to make it inconspicuons.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal processing device that converts a video signal into a digital video signal using an analog/digital converter and then performs digital signal processing using an image memory. The present invention relates to a video signal processing device for making quantization errors associated with analog/digital conversion visually inconspicuous.

Background of the Invention In recent years, with the rapid development of semiconductor technology, large-scale digital circuits have been converted into LSIs, and high-speed analog/digital converters (hereinafter referred to as A/D converters) that can be operated in video notebooks,
Digital signal processing for consumer video equipment has become a reality, making it possible to implement digital/analog converters (hereinafter abbreviated as D/A converters).

Digitization of consumer video equipment such as TV receivers and video tape recorders has improved basic performance, efficient integration with new media equipment, stable and uniform quality, reduced number of parts, and improved service efficiency. At the same time, in recent years, with the adoption of digital memory and memory controllers that have significantly increased capacity and low cost, it has become possible to freeze the screen, parent and child screens (
Digital application devices with various unique features such as picture-in-picture (picture-in-picture) and multi-screen have been developed (
"Telehi Technology J 1986, VOL34, PI3)
.

FIG. 4 is an example of a digital video signal processing device using an image memory. In the figure, 1 is a video signal input terminal, 2
3 is a clock generator, 3 is a clamp circuit, 4 is an A/D converter, 6 is an image memory, 7 is a memory control unit, 8 is a microcomputer for giving instructions or data, etc. to the memory control circuit, 9 1 is a digital/analog converter (hereinafter abbreviated as a D/A converter), and 1o is a video signal output terminal.

The operation of the digital video signal processing device configured as described above will be described below.

First, the leading edge of the horizontal synchronizing signal of the input video signal input to the video signal input terminal 1 is fixed at a predetermined position by the clamp circuit 3, converted into a digital signal by the A/D converter 4, and written into the image memory 6. At this time, the memory control unit 7 controls the write address, read address, write and read timing, etc. of the image memory 6, and the memory control by the memory control unit 7 allows image compositing, image data thinning, Various functions such as removal of time axis fluctuations become possible. Furthermore, the data sent from the microcomputer (hereinafter abbreviated as microcomputer) 8 is for transmitting data such as mode commands for selecting the various functions mentioned above and address designation on the memory to the memory control unit 7. This makes it possible to change and specify various combinations and selections of functions, combinations with other devices, etc. using software. The digital signal that has been subjected to various conversion processes in the image memory 6 is converted into an analog video signal by the D/A converter 9 and output to the video signal output terminal 10.

In addition, as shown in FIG. 4 (17), the generation circuit 2 generates the sampling clock for the A/D converter 4 and D/A converter 9, and also controls the writing and reading timing of the image memory 6, and the transfer of digital data. It also serves as a reference clock for the generation of various timing pulses such as etc. Generally, the clock frequency is the horizontal synchronization signal in the input video signal divided by a predetermined frequency division ratio, or the frequency of the horizontal synchronization signal in the input video signal. 3 in synchronization with the carrier color subcarrier (burst signal) included in the
The value multiplied by ~4 is used.

With the above configuration, it is possible to digitize the video signal and store it in memory, allowing you to freeze the image, synchronize it with another input image, reduce the image size,
Although it is possible to have functions such as enlargement, it causes image quality deterioration peculiar to digital images when A/D converting and D/A converting the video signal.

As is well known, the most typical image quality deterioration due to original delta conversion is quantization error, which occurs in the video signal portion where the gradation changes slowly in reality. Where there is a correlation and the quantization level changes,
Contours can be seen that look like contour lines on a map, and this is called false contouring (``Digital Signal Processing of Images'' by Takahiko Fukinuki, Nikkan Kogyo Shimbun, p. 77).

For example, when a video signal as shown in Figure 5(a) is quantized, the waveform becomes a step-like waveform as shown in the figure (middle of the figure), and the quantization error is caused by two-dimensional low frequency components with high visual sensitivity (low spatial frequency component) and is recognized as a stationary false contour component on the screen. All video signals within one frame are shown in Figure 5 (a
), when the quantized signal ((b) in the same figure) is observed on a TV screen, vertical stripes like the one shown in Fig. 5(e) toward the dashed line are seen, which is visually pleasing. There will be no.

It is said that the above-mentioned false contour cannot be detected visually if the number of quantization bits is 7 bits, but 8 bits or more is required to achieve multiple calculations and high image quality. Therefore, in general, to perform high-quality digital processing, a quantization bit number of 8 bits or more is required.

Problems to be Solved by the Invention However, selecting the number of quantization bits to be 8 bits or more in the above configuration results in an increase in image memory and
Current consumer devices generally perform 6- to 7-bit digital processing, which increases the complexity of memory control units and increases the cost of A/D and D/A converters. This has had the problem of causing image quality deterioration such as S/N deterioration.

In view of the above-mentioned problems, the present invention makes it possible to make the false contour phenomenon that occurs due to quantization visually inconspicuous, and to obtain image quality that is substantially the same as when the number of quantization bits is increased by one bit. The present invention provides a video signal processing device.

Means for Solving the Problems In order to solve the above problems, the video signal processing device of the present invention converts an input video signal into a digital signal using an analog/digital converter, and then performs digital signal processing using an image memory. In a video signal processing device that performs When the output pulse of the 1/2 frequency divider is at a high level, the input video signal is clamped to the first clamp voltage, and when the output pulse of the 1/2 frequency divider is at a low level, the input video signal is clamped to the first clamp voltage. A clamp circuit configured to clamp the input video signal to a second clamp voltage that is higher or lower by a voltage equivalent to 1/2 of the least significant bit during analog/digital conversion; and the clamp circuit. The device has an analog/digital converter for converting the output of the digital signal into a digital signal.

Effect The present invention has the above-described configuration, and uses 1/1 of the least significant bit (LSB) as the clamp voltage of the video signal before A/D conversion.
Two types of clamp voltages, a first clamp voltage and a second clamp voltage, which differ by an input voltage corresponding to 2 are pumped. That is, the input video signal in the first horizontal scanning period is
The input video signal for the next second horizontal scanning period that is clamped to the first clamp voltage is clamped to a second clamp voltage that is higher (or lower) by 1/2LSB equivalent than the first clamp voltage, The input video signal is subjected to a DC shift of 1/2 LSB every horizontal scanning period.

By the above-mentioned clamp operation, the threshold level of the voltage comparator during A/D conversion is -1/2 LSB every horizontal scanning period.
Even when a video signal with a gradual gradation that moves up and down by a considerable amount and makes the aforementioned false contour phenomenon noticeable is input, the false contour occurrence position changes alternately every -horizontal scanning period, and the D/
The occurrence of false contours in the video signal after A-conversion is visually doubled as a two-dimensional frequency (spatial frequency) and becomes less noticeable.

Furthermore, in addition to the clamp voltage control described above, the image data after A/D conversion is delayed by one horizontal scanning period (hereinafter referred to as 1H).
The image data before the 1H delay and the image data after the 1H delay are compared, and if both image data are almost the same, that is, the line memory is If there is a correlation, the arithmetic unit averages (smoothes) the image data before and after the 1H delay, making it possible to increase the actual number of quantization bits by 1 bit.

This not only makes false contours visually less noticeable, but also
It has become possible to improve the S/N ratio including quantization noise.

Embodiment Hereinafter, a video signal processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the main blocks of a video signal processing device in a first embodiment of the present invention. In Figure 1, 1
is an input terminal, 2 is a clock generation circuit, 4 is an A/D converter, 6 is an image memory 17 is a memory control unit, 8 is a microcomputer, 9 is a D/A converter, 10 is an output terminal, 21 is a clamp voltage control 22 is a horizontal synchronization separation circuit, and 23 is a clamp circuit.

The operation of the video signal processing device configured as described above will be described below with reference to FIGS. 1 and 5.

First, the horizontal synchronization signal in the video signal input to input terminal 1 in FIG. A control pulse having a cycle twice as long as the horizontal scanning period is generated such that it is at a high level during one horizontal scanning period and at a low level during the next horizontal scanning period.

Further, the control pulse generated by the clamp voltage control circuit 21 is supplied to the clamp circuit 23, where when the control pulse is at a high level, the input video signal is clamped with a first clamp voltage v1, and when the control pulse is at a low level, the input video signal is clamped. At the level, the least significant bit (LSB) is lower than the first clamp voltage.
) is higher (or lower) by the input voltage equivalent to 1/2 of
The input video signal is clamped with clamp voltage 2. Thereby, the video signal is clamped by the clamp circuit 23 with a DC voltage difference corresponding to 1/2LSB every horizontal scanning period, and is supplied to the A/D converter 4.

In the A/D converter 4, the video signal is sampled and further converted into a digital signal in accordance with the clock pulse generated by the clock generation circuit 2. At this time, the video signal input to the A/D converter 4 is DC-shifted and clamped by an amount equivalent to 1'/2 LSB of the comparison voltage of the A/D converter 4 every horizontal scan. - The sampling waveform changes alternately every horizontal scanning period.

The situation will be explained using FIG. 6. FIG. 5(a) shows an input video signal, which is clamped by the clamp circuit 23 and then sampled by the A/D converter 4. It is assumed that the signal is clamped to the clamp voltage ■1 in the first horizontal scanning period. For example, the video signal after sampling is shown in Figure 5)
become that way.

In the next horizontal scanning period, the video signal is controlled by the clamp voltage control circuit 21, and the clamp voltage ■2 (vl<■2)
As shown in FIG. 5(C), the video signal after sampling is clamped to -the video signal before the horizontal scanning period (
The signal is sampled in a manner shifted upward by 1/2 LSB compared to FIG. 5(b)). In this way, −
The video signal processing device of the present invention is characterized in that the sampling point is sampled up and down in the amplitude direction by an amount equivalent to 1/2 LSB every horizontal scanning period.

The video signal sampled as described above is A/
After being further encoded and converted into a digital signal by the D converter 4, it is written to the image memory 6 based on the write timing controlled by the memory control unit 7 mentioned above, and is also specified by the microcomputer 8 by address control etc. Image data processing is performed according to the mode. Image memory 6, memory control section 7. After predetermined image data processing is performed by the microcomputer 8, the image data is read out based on read timing, and converted into an analog video signal by the D/A converter 9.

As described above, according to this embodiment, by clamping the video signal before A/D conversion to a clamp voltage that differs by an amount equivalent to 1/2LSB every horizontal scanning period, false contours that occur during quantization can be reduced. The phenomenon can be made visually less noticeable.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram of a video signal processing device showing a second embodiment of the present invention. The difference from the configuration in Figure 1 is that
In the figure, the false contour phenomenon described above is made less noticeable by switching the clamp voltage of the clamp circuit 23 every horizontal scanning period, but in FIG. The comparison voltage used during D conversion is raised or lowered by an amount equivalent to 1/2LSB every horizontal scanning period to make the false contour phenomenon less noticeable. That is, in FIG. 2, the video signal clamped to a predetermined voltage by the clamp circuit 3 is converted into a digital signal by the A/D converter 4, but at that time, the above-mentioned horizontal synchronization separation circuit 23 The comparison voltage control circuit 24 divides the horizontal synchronizing signal which is the output of
The comparison voltage value of the comparison voltage generation circuit 26 is controlled so that A/D conversion is performed by setting the value higher by an amount equivalent to /2 LSB. As a result, the same effects as in the first embodiment can be obtained.

As described above, the first embodiment and the second embodiment can obtain the same effect in terms of making the false contour phenomenon less noticeable, but they also make the false contour phenomenon less noticeable and the S/
In order to also improve the N ratio, the third embodiment shown in FIG. 3 is effective.

A third embodiment of the present invention will be described below with reference to FIG. In the figure, 1 is an input terminal, 2 is a clock generator, 3 is a clamp circuit, 4 is an A/D converter, 6 is an image memory, 7 is a memory control unit, 8 is a microcomputer, and 9 is a D
/A converter, 10 is an output terminal, 22 is a horizontal synchronization separation circuit, 24 is a comparison voltage control circuit, and 25 is a comparison voltage generation circuit, which is the same as the structure shown in FIG. The difference from the configuration shown in FIG. 2 is that line memory 27. Line correlation detection section 29. The two points are that a calculation section 28 is provided, and a line memory control section 26 is provided for controlling the line memory 27.

Here, the line memory 27 is a digital memory that can delay the digital video signal by one horizontal scanning period, and stores the digital video signal after A/D conversion, the signal delayed by one horizontal scanning period, and the signal before the delay. Line correlation detection section 2
9, and by detecting the difference between both signals, the amount of line correlation between both signals is detected. For landed fish where the line correlation amount is large, that is, the signal from one horizontal scanning period ago and the current signal are almost the same, the calculation unit 28 adds both signals, and the average value is output to the image memory 6. , when the line correlation amount is small, that is, when the signal from one horizontal scanning period ago is different from the current signal, the arithmetic unit 28 outputs the output signal of the A/D converter 4 to the image memory 6 as it is.

By performing the above operation, when the line correlation amount is large, adjacent horizontal scanning lines are averaged (smoothed), and the sample points during A/D conversion mentioned above are calculated every 1,000 horizontal scanning periods. This embodiment 1 moves by 1/2 LSB phase. In combination with the operation described in section 2, the number of quantization bits visually increases by one bit.

For example, considering the video signal of FIG. 6(a) having line correlation, Example 1. or A/D as mentioned above in 2.
The state of the video signal sampled by the converter 4 is as shown in FIG. 6(b) during the first horizontal synchronization period, and as shown in FIG. 5(c) during the next horizontal synchronization period. After performing digital averaging processing between lines by the line memory 27 and calculation unit 28, the D/A converter 9 converts the signal into an analog signal as shown in Fig. 6(d). Although the quantization width is doubled, the number of quantization bits is essentially increased by 1 bit. This makes the false contour phenomenon more noticeable, reduces quantization noise, and improves the S/N ratio.

Note that in the third embodiment, the line memory 27, the line correlation detection section 29. Although the arithmetic unit 28 has been described as performing digital processing after A/D conversion, it may also be processed analogously by a D/A conversion converter. In that case, it is necessary to use a COD or the like, which is an analog delay element, as the line memory 27.

Moreover, the clamp voltage control circuit 21 in the first embodiment
Although the comparison voltage control circuit 24 in the second embodiment has been described as a frequency divider that divides the horizontal synchronizing signal, it is also possible to switch the clamp voltage or the comparison voltage of the A/D converter every horizontal scanning period. Anything is possible if possible.

Effects of the Invention As described above, the present invention provides j/2LS per horizontal scanning period.
By providing a clamp circuit configured to clamp to a voltage that differs by the amount of voltage B and a frequency divider that divides the horizontal synchronization signal by 1/2 in order to control the clamp circuit, it is possible to eliminate quantization errors caused by quantization errors. The present invention makes the false contour phenomenon inconspicuous, and further includes a line memory, a line correlation detector for detecting the amount of line correlation, and an arithmetic unit configured to take the arithmetic average between lines when the amount of line correlation is large. By adding this, an effect equivalent to increasing the actual number of quantization bits by 1 bit can be obtained, and the S/N ratio can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal processing device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a video signal processing device according to a second embodiment of the present invention, and FIG. 3 is a block diagram of a video signal processing device according to a second embodiment of the present invention. FIG. 4 is a block diagram of a video signal processing device in the third embodiment, FIG. 4 is a block diagram of a conventional video signal processing device, and FIG. 5 is an explanatory diagram. 21... Clamp voltage control circuit, 22...
・Horizontal synchronization separation circuit, 23...clamp circuit, 2
4...Comparison voltage control circuit, 25...Comparison voltage generation circuit, 26...Line memory control section, 27...Line memory, 28...・・・
- Arithmetic section, 29. Middle... Line correlation detection section. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Figure 2 PA Figure 4 Figure 5

Claims (4)

[Claims] (1) A video signal processing device that converts an input video signal into a digital signal using an analog/digital converter and then performs digital signal processing using an image memory, which separates a horizontal synchronization signal from the input video signal. A sync separation circuit, a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit into 1/2, and a first clamp voltage when the output pulse of the 1/2 frequency divider is at a high level. When the input video signal is clamped and the output pulse of the 1/2 frequency divider is at a low level, the voltage is set to 1/2 of the least significant bit during analog/digital conversion compared to the first clamp voltage.
a clamp circuit configured to clamp the input video signal to a second clamp voltage that is either higher or lower by a corresponding voltage; and an analog-to-digital converter for converting the output of the clamp circuit to a digital signal. A video signal processing device comprising: (2) A video signal processing device that converts an input video signal into a digital signal using an analog/digital converter and then performs digital signal processing using an image memory, the horizontal synchronizing signal being separated from the input video signal. A sync separation circuit, a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit into 1/2, and a first clamp voltage when the output pulse of the 1/2 frequency divider is at a high level. When the input video signal is clamped and the output pulse of the 1/2 frequency divider is at a low level, the voltage is set to 1/2 of the least significant bit during analog/digital conversion compared to the first clamp voltage.
a clamp circuit configured to clamp the input video signal to a second clamp voltage that is either higher or lower by a corresponding voltage; and an analog-to-digital converter for converting the output of the clamp circuit to a digital signal. analog/
a line memory configured to delay the output of the digital converter by one horizontal scanning period; a line correlation detector configured to detect the amount of correlation between the line memory output and the output of the analog/digital converter; It is characterized by having an arithmetic unit configured to take an arithmetic average of the output of the analog/digital converter and the output of the line memory when the line correlation amount is large according to the detection output. video signal processing equipment. (3) Horizontal synchronization separation in which a horizontal synchronization signal is separated from the input video signal in a video signal processing device that converts an input video signal into a digital signal using an analog/digital converter and then processes the digital signal using an image memory. a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit into 1/2, a clamp circuit that clamps the input video signal to a predetermined voltage, and a 1/2 frequency divider. When the output pulse is at a high level, the first comparison voltage is used as the comparison voltage of the analog/digital converter, and the first comparison voltage is used as the comparison voltage of the analog/digital converter.
When the output pulse of the /2 frequency divider is at a low level, a second comparison voltage that is higher or lower than the comparison voltage of the analog/digital converter by a voltage equivalent to 1/2 of the least significant bit during analog/digital conversion is applied. and an analog/digital converter for converting the output of the clamp circuit into a digital signal. (4) Horizontal synchronization separation that separates a horizontal synchronization signal from the input video signal in a video signal processing device that converts an input video signal into a digital signal using an analog/digital converter and then processes the digital signal using an image memory. a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit into 1/2, a clamp circuit that clamps the input video signal to a predetermined voltage, and a 1/2 frequency divider. When the output pulse is at a high level, the first comparison voltage is used as the comparison voltage of the analog/digital converter, and the first comparison voltage is used as the comparison voltage of the analog/digital converter.
When the output pulse of the /2 frequency divider is at a low level, a second comparison voltage that is higher or lower than the comparison voltage of the analog/digital converter by a voltage equivalent to 1/2 of the least significant bit during analog/digital conversion is applied. an analog/digital converter for converting the output of the clamp circuit into a digital signal;
a line memory configured to delay the output of the analog/digital converter by one horizontal scanning period; a line correlation detector configured to detect the amount of correlation between the line memory output and the output of the analog/digital converter; It is characterized by having an arithmetic unit configured to take an arithmetic average of the output of the analog/digital converter and the output of the line memory when the line correlation voltage becomes large based on the line correlation detection output. A video signal processing device.