JPH06105286A - Jitter compensating circuit - Google Patents

Abstract

PURPOSE:To compensate a video jitter either in a reproduced video in a VTR, or at a video processing stage in a monitor. CONSTITUTION:An input analog video signal is converted into a digital signal by using a first clock signal 31 following up a horizontal synchronizing signal (HD) separated by a synchronizing separator circuit 6, and stored in a video memory 4. On the other hand, an average time per one line is calculated by a control part 8 from both the horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) separated from the input video signal by the synchronizing separator circuit 6, and a second clock signal 32 corresponding to the average time is generated by a VCO10. Then, the video data read from the memory part 4 are converted in D/A by a D/A conversion circuit 5 by using the second clock signal 32. The D/A conversion is operated at every average time of a constant value, so that even when the jitter is generated at an input stage, the jitter can be excluded (compensated) at the D/A conversion stage after the memory reading.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to compensation of jitter in a reproduced image in a VTR or an image processing stage in a monitor.

[0002]

2. Description of the Related Art Conventionally, several methods have been proposed for jitter compensation. As an example, mainly VT for business use
The principle diagram of the method adopted in R is shown in FIG. Hereinafter, the outline will be described with reference to FIG. A first variable delay line 22 and a second variable delay line 23 are provided as shown for the reproduced video signal 21. The reproduction horizontal sync signal separated from the reproduction video signal 21 by the horizontal sync separation circuit 24 and the reference horizontal sync signal 25 are compared in phase by the first phase comparator 26, and the first variable delay line 22 is connected by the phase difference. A video phase stabilizer to be controlled and a reproduction burst signal and a reference burst signal separated from a video signal 27 passing through the first variable delay line 22 by a color burst separation circuit 28.
The second and the second phase comparators 29 compare the phases with each other, and the color difference is controlled by the color phase stabilizer which controls the second variable delay line 23 according to the phase difference.

[0003]

SUMMARY OF THE INVENTION The present invention provides a jitter compensating circuit having a simple structure which is different in concept from the above technique and can be easily applied to a general household VTR, a monitor TV, or the like. To aim.

[0004]

According to the present invention, a PLL for generating a first clock signal following a horizontal synchronizing signal separated from an input video signal, and an analog video signal using the first clock signal are provided. An A / D conversion circuit for converting to digital, a means for storing a digital signal from the A / D conversion circuit in a memory section, and a time for one field from a vertical synchronizing signal separated from an input video signal and the horizontal synchronizing signal. And a number of lines in the one field and outputs a signal indicating an average time per line calculated based on the measurement, and a first unit for converting a digital output of the control unit into an analog signal. A D / A conversion circuit, a voltage controlled oscillator that generates a second clock signal based on the control of the output voltage from the first D / A conversion circuit, and the voltage controlled oscillator A second D / A conversion circuit for converting the memory data read from the memory unit from a digital signal into an analog signal by using a second clock signal, so as to compensate the jitter in units of horizontal lines. The present invention provides a jitter compensation circuit.

[0005]

The input analog video signal is converted into a digital signal by using the first clock signal that follows the horizontal synchronizing signal,
Capture (store) in memory. On the other hand, the average time per line is calculated from the horizontal sync signal and the vertical sync signal separated from the input video signal, and the second clock signal corresponding to this average time is generated. The video data read from the memory unit is D / A converted using the second clock signal. As a result of this D / A conversion being performed at the above-mentioned averaging time of a constant value, even if jitter has occurred at the input stage, this jitter is eliminated at the D / A conversion stage after memory reading.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A jitter compensation circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of a jitter compensation circuit according to the present invention. In the figure,
Reference numeral 1 is an analog input video signal, 2 is a video processing circuit for performing a predetermined predetermined processing on the input video signal 1, and 3 is a video processing circuit for converting the video signal after the processing by the video processing circuit 2 from analog to digital. A / D conversion circuit, 4
Is a memory unit for storing the video signal from the A / D conversion circuit 3, 5 is a second D / A conversion circuit for returning the video signal read from the memory unit 4 from analog to digital, and 6 is horizontal synchronization from the input video signal Signal (HD) and vertical sync signal (VD)
A sync signal separating circuit for separating the horizontal synchronizing signal (HD), a PLL circuit for outputting a first clock signal 31 following the separated horizontal synchronizing signal (HD) to the A / D conversion circuit 3, and a horizontal synchronizing signal for separating 8 1 from signal (HD) and vertical sync signal (VD)
A control unit that measures the time of the field and the number of lines in the one field and outputs a signal indicating the average time per line calculated based on the measurement, 9 is a digital output of the control unit 8 to an analog signal First D / A to convert
The conversion circuit, 10 is a voltage controlled oscillator (VCO) that generates a second clock signal 32 based on the output voltage of the first D / A conversion circuit 9.

Next, the operation of the present invention will be described. The analog input video signal 1 is subjected to predetermined processing by the video processing circuit 2 and then digitized by the A / D conversion circuit 3. The first clock signal 31 used for sampling in this conversion is a signal that follows HD and is supplied from the PLL 7. Digital video signals are sequentially stored in the memory unit 4. if,
When the input video signal 1 causes jitter, the storage of the memory unit 4 is also stored in that state. On the other hand, HD and VD separated from the input video signal 1 by the sync separation circuit 6 are input to the control unit 8. Since the HD and VD are synchronization signals, they can be treated as digital signals. The control unit 8 measures the time of one field from the VD and the number of lines in the one field from the HD. Further, the control unit 8 calculates the average time per line (Tm = 1 time of one field / number of lines) from this measurement, and outputs a digital signal corresponding to the Tm. The first D / A conversion circuit 9 converts the digital output from the control unit 8 into an analog voltage. The analog voltage becomes the control voltage of VCO10. The VCO 10 generates the second clock signal 32 based on the control voltage corresponding to the Tm.

Memory data is sequentially read from the memory section 4, and is sequentially converted back to analog by the second D / A conversion circuit 5. The second clock signal 32 is used for this D / A conversion. Since the second clock signal 32 is a signal based on the constant value Tm, each line is D / A at the time of the constant value Tm.
Will be converted. Therefore, even when the input video signal 1 causes jitter, the analog video signal of the horizontal period Tm (constant) is obtained at the stage of reading from the memory unit 4 and performing D / A conversion regardless of the presence or absence of jitter. Will be done. The constant horizontal period means that the one-field period is also constant. As described above, even if the jitter occurs at the input stage, a signal in which the jitter phenomenon is eliminated (compensated) can be obtained at the output stage. The average time Tm per line is an average time calculated based on HD and VD of the input video signal 1 and is different from the standard value in the so-called signal system (however, in terms of value. Approximate or equivalent). Therefore, even if the HD or VD cycle of the input video signal is slightly deviated from the standard value, the jitter compensation can be performed, which is one of the features of the present invention.

[0009]

As described above, according to the present invention, V
It is possible to compensate for a jitter phenomenon that occurs on a monitor of a TR reproduced image or another image by a simple configuration at the digital processing stage. Further, there is a feature that even if the synchronizing signal cycle of the input video signal is slightly deviated from the standard value, the jitter compensation can be performed. As a result, the image quality can be improved. In particular, it is considered that the improvement of the image quality according to the present invention is significant in view of the recent trend toward larger screens.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of a jitter compensation circuit according to the present invention.

FIG. 2 is a principal block diagram showing the principle of an embodiment of a conventional jitter compensation circuit.

[Explanation of symbols]

 1 Input Video Signal 2 Video Processing Circuit 3 A / D Conversion Circuit 4 Memory Section 5 Second D / A Conversion Circuit 6 Synchronous Signal Separation Circuit 7 PLL Circuit 8 Control Section 9 First D / A Conversion Circuit 10 Voltage Controlled Oscillator (VCO)

Claims (1)

[Claims] 1. A PLL for generating a first clock signal that follows a horizontal synchronizing signal separated from an input video signal, and an A / D converter for converting an analog video signal into a digital signal using the first clock signal. Circuit, means for storing the digital signal from the A / D conversion circuit in a memory section, time for one field from the vertical synchronizing signal and the horizontal synchronizing signal separated from the input video signal, and the number of lines in the one field And a first D / A conversion circuit for converting a digital output of the control unit into an analog signal, the controller outputting a signal indicating an average time per line calculated based on the measurement. A voltage-controlled oscillator that generates a second clock signal based on the control of the output voltage from the first D / A conversion circuit, and a second clock signal from the voltage-controlled oscillator are used. And a second D / A conversion circuit for converting the memory data read out from the memory section into a digital signal from an analog signal so as to compensate the jitter in units of horizontal lines. Compensation circuit.