KR950013829B1 - Time axis compensation system of image recording & reproducing machine - Google Patents

Abstract

The time axis correcting device for image record reproducing apparatus comprises: a record control signal generating unit for separating a brightness signal into horizontal and vertical synchronizing signals, generating a first record control signal synchronized with the horizontal synchronizing signal and a second record control signal with a cycle twice of the first record control signal and supplying them to a brightness data storing output unit and a croma data storing output unit; a field detecting unit for generating a pulse expanded by 1/2H in response to the horizontal synchronizing signal and outputting a field detecting signal by inputting the pulse and the vertical synchronizing signal; a frame reset generating unit for counting the field detecting signal and generating a reset signal every frame; and a read control signal generating unit for generating a pseudo horizontal synchronizing signal synchronized with the frame reset signal and supplying the first and second read control signals to the brightness data storing output unit and croma data storing output unit from the 1/2H point of a record starting point.

Description

Time base correction device of video recorder

1 is a block diagram of a time base correction apparatus of a video recording and reproducing apparatus according to the present invention.

2 is an operation waveform diagram for explaining the operation of FIG.

* Explanation of symbols for main parts of the drawings

2, 16: first and second analog / digital converter

1: Y / C separation part

4, 8, 19: 1st-3rd digital / analog changing part

3, 17: line memory 6: synchronization separator

5: addition unit 8: recording control unit

7: Phase locked loop circuit 10: Sync generator

9: read control unit 11: monostable multivibrator

12: field detector 13: reset signal generator

14 Chroma Decoder 15 Multiplexer

20: chroma encoder

이상 벗어나지 않는 지터(jitter)를 보정하는 시간축 보정장치에 관한 것이다.TECHNICAL FIELD The present invention relates to an apparatus for correcting a time axis of a video recording and reproducing apparatus, in particular within two fields.

A time axis correction device for correcting jitter that does not deviate abnormally.

In general, it refers to a phenomenon in which the width, frequency, and phase of a jitter periodic pulse waveform change due to noise, and the like, and the occurrence of jitter causes a decrease in resolution.

In the conventional case, the multi-function processing of the video tape recorder was difficult. In order to suppress the occurrence of jitter, the memory capacity is increased by adopting a method of applying an advance signal to the servo to control the jitter. There was an issue that was raised.

Accordingly, an object of the present invention is to provide a time-base correction device for a VTR that obtains a reliable TBC effect by correcting jitter that does not deviate by more than ½H by controlling the line memory in one frame period.

신장된 펄스를 발생하고, 상기 발생된 펄스와 수직동기신호를 입력하여 필드검출신호를 출력하는 필드검출수단과, 상기 필드검출수단으로부터 출력되는 필드검출신호를 계수하여 매 프레임마다 리세트신호를 발생하는 프레임 리세트 발생수단과, 상기 프레임 리세트 발생수단으로부터 출력되는 프레임 리세트신호에 동기된 의사 수평동기신호를 발생하고, 상기 의사 수평동기신호에 의해 기록시작점의

점으로부터 제1 및 제 2 독출제어신호를 상기 휘도데이타 저장 출력수단과 상기 크로마데이타 저장 출력수단에 공급하는 독출(read)제어신호 발생수단으로 구성됨을 특징으로 한다.According to an aspect of the present invention, a Y / C separation unit for separately outputting a luminance signal and a chroma signal, and digitally converts and stores the separated luminance signal in response to an input of a first recording control signal. A luminance data storage output means for outputting the stored data in response to an fish signal, and digitally storing the separated chroma signal in response to an input of a second recording control signal and in response to an input of a second read control signal. Converting the chroma data storage output means for outputting the stored data and the luminance data output from the brightness data storage output means into an analog signal, and converting the chroma data output from the chroma data storage output means into an analog signal, And a video output means for outputting a video signal by adding the converted luminance and chroma data. A time axis correcting apparatus of a video recording / reproducing apparatus, comprising: separating horizontal and vertical synchronizing signals from the separated luminance signals, wherein the first recording control signal and two of the first recording control signals synchronized with the separated horizontal synchronizing signals are separated; A recording control signal generating means for generating a second recording control signal having a double cycle and supplying the luminance data storing output means and the chroma data storing output means, and in response to the separated horizontal synchronization signal;

A field detection means for generating an extended pulse, inputting the generated pulse and a vertical synchronization signal to output a field detection signal, and counting the field detection signal output from the field detection means to generate a reset signal every frame And a pseudo horizontal synchronizing signal synchronized with the frame reset signal outputted from the frame reset generating means, and generating a recording start point by the pseudo horizontal synchronizing signal.

And a read control signal generating means for supplying the first and second read control signals to the luminance data storage output means and the chroma data storage output means from the point of view.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same reference numerals as much as possible even though they are displayed on different drawings. In addition, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be obvious to those skilled in the art. In the following description of the present invention, detailed descriptions of related well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention.

로 늘어나도록 조절하여 출력하는 단안정 멀티 바이브레이터(이하 "MMV"라 함)(11)와, 상기 동기분리부(6)로부터 검출된 수평동기신호(fh)와 수직동기신호(fv)를 입력하여 홀수 혹은 짝수 필드를 판별하는 필드검출부(12)와, 상기 짝수 혹은 홀수 필드 판별결과에 따라 2필드 리세트신호를 발생하는 리세트신호 발생부(13)와 상기 2필드 리세트신호에 락킹된 의사 수평동기신호와 독출 클럭을 발생하는 동기발생부(10)와, 상기 리세트신호발생부(13)로부터 출력되는 2필드 리세트신호를 입력하여 2필드 주기로 독출 시작이 기록 시작의

가 되도록 상기 제2 및 제 1 라인메모리(17,3)를 각각 제어하는 프레임 리세트로 동작하는 독출제어부(9)와, 상기 제 1 라인메모리(3)로부터 독출한 휘도신호(Y)를 상기 독출제어부(9)의 스위칭 상태에 따라 아날로그화 하는 제 1 디지탈/아날로그 변환부(이하 "DAC"라 함)(4)와, 상기 제 2 라인메모리(17)로부터 독출된 B-Y, B-Y신호를 상기 독출제어부(9)의 스위칭상태에 따라 아날로그화 하는 제2 및 제3DAC(18,19)와, 상기 아날로그화된 B-Y 신호와 B-Y신호를 엔코딩하여 원래의 크로마신호를 발생하는 크로마 엔코드(20)와, 상기 제1DAC(4)로부터 출력된 아날로그 디지탈 신호와 상기 크로마 엔코더(20)로부터 출력된 크로마신호를 가산하여 최종 비디오신호(VO)를 출력하는 가산부(5)와, 상기 상기 위상동기 루우프회로(7)로부터 발생되는 기록클럭을 소정 분주하여 상기 제1 및 제2ADC(2,16)를 스위칭하여 상기 제1 및 제 2 라인메모리(3,17)의 기록을 제어하는 기록 제어부(8)로 구성된다.1 is a block diagram of the present invention, a Y / C separator 1 for inputting a video signal VI to separate a luminance signal Y and a chroma signal C, and the luminance signal Y. And a phase synchronization loop circuit (PLL) 7 for generating a write clock locked to the horizontal synchronization signal, and a Y / C for detecting a horizontal synchronization signal and a vertical synchronization signal. A first analog / digital converter (hereinafter referred to as "ADC") 2 for digitalizing the analog luminance signal Y detected from the separating unit 1, and a first for recording and reading the digitally converted luminance signal. A line memory 3, a chroma decoder 14 for decoding the chroma signal C detected from the Y / C separation unit 1, and outputting BY and BY signals, and a chroma decoder 14 outputted from the chroma decoder 14; An analog multiplexer 15 for digitally converting a BY or BY signal and selectively outputting the BY or BY signal output from the multiplexer 15; A second ADC 16 for digitally converting the BY signal, a second line memory 17 for recording and reading the BY signal and the BY signal output from the second ADC 16, and an output from the synchronization separator 6; Width of the horizontal synchronization signal (fh)

Inputting a monostable multivibrator 11 (hereinafter referred to as " MMV ") 11 that is adjusted to extend and outputs a horizontal sync signal, and a horizontal synchronizing signal fh and a vertical synchronizing signal fv detected from the synchronizing separator 6 A field detector 12 for discriminating odd or even fields, a reset signal generator 13 for generating a two-field reset signal according to the even or odd field discrimination result, and a pseudo locked to the two-field reset signal The synchronization start unit 10 for generating the horizontal synchronization signal and the read clock and the two-field reset signal outputted from the reset signal generator 13 are inputted, and the reading start is started every two field periods.

Read-out control unit 9 operating in a frame reset for controlling the second and first line memories 17 and 3, respectively, and the luminance signal Y read out from the first line memory 3; BY and BY signals read from the first digital / analog converter (hereinafter referred to as "DAC") 4 and the second line memory 17 to be analogized according to the switching state of the read controller 9. The second and third DACs 18 and 19 for analogizing the switching controller 9 according to the switching state of the read control unit 9, and the chroma encoding for generating the original chroma signal by encoding the analogized BY and BY signals. (20), an adder (5) for adding the analog digital signal output from the first DAC (4) and the chroma signal output from the chroma encoder (20) to output a final video signal (VO), and the The first and second recording clocks generated from the phase locked loop circuit 7 are divided by Is configured to switch the 2ADC (2,16) to the recording control unit 8 for controlling the recording of said first and second line memories (3,17).

In the structure of FIG. 1, the ADC 2 and the line memory 3 correspond to the luminance data storage output means, and the chroma decoder 14, the multiplexer 15, the ADC 16 and the line memory 17 are chroma data. Corresponding to the storage output means, the DAC 4 (18.19), the chroma encoder 20, and the adder 5 correspond to the image output means. The synchronization separator 6, the PLL 7, and the recording controller 8 correspond to the recording control signal generating means, and the MMV 11 and the field detecting part 12 correspond to the field detecting means, and the reset signal is generated. The unit 13 is a frame reset generating means. The synchronization generating section 10 and the read control section 9 correspond to the read control signal generating means.

2 is an operation waveform diagram according to the present invention, where 2a is a recording vertical synchronization signal waveform, 2b is a recording horizontal synchronization signal waveform, and 2c is a monostable multivibrator 11 output waveform. (2d) is a field discrimination signal waveform, (2e) is a two-field reset pulse waveform, and (2f) is a horizontal synchronous output waveform of the synchronization generator 10.

Based on the above configuration, the operation of one embodiment of the present invention shown in FIG. 2 will be described in detail.

When the video signal VI is input, the Y / C separation unit 1 outputs the luminance signal Y and the chroma signal C separately. In the synchronization separator 6 inputting the luminance signal Y, the horizontal synchronization signal H Sync (fh) and the vertical synchronization signal V Sync (fv) shown in (2b) and (2a) of FIG. Detect. A phase locked loop (hereinafter referred to as PLL) 7 generates a write clock locked to the separated horizontal synchronizing signal fh and supplies it to the write controller 8. At this time, the recording clock has a frequency of 4fsc.

The recording control unit 8 which inputs the recording clock controls the first ADC 2 and the first line memory 3 which digitalize the analog luminance signal Y which is separated from the Y / C separation unit 1 and output. The digitally converted luminance signal is stored in the first line memory 3.

In addition, the chroma decoder 14 decodes the chroma signal C separately output from the Y / C separation unit 1, and outputs B-Y and B-Y signals of the color difference signal. At this time, the multiplexer 15 selectively outputs the BY or BY signal to the input terminal of the second ADC 16, and the second ADC 16 outputs the input BY or BY signal from the recording controller 8 to the 2fsc. Digital conversion is performed by the chroma write clock and written in the second memory 17. At this time, the recording controller 8 generates a clock of 2fsc divided by two divided by 4fsc of the recording clock output from the PLL circuit 7 and supplies it to the sampling clock of the second ADC 16.

로 늘어나도록 조절하여 출력한다. 특, 상기 MMV(11)는 상기 수평동기신호(fh)의 입력에 트리거되어

의 기간을 가지는 동기신호를 출력한다. 이때 필드 검출부(12)에서는 상기 동기분리부(6)로부터 검출된 수평동기신호(fh) 수직동기신호(fv)를 입력하여 (2d)에 도시된 바와 같이 홀수 혹은 짝수 필드를 판별한다. 상기 짝수 혹은 홀수 필드 판별 결과에 따라 리세트신호 발생부(13)는 제 2 도의 (2e)에 도시된 바와 같이 2필드 리세트신호(2FREST)를 발생하여 동기발생부(10)로 출력한다. 상기 2필드 리세트신호(2FREST)는 2필드의 초기 위치로부터

만큼 지연 출력된다. 상기 동기발생부(10)는 상기 2필드 리세트신호(2FREST)에 락킹된 수평동기신호를 제 2 도의 (2f)에 도시된 바와 같이 출력함과 동시에 2필드 리세트신호(2FREST)에 락킹된 4fsc의 독출클럭을 발생하여 독출제어부(9)로 인가한다. 그러므로 1프레임(frame)의 주기로 독출 동작을 하는 상기 독출제어부(9)는 2필드 주기로, 독출시작을 기록 시작의

가 되도록 상기 제 2 및 제 1 라인메모리(17,3)를 각각 제어하게 된다. 즉, 상기 제 1 라인메모리(3)에 저장된 휘도신호(Y)를 4fsc의 클럭으로 독출한 후 제1DAC(4)를 통해 아날로그화 하여 출력하게 된다.On the other hand, the MMV 11 is triggered by the synchronously separated horizontal synchronous signal fh so that the width of the horizontal synchronous signal output from the synchronous separation section 3 is as shown in 2C.

Adjust to increase the output. In particular, the MMV 11 is triggered by the input of the horizontal synchronization signal (fh)

A synchronization signal having a period of time is output. At this time, the field detector 12 inputs the horizontal synchronizing signal fh and the vertical synchronizing signal fv detected from the synchronizing separator 6 to determine odd or even fields as shown in 2d. According to the even or odd field discrimination result, the reset signal generator 13 generates a two-field reset signal 2FREST as shown in FIG. 2E and outputs it to the synchronization generator 10. The two field reset signal 2FREST is obtained from an initial position of two fields.

As long as the delay is output. The synchronization generator 10 outputs the horizontal synchronization signal locked to the two-field reset signal 2FREST and locks the two-field reset signal 2FREST as shown in FIG. 2F of FIG. A read clock of 4 fsc is generated and applied to the read control unit 9. Therefore, the read control unit 9, which performs a read operation at a period of one frame, has a two-field period to start reading the start of recording.

The second and first line memories 17 and 3 are respectively controlled to be. That is, the luminance signal Y stored in the first line memory 3 is read out with a clock of 4 fsc and then analogized and output through the first DAC 4.

On the other hand, the second line memory 17 reads a B-Y signal and a B-Y signal by providing a clock of 2fsc divided by 2 divided by 4fsc as a read clock. At this time, the BY signal and the BY signal read out from the second memory 17 are applied to the second and third DACs 18 and 19, respectively, and converted into analog signals, and the read agent is added to the second and third DACs 18 and 19. The clock of 4fsc output from the fisherman 9 is input. Therefore, the sampling rate of the luminance signal Y, the B-Y signal, and the B-Y signal is 4: 1: 1. The B-Y and B-Y signals analogized via the second and third DACs 18 and 19 are applied to the chroma encoder 20. The chroma encoder 20 encodes the BY signal and the BY signal to generate an original chroma signal, and the adder 5 outputs the analog luminance signal output from the first DAC 4 and the chroma encoder 20. The output chroma signal is added to finally output the video signal VO.

이내로 벗어나는 지터에 대하여 1프레임 리세트로 라인메모리를 제어하여 1프레임 주기로 아주 안정된 클럭으로 독출하게 할 수 있도록 보정함으로써 저렴한 가격으로 우수한 TBC 효과를 거둘 수 있는 잇점이 있다.The present invention as described above is within two fields

The advantage is that the TBC effect can be achieved at a low price by controlling the line memory with one frame reset for the jitter that deviates within a certain period so that it can be read out with a very stable clock in one frame period.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (4)

A Y / C separation unit for separately outputting a luminance signal and a chroma signal, and digitally converting and storing the separated luminance signal in response to an input of a first recording control signal and outputting the stored data in response to a first read control signal. A luminance data storage output means for performing digital conversion and storing the separated chroma signal in response to an input of a second recording control signal, and outputting the stored data in response to an input of a second read control signal. And converts the luminance data output from the luminance data storage output means into an analog signal, converts the chroma data output from the chroma data storage output means into an analog signal, and adds the analog converted luminance and chroma data to the image signal. To a time base correction apparatus of a video recording / reproducing apparatus having a video output means for outputting And a second recording control signal having a period doubled between the first recording control signal and the first recording control signal synchronized with the separated horizontal synchronization signal. And a recording control signal generating means for supplying to the luminance data storing output means and the chroma data storing output means, and in response to the separated horizontal synchronization signal.

A field detection means for generating an extended pulse, inputting the generated pulse and a vertical synchronization signal to output a field detection signal, and counting the field detection signal output from the field detection means to generate a reset signal every frame And a pseudo horizontal synchronizing signal synchronized with the frame reset signal outputted from the frame reset generating means, and generating a recording start point by the pseudo horizontal synchronizing signal.

And a read control signal generating means for supplying the first and second read control signals to the luminance data storage output means and the chroma data storage output means from the point of view. The recording control signal generating means according to claim 1, wherein the recording control signal generating means comprises: a phase-locking loop circuit for generating and supplying a recording clock locked to the horizontal synchronizing signal to a recording controller; And a recording control section for supplying the first recording control signal to the luminance data storage output means and for supplying the second recording control signal having a period twice as large as the first recording control signal to the chroma data storage output means. Device for correcting the time base of the video recording and playback device, characterized in that. The method of claim 2, wherein the field detection means, the width of the separated horizontal synchronous signal

Output from the monostable multi-vibrator and the monostable multi-vibrator

And a field detector for discriminating odd or even fields by inputting the extended sync signal and the vertical sync signal. 3. The time base of an image recording and reproducing apparatus according to claim 2, wherein the first recording control signal and the first read control signal are signals of 4fsc, and the second recording control signal and the second read control signal are 2fsc. Compensator.

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