JP3114180B2 - Synchronous discontinuity detector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization discontinuity detection device used in a television character multiplexing device, and more particularly, to a synchronization discontinuity in which a synchronization signal of a television signal exceeds a predetermined value from a standard state. The present invention relates to a synchronization discontinuity detection device that outputs a synchronization discontinuity detection signal when continuity occurs.

[Conventional technology]

When various types of character and graphic information are superimposed during an empty horizontal scanning period within the vertical blanking period of a television signal, the synchronization discontinuity of the television synchronization signal is reduced because the horizontal scanning period that can be superimposed is limited. If the value exceeds the allowable value, character data cannot be received. For this reason, when the synchronization discontinuity of the television signal exceeds the allowable value, it is necessary to stop the superimposition of the character data. Therefore, the superimposition of the character data is performed in accordance with the synchronization discontinuity detection signal output from the synchronization discontinuity detection device. Controlling processing.

A conventional synchronization discontinuity detection device compares a reference synchronization signal set in advance in a broadcasting station with a synchronization signal of a television signal on which character data is superimposed by a first comparison circuit, and averages the difference by an integration circuit. Then, the average value is detected, and the second comparison circuit compares the average value with a predetermined value, and outputs a synchronization discontinuity detection signal when the average value exceeds a predetermined value.

[Problems to be solved by the invention]

Since the above-described conventional synchronization discontinuity detection device detects the synchronization discontinuity by comparing with the reference synchronization signal, it is possible to detect the phase difference only with respect to the signal synchronized with the reference synchronization signal. Synchronous discontinuity cannot be detected for an asynchronous signal.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronization discontinuity detection device capable of detecting a synchronization discontinuity even for a signal that is asynchronous with a reference synchronization signal.

[Means for solving the problem]

The synchronization discontinuity detection device of the present invention is a synchronization discontinuity detection device that detects a synchronization discontinuity of a television signal on which character information and the like are superimposed during a horizontal scanning period within a vertical blanking period, A synchronization signal separation circuit for separating a composite synchronization signal including horizontal and vertical synchronization signals, a clock signal generation circuit for generating a clock signal at a frequency that is a positive integer multiple of the color subcarrier of the television signal, and the composite synchronization signal A vertical drive signal generation circuit for generating a vertical drive signal indicating a period including a vertical synchronization pulse and an equalization pulse before and after the vertical synchronization pulse (referred to as a vertical drive period), and a composite synchronization signal separated by the synchronization signal separation circuit into one A delay circuit that delays by a horizontal scanning period, and compares the composite synchronization signal that has passed through the delay circuit with the composite synchronization signal that is input to the delay circuit. A first exclusive OR circuit that outputs a difference between the first exclusive OR circuit and a signal output from the first exclusive OR circuit when the signal of the composite drive signal in the vertical driving period in the standard state is input. A storage circuit that stores in advance as a pattern signal, a read signal generation circuit that generates a signal for reading the standard pattern signal from the storage circuit in synchronization with the vertical drive signal and the clock signal, and a read signal that is read from the storage circuit. A second exclusive-OR circuit for comparing the standard pattern signal with an output of the first exclusive-OR circuit and outputting the difference, and an output of the first and second exclusive-OR circuits; Receiving the vertical drive signal and selecting the output of the first exclusive OR circuit during a period other than the vertical drive period, and selecting the output of the second exclusive OR circuit during the vertical drive period A switch for selecting an output of the circuit, a first integrating circuit for integrating and outputting the output of the switch with a preset time constant, and a time constant set according to a phase error of the clock signal. A second integration circuit for integrating the vertical drive signal, a synthesis circuit for synthesizing the outputs of the first integration circuit and the second integration circuit, and an output level of the synthesis circuit being equal to or higher than a preset value. And a comparison circuit that outputs a synchronization discontinuity detection signal when the signal becomes non-consecutive.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which a synchronizing signal separating circuit 1 for separating a synchronizing signal (a composite synchronizing signal including a horizontal and vertical synchronizing signal) of a television signal, a color subcarrier (3.58 MHz) clock signal generating circuit 2 for generating and outputting a clock signal S _C at 4 times the frequency of, and 1H from 9H period (hereinafter the vertical driving period including a vertical synchronizing pulse and before and after equalizing pulses thereof in the vertical blanking interval It referred) and outputs the delayed vertical drive signal generating circuit 3 for generating and outputting a vertical drive signal V _D of "0" level, the sync signal by one horizontal scanning period
1H delay circuit 4, a signal H ₁ indicating a difference between a synchronization signal delayed by one horizontal scanning period and a synchronization signal not delayed.
A first exclusive-OR circuit 5 that outputs a signal having a peculiar pattern output from the first exclusive-OR circuit 5 when a signal in a vertical drive period of a synchronization signal in a standard state is input. storage circuit 6 which stores in advance as a signal, a read signal generating circuit 7 for the vertical drive signal V _D receiving in synchronization with the clock signal S _C to generate a reading signal standard pattern signal from the memory circuit 6 outputs, signal second exclusive oR circuit 8 to output the difference by comparing the standard pattern signal is read out from the H ₁ and memory circuit 6, the vertical drive signal V _D
Inverter 9 inverts and outputs the code, the output signal H of the signal H ₁ and a first AND circuit 10 that receives the vertical drive signal V _D and outputs the logical product, said second exclusive OR circuit 8 _Two
And a second AND circuit 11, first and second AND circuit 10, 11 the logical OR signal receiving respectively the output signal of which receives a vertical drive signal V _D having passed through the inverter 9 outputs the logical product OR circuit 12 for outputting H ₃ , first integration circuit 13 for integrating and outputting OR signal H ₃ with a preset time constant, and vertical drive signal V _D with a time constant set according to a detection error A second integrating circuit 14 for integrating and outputting the outputs of the first integrating circuit 13, a combining circuit 15 for combining the respective outputs of the first integrating circuit 13 and the second integrating circuit 14, and monitoring the output level of the combining circuit 15 to set a predetermined value. and a comparator circuit 16 which outputs a synchronization discontinuity detection signal S _E indicating the discontinuities synchronization when it becomes equal to or greater than.

 Next, the operation will be described.

The synchronization signal S _S separated from the television signal by the synchronization signal separation circuit 1 detects a discontinuity of horizontal synchronization in the 1H delay circuit 4 and the first exclusive OR circuit 5 and generates a horizontal synchronization discontinuity signal H _1. Is output. On the other hand, the standard pattern signal S _P to be read from the memory circuit 6 at four times the frequency (cycle of about 70 nS) of the color subcarrier in a vertical driving period in synchronization with the vertical drive signal V _D (3.58 MHz), the second exclusive sum circuit 8 is compared with the horizontal synchronizing discontinuous signals H ₁ signal H ₂ indicating the difference between the standard pattern signal S _P output is outputted. Incidentally, in the vertical drive period, equalizing pulses and vertical sync pulses have different pulse widths and horizontal synchronizing signals, for a pulse period, the synchronization signal S _S is first exclusive OR circuit even normal 5 The signal H1 output from is not a "0" level, but a signal having a peculiar pattern. However, the signal H ₁ at this time is consistent with the standard pattern signal S _P which is recorded in the storage circuit 6. Now, the signal H ₂ of the second exclusive OR circuit 8 outputs if the synchronization signal S _S is successful synchronization signal is "0" level. Now, the horizontal synchronizing discontinuous signals H ₁ and the vertical drive signal
V _D is inputted to the logical product is outputted to the first AND circuit 10. In this case, since the vertical drive period signal level of the vertical drive signal V _D is "0", the horizontal synchronizing discontinuous signal H ₁ is output outside not only output the vertical drive period vertical drive period. The signal H ₂ and the vertical drive signal V _D having passed through the inverter 9 is input to the logical product to the second AND circuit 11 is output. In this case, since the signal level of the vertical drive signal V _D is inverted, the signal H ₂ is not outputted outside is output only the vertical drive period vertical drive period. Therefore, the OR circuit 12
From the signal H ₂ shows the difference between the standard pattern signal S _P in the vertical drive period, also outside the vertical drive period is output as the horizontal synchronizing discrete signal H ₁ is the signal H _3. The signal H ₃ is the first integrating circuit 13, and output is integrated with a time constant that is set in advance.

When the standard pattern signal _SP is read from the storage circuit 6, the frequency is four times the frequency of the chrominance subcarrier, that is, the period is about 70%.
Although a read signal is generated and read based on the nS clock signal, a phase error of 0 to 70 nS occurs because the phase of the color subcarrier and the phase of the horizontal synchronization signal do not always match.
To compensate for this phase error and a second integrator circuit 14 is provided to be integrated with a time constant set according to the vertical drive signal V _D to the phase error output. The output signals of the first and second integrating circuits 13 and 14 are combined by a combining circuit 15 and then compared with a preset value by a comparing circuit 16. is output synchronized discontinuous detection signal S _E indicating the.

The same operation can be performed if the frequency of the clock signal is a positive integer multiple of the color subcarrier frequency.

〔The invention's effect〕

As described above, according to the present invention, the standard pattern indicating the horizontal synchronization discontinuity of the standard synchronization signal is stored in the storage circuit in advance, and the standard pattern is synchronized with the synchronization signal of the television signal to be compared. Since the synchronization discontinuity is detected by detecting the difference by reading out and comparing, the synchronization discontinuity can be detected without the reference synchronization signal. In addition, since the second integration circuit is provided to compensate for the phase error accompanying the reading of the standard pattern, the detection accuracy of the synchronization discontinuity can be improved.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. 1 synchronization signal separation circuit 2 clock signal generation circuit 3 vertical drive signal generation circuit 4 1H delay circuit
5... First exclusive OR circuit, 6... Storage circuit, 7.
... a read signal generation circuit, 8 ... a second exclusive OR circuit,
9 ... inverter, 10 ... first AND circuit, 11 ... second AND circuit, 12 ... OR circuit, 13 ... first integration circuit, 14 ... second integration circuit, 15 …… Synthesis circuit, 16 ……
Comparator circuit, S _E ...... synchronization discontinuity detection signal, S _P ...... reference pattern signal, _S S ...... separated sync signal, V _D ...... vertical drive signal.

Claims (1)

(57) [Claims] An apparatus for detecting a synchronization discontinuity of a television signal on which character information or the like is superimposed during a horizontal scanning period in a vertical blanking period, wherein a horizontal and vertical synchronization signal is detected from the television signal. A synchronization signal separation circuit that separates a composite synchronization signal, a clock signal generation circuit that generates a clock signal at a frequency that is a positive integer multiple of the color subcarrier of the television signal, and a vertical drive period ( A vertical drive signal generation circuit for generating a vertical drive signal indicating a vertical synchronization pulse and an equalization pulse before and after the vertical synchronization pulse, and a delay for delaying the composite synchronization signal separated by the synchronization signal separation circuit by one horizontal scanning period. A first circuit for comparing the composite synchronizing signal passed through the delay circuit with the composite synchronizing signal input to the delay circuit and outputting a difference between the two. Another OR circuit, and a storage circuit for storing in advance a signal output from the first exclusive OR circuit as a standard pattern signal when a signal in the vertical drive period of the composite synchronization signal in a standard state is input. A read signal generation circuit for generating a signal for reading the standard pattern signal from the storage circuit in synchronization with the vertical drive signal and the clock signal; a read signal generation circuit for reading the standard pattern signal from the storage circuit; A second exclusive-OR circuit for comparing the output of the exclusive-OR circuit and outputting the difference, and receiving the outputs of the first and second exclusive-OR circuits and the vertical drive signal. A switch for selecting an output of the first exclusive OR circuit during periods other than the vertical drive period, and selecting an output of the second exclusive OR circuit during the vertical drive period. Switch means, a first integration circuit for integrating and outputting the output of the switch means with a preset time constant, and the vertical drive signal with a time constant set according to a phase error of the clock signal. A second integrating circuit for integrating, a combining circuit for combining outputs of the first integrating circuit and the second integrating circuit,
A synchronization circuit that outputs a synchronization discontinuity detection signal when an output level of the combining circuit is equal to or higher than a preset value.