JP3297753B2 - Scan converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan converter suitable for use, for example, when converting a video signal output from a personal computer into an NTSC video signal.

[0002]

2. Description of the Related Art Effective image data of a video signal output from a personal computer is, for example, 640 pixels × 48 pixels.
It is composed of 0 lines. On the other hand, effective screen data in an NTSC video signal is composed of 760 pixels × 480 lines. Therefore, when a video signal output from the personal computer is to be displayed on an NTSC television receiver, it is necessary to convert the video signal from the personal computer into an NTSC video signal. For this purpose, a scan converter is used.

[0003]

However, in the conventional scan converter, although the number of horizontal scanning lines per frame is changed to a predetermined value, the aspect ratio changes, so that the image becomes difficult to see. there were.

[0004] The present invention has been made in view of such a situation, and it is an object of the present invention to obtain a more easily viewable image.

[0005]

SUMMARY OF THE INVENTION First Scan of the Invention
The converter performs A / D conversion of an input video signal.
A / D conversion means and A / D conversion by the A / D conversion means
Storage means for storing the video data obtained, and
Dividing the read video data by an integer power of 2 and
Calculated by a combination of
Is the number of pixels corresponding to the video signal of the second system.
Generating means for generating new new pixels.
Sign.

[0006] The second scan converter of the present invention comprises an input scan converter.
A / D conversion means for A / D converting a video signal to be input
And the video data A / D converted by the A / D conversion means.
Storage means for storing the data, and video by the A / D conversion means.
A predetermined frequency used for A / D conversion of data
A clock generating means for generating a clock;
The wave number is determined by the number of pixels per line of the video signal of the first system.
And the number of pixels per line of the video signal of the second system
Of the input video signal and the reference clock of the input video signal.
Frequency setting means for setting according to
I do.

[0007]

In the first scan converter of the present invention,
Indicates that an input video signal is A / D converted and A / D converted
The converted video data is stored, and the read video data is stored.
Data is a combination of division and addition / subtraction by an integer power of 2.
And the number of pixels in the horizontal scan line is calculated by the second
New pixels, the number of pixels corresponding to the video signal of the
Generated.

[0008] In the second scan converter of the present invention
In this case, an input video signal is A / D converted and A / D converted.
The converted video data is stored, and the video data is A
A clock of a predetermined frequency used when performing / D conversion
Is generated and the frequency of the clock is
Number of pixels per line of signal and video signal of second system
Of the number of pixels per line and the input video
It is set in accordance with the reference clock of the E signal.

[0009]

FIG. 1 is a block diagram showing the configuration of an embodiment of a scan converter according to the present invention. The personal computer 1 operating with the reference clock of the frequency f _PC has R,
G and B analog video signals are output. The G signal is input to the processing circuit 9. Although not shown, a processing circuit similar to the processing circuit 9 that processes each of the R signal and the B signal is also provided, and these signals are input to those processing circuits.

The processing circuit 9 includes the personal computer 1
A / D converter 2 for A / D converting the G signal output from
A filter 3 for removing a flicker component of a video signal output from the A / D converter 2; and a memory 4 in which an output of the filter 3 is written, for example, a FIFO. The writing and reading of the memory 4 are controlled by a controller 5. The generation circuit 8 generates a read clock of a frequency f _NT (= 4f _SC : f _SC is a color subcarrier frequency of the NTSC system),
Output to the controller 5. The controller 5
, The write clock frequency f _W, which is generated in synchronization with the reference clock frequency f _PC is supplied.

The data read from the memory 4 is input to an aspect converter 6 so that the number of pixels per line is changed to a predetermined value. The data output from the aspect converter 6 is D / A converted by a D / A converter 7 and then output to a circuit (not shown).

A processing circuit for processing the R signal and the B signal has the same configuration as the processing circuit 9.

FIG. 2 shows a configuration example of the memory 4.
In this embodiment, the data output from the filter 3 is supplied to a memory (FIFO) 21 or 22 via a switch 24. Switch 2
4 is alternately switched to the upper side or the lower side in the figure every 1H. The switch 25 is switched upward or downward in the figure for each field. As a result, the video data for one field stored in the memory 21 or 22 becomes 1
The data is read alternately for each field and supplied to the aspect converter 6.

Next, the operation will be described. The G signal output from the personal computer 1 is A / D converted by the A / D converter 2. Clock f _W used at this time is synchronized with the reference clock f _PC used in the personal computer 1, the same frequency clock is used. The output of the A / D converter 2 is input to the filter 3, where the flicker component is removed. The data output from the filter 3 is supplied to the memory 4.

The switch 24 of the memory 4 is switched every 1H, and data of odd lines is written in the memory 21 and data of even lines are written in the memory 22. As this time controller 5 write clock f _W, the reference clock f in the personal computer 1
_Use the same frequency clock synchronized with _PC .

The controller 5 reads data from the memory 4 using the clock of the frequency f _NT output from the generating circuit 8 as a reading clock. At this time, switch 25
Is switched for each field in the NTSC video signal. That is, the data written in the memory 21 is read in the odd field, and the data written in the memory 22 is read in the even field. Thus, the non-interlaced video signal is converted into an interlaced video signal and output.

The data read from the memory 4 is input to the aspect converter 6, and the number of pixels is changed. That is, for example, when the number of pixels for one line read from the memory 4 is 640, the number is changed to 760. The output of the aspect converter 6 is D / A converted by the D / A converter 7 and output to an NTSC monitor (not shown) for display.

FIG. 3 schematically shows a screen displayed by the above processing. That is, one frame of non-interlaced data output from the personal computer 1 is composed of 640 pixels × 480 lines, and this data is a signal composed of 760 pixels × 480 lines of data per frame. It is converted to

FIG. 4 shows a configuration example of the aspect converter 6. In this example, after the data output from the memory 4 is latched by the latch circuit 31, the data read from the latch circuit 31 is transferred to the circuit 30 and the circuit 4.
0 is supplied. The circuit 30 shifts the data output from the latch circuit (D) 31 by a predetermined bit and substantially divides the data by 2 ⁿ , and converts the output data of the bit shifter 32 as necessary. An exclusive-OR (EXOR) circuit 33 that outputs data of opposite polarity, an AND gate 34 that gates the data output from the latch circuit 31, and an EXOR
It comprises a circuit 33 and an adder (ADD) 35 for adding the output of the AND gate 34.

The circuit 40 includes a latch circuit 41, a bit shifter 42, an EXOR circuit 43, an AND gate 44, and an adder 45, like the latch circuit 31, the bit shifter 32, the EXOR circuit 33, the AND gate 34, and the adder 35. Have been. That is, data that is one clock earlier than the data being processed by the circuit 30 is processed by the circuit 40, as in the case of the circuit 30.

The circuit 30 (adder 35) and the circuit 4
The output of 0 (adder 45) is added by adder 51,
The data is output to the selector 52. The other terminal of the selector 52 has blank data (black data)
Is supplied. The selector 52 selects one of the blank data and the output of the adder 51, and outputs the selected data via the latch circuit 53. The selector 52 adds blank data as necessary in order to adapt the number of lines to the number of lines in the NTSC system. For example, when the number of lines for one frame written to the memory 4 is 400, 40 black data are added to the upper and lower portions of the screen, and the number of lines for one frame is changed to 480. Is done.

The counter 61 outputs N
Counting the clock of frequency f _NT of TSC method, and outputs the count value to the ROM 62. ROM62
Are predetermined timing signals AS00 to AS11, AG0, AG1, AC corresponding to the count value of the counter 61.
0, AC1, AA0, AA1, AS, AA, AG, AC
Is generated and supplied to each circuit.

As described above with reference to FIG. 3, in this circuit, 640 pixels are converted to 760 pixels per line. That is, six pixels are generated from five pixels. Therefore, for example, as shown in FIG. 5, a pixel c is formed between the pixels a and b. At this time, when the distance between the pixels a and b is 1 and the distance between the pixels a and c is α (accordingly, the distance between the pixels b and c is 1−α), the pixel c
Is generated by weighting of the following equation. c = a × (1−α) + b × α

In the embodiment shown in FIG. 4, α is sequentially changed every clock as shown in Table 1. That is, α
Are sequentially changed in the order of 1, 7/8, 3/4, 1/4, 1/8, 0. As a result, 1-α is 0, 1/8, 1/4,
It is sequentially changed every clock in the order of 3/4, 7/8, 1.

[0025]

[Table 1]

In the embodiment of FIG. 4, 7/8 is (1-
1/8), 3/4 are calculated as (1-1 / 4), and 1
/ 8, 1/4 means that the data is 3 bits or 2 bits L
It is calculated by shifting to the SB side.

When the coefficient is further multiplied by 0, the bit shift amount in the bit shifter 32 is set to 0 and EXOR
The polarity of the data is inverted by the circuit 33, and the data supplied from the AND gate 34 is added to the data by the adder 35. In addition, when multiplying by a coefficient 1, the bit shift amount in the bit shifter 32 is set to 0 and the EXO
The polarity inversion in the R circuit 33 is not performed, and the AND gate 34 is turned off.

For example, the data latched by the latch circuit 31 is shifted by 3 bits to the LSB side by the bit shifter 32 and is multiplied by ８. The output of the bit shifter 32 is input to the EXOR circuit 33, the polarity of which is inverted, and then input to the adder 35. Since the data output from the latch circuit 31 is input to the adder 35 via the AND gate 34, the adder 35 eventually outputs a value obtained by multiplying (1-1 / 8) by the original data. Become.

At this time, if the bit shift amount in the bit shifter 32 is 2, the operation of (1-1 / 4) can be executed.

The AND gate 34 is closed, and the bit shift amount in the bit shifter 32 is set to 2
If the data output from the bit shifter 32 is output as it is without inverting the polarity in the EXOR circuit 33 and the EXOR circuit 33 outputs the data, the output of the adder 35 becomes 1/4 times the original data.

Further, in this case, if the bit shift amount in the bit shifter 32 is 3 bits, the original data becomes 1/8 times the data.

As described above, the conduction state of the AND gate 34 is set to the conduction state or the non-conduction state by the timing signal AA0, and the shift amount of the bit shifter 32 is determined by the timing signal AS.
00, AS01 and AG0, and EX
By controlling the polarity inversion operation or non-inversion operation of the OR circuit 33 by the timing signal AC0, the original data can be multiplied by a coefficient of α or (1−α) as shown in Table 1. it can.

As described above, the circuit 40 includes the latch circuit 4
Except for 1, the configuration is the same as that of the circuit 30. Therefore, in the circuit 40, the same processing as in the circuit 30 is performed on the data latched by the latch circuit 31 with the output of the latch circuit 31 (data one clock before the data being processed by the circuit 30). be able to.

Therefore, in the circuit 30 and the circuit 40, the b × α operation and the a × (1-α) operation are performed on the current pixel b shown in FIG. Are performed, and when both are added by the adder 51, c (= a × (1−α) + b × α) can be obtained.

FIG. 6 schematically shows the operation in FIG.
It becomes as shown in. That is, 7/8, 1 /
New data is interpolated by multiplying and adding one of the coefficients of 8, 3/4, 1/4, 1, 0, thereby obtaining 6 pixels from 5 pixels. I have.

As shown in FIG. 6, according to such weighting, the interpolated data is not given equal weighting to the original data, and thus cannot be necessarily balanced weighting.

In other words, in order to achieve balanced weighting, it is necessary to perform weighting of 1/5 to 5/5 as shown in FIG. However, such multiplication of coefficients in units of 1/5 cannot be performed by a simple configuration. On the other hand, the coefficient in FIG.
Since 2 is used as a unit, multiplication can be performed by combining bit shift and addition / subtraction.
Therefore, as shown in FIG. 6, it is preferable to perform processing in units of 2 ⁿ .

FIG. 8 shows a second embodiment of the scan converter according to the present invention. In this embodiment, FIG.
In this embodiment, the aspect converter 6 is omitted,
Instead, a clock generation circuit 17 is provided.

The clock generation circuit 17 includes an OR gate 11 to which a G signal and a synchronization signal output from the personal computer 1 are input, a synchronization separation circuit 12 for separating a synchronization signal from an output of the OR gate 11, and a synchronization separation circuit 12. A phase comparison circuit 13 for comparing the output with the output of the frequency divider 16, a low-pass filter (LPF) 14 for smoothing the output of the phase comparison circuit 13, and a predetermined frequency f _Wa corresponding to the output of the low-pass filter 14. (VXO) 15 that generates the clock of (1) and the frequency of the horizontal synchronization signal output from the synchronization separation circuit 12, and controls the frequency division ratio (m / n) of the frequency divider 16 according to the determination result. And a determination circuit 18 that performs the determination.

Phase comparison circuit 13, low-pass filter 1
4. The oscillator 15 and the frequency divider 16 constitute a so-called PLL. The clock f _W generated by the oscillator 15 is supplied as a write clock of the clock and the memory 4 A / D converter 2. Other configurations are
This is the same as in FIG.

The synchronization separation circuit 12 separates the horizontal synchronization signal superimposed thereon from the G signal supplied from the OR gate 11. When the synchronization signal is not superimposed on the G signal, the horizontal synchronization signal is separated from the synchronization signal output from the personal computer 1. Phase comparing circuit 13, low-pass filter 14, PLL consisting of oscillator 15 and frequency divider 16 generates a clock f _W phase synchronized with the horizontal synchronizing signal separated by the sync separation circuit 12. The determination circuit 18 determines the frequency of the horizontal synchronization signal separated by the synchronization separation circuit 12, and sets the frequency division ratio of the frequency divider 16 to a predetermined integer ratio m / n according to the determination result.

[0042]

[Table 2]

Table 2 shows the frequency f _H of the horizontal synchronization signal separated by the synchronization separation circuit 12, the reference clock f _PC of the personal computer 1, the write clock f _Wa output from the oscillator 15, and the frequency divider 16 In relation to the frequency division ratio. For example, a personal computer of Company M has a horizontal scanning frequency f _H of 35.0 kHz and a reference clock f _PC of 30.24 MHz. Similarly, I's computer, f _H and f _{P C,} respectively 31.469kHz
And 25.175 MHz, and the personal computer of Company P is 24.826 kHz and 21.0526 MHz.
It is.

The decision circuit 18 by determining the horizontal synchronizing frequency f _H, determines the reference clock f _PC to the personal computer is used. Then, in accordance with the determination result, the frequency division ratio of the frequency divider 16 is set to a predetermined integer ratio. For example, when the personal computer 1 is a computer of company M, the frequency division ratio is set to 1026, and when the personal computer 1 is a computer of company I or a computer of company P, the frequency division ratio is set to 950 or 1007, respectively. You. This frequency division ratio is determined as follows.

That is, for example, since the reference clock of the personal computer of Company I is 25.175 MHz, 1
The number of pixels (number of data) per line from 640 to 76
First, this reference clock is set to 76
The frequency 29.853125 multiplied by 0/640 (= 2
5.175 × 760/640 MHz). To accurately generate this frequency by the PLL, the frequency divider 1
The division ratio at 6 becomes a non-integer. Therefore, the division ratio can be set to an appropriate integer, and 29.8
As a frequency close to 954125 MHz, for example, 29.
895550 MHz is selected. At this time, 950 is selected as the frequency division ratio. In this way, 3
By setting the frequency division ratio to 950 from the frequency of 1.469 kHz, the clock f of 29.895550 MHz is set.
_Wa can be generated.

When the clock is set in this manner and supplied to the A / D converter 2, the number of samplings per line increases from 640 to 760. Therefore, the video signal output from the personal computer 1 can be displayed with the aspect ratio of the NTSC system.

[0047]

According to the first scan converter of the present invention,
Then, the input video signal is A / D converted and A / D converted.
The converted video data is stored and the read video data is stored.
To a combination of division and addition / subtraction by an integer power of 2
The number of pixels in the horizontal scanning line is calculated according to the second method.
Generate new pixels with the number of pixels corresponding to the video signal
So, while converting the number of lines, and
The aspect ratio can be set to a desired value.

According to the second scan converter of the present invention,
For example, the input video signal is A / D converted and A / D converted.
And stores the converted video data in an A / D conversion.
Generates a clock of a predetermined frequency used when switching
Then, the frequency of the clock is set to one of the video signals of the first system.
Number of pixels per line and one line of video signal of the second system
Of the input video signal
Since the setting is made in accordance with the reference clock, the aspect ratio can be set to a desired value.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a scan converter according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a memory 4 of FIG. 1;

FIG. 3 is a diagram illustrating a change in aspect ratio in the embodiment of FIG.

FIG. 4 is a block diagram illustrating a configuration example of an aspect converter 6 of FIG. 1;

FIG. 5 is a diagram illustrating the operation of the circuit 30 of FIG.

FIG. 6 is a diagram showing an example in which the pixel data of FIG.
FIG. 4 is a diagram illustrating a state in which pieces of pixel data are generated.

FIG. 7 is a diagram schematically illustrating a case in which six pixel data are equally obtained from five pixel data.

FIG. 8 is a block diagram showing a configuration of another embodiment of the scan converter of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Personal computer 2 A / D converter 3 Filter 4 Memory 6 Aspect converter 7 D / A converter 17 Clock generation circuit 18 Judgment circuit

Claims (2)

(57) [Claims] 1. An input video signal of a first system
In a scan converter for changing the number of horizontal scanning lines per frame and outputting as a video signal of the second system, A / D conversion means for A / D converting an input video signal; Storage means for storing A / D-converted video data; and video data read from the storage means,
Operate by a combination of division by multiplication and addition / subtraction,
The number of pixels in a horizontal scan line is the video signal of the second system.
Generating a new pixel with the number of pixels corresponding to the
Scan converter characterized by comprising a stage. 2. One of the input video signals of the first system.
In a scan converter for changing the number of horizontal scanning lines per frame and outputting as a video signal of the second system, A / D conversion means for A / D converting an input video signal; Storage means for storing A / D-converted video data; clock generation means for generating a clock having a predetermined frequency used when A / D-converting the video data by the A / D conversion means; The frequency of the video signal of the first system
And the video signal of the second system
And a frequency setting means for setting the ratio with respect to the number of pixels per line and a reference clock of an input video signal.