JP3162815B2 - Television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver for displaying a squeeze mode output of a MUSE / NTSC down converter on a monitor having an aspect ratio of 4: 3.
In particular, the present invention relates to a television receiver in which a child screen is reduced and combined with a part of a parent screen.

[0002]

2. Description of the Related Art A conventional MUSE / NTSC down converter is disclosed in Japanese Patent Application Laid-Open No. 2-285897 (H04N11 / 20).

This apparatus inputs a 16: 9 aspect ratio Hi-Vision image signal which has been band-compressed by the MUSE method, and outputs it on a 4: 3 aspect ratio display.
6: 9.

However, when such a high-definition image signal is displayed as a sub-screen of a two-screen television receiver which combines and displays a sub-screen in which a reduced image is formed on a part of the main screen, a blanking signal is generated vertically. The added Hi-Vision signal is displayed as a child screen, which has a disadvantage that a part of the parent image is lost as shown in FIG. 8A.

When an image signal input from an external device (for example, a video tape recorder) is an image (squeeze image) obtained by compressing a Hi-Vision signal in the horizontal direction, the image signal is compressed in the horizontal direction as shown in FIG. 8B. There is a disadvantage that the image is displayed on the display as a child screen as it is.

[0006]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks, and an image (squeeze image) obtained by horizontally compressing a video signal having an aspect ratio of 16: 9 and having an aspect ratio of 4: 3. Is input, the sub-screen display is switched to the 16: 9 aspect display as shown in FIG. 8C. When a video signal having an aspect ratio of 4: 3 is input, the sub-screen display is displayed as shown in FIG. 8D. It is an object of the present invention to provide a television receiver capable of displaying an optimum small screen by switching the screen display to the 4: 3 aspect display.

[0007]

SUMMARY OF THE INVENTION According to the present invention, there is provided a television receiver in which a second video signal is reduced and projected in the first video signal. Demodulating means, second demodulating means for demodulating a second video signal, vertical sampling means for sampling the number of scanning lines of the second video signal from the second demodulating means, and a sampling frequency of the vertical sampling means. A switching CPU, a memory for storing a second video signal from the vertical sampling circuit, and a synthesizing unit for synthesizing an output from the first demodulating unit and an output from the memory, and a control signal from the CPU. When a signal obtained by horizontally compressing an image having an aspect ratio of 16: 9 is input as a second video signal, the frequency of the vertical sampling means is set to 1
/ 3 times as well as the normal aspect ratio 4: a television receiver, wherein said that a half times the frequency of the vertical sampling means when the third signal is input.

Further, the present invention provides a television receiver in which a second video signal is reduced and projected in a first video signal, a first demodulation means for demodulating the first video signal, A second demodulator for demodulating the second video signal, a vertical low-pass filter for vertically band-limiting the second video signal from the second demodulator, and a second video signal passing through the vertical low-pass filter. A vertical sampling means for sampling the number of scanning lines, a CPU for switching a sampling frequency of the vertical sampling means and a filter characteristic of a vertical low-pass filter, a memory for storing a second video signal from the vertical sampling circuit, (1) a synthesizing means for synthesizing an output from the demodulating means and an output from the memory, wherein the second video signal is controlled by a control signal from the CPU; Aspect ratio 16 as: 9 image when the input horizontal compressed signal, the frequency of the vertical sampling means with creating a second image signal from the third horizontal successive scan lines by the vertical low-pass filter 1/3 Double the normal aspect ratio of 4: 3
The television receiver is characterized in that, when the signal is input, the vertical low-pass filter is used to create two consecutive horizontal scanning lines and the frequency of the vertical sampling means is reduced by half .

[0009]

According to the present invention, when an image (squeeze image) having an aspect ratio of 4: 3 is input by horizontally compressing a video signal having an aspect ratio of 16: 9, the output from the CPU is set to a low level. As a result, the vertical filter functions as a 3-tap filter, and the sampling frequency of the vertical sampling circuit is reduced to 1/3.
An image having an aspect ratio of 16: 9 is displayed as shown in FIG. On the other hand, when a video signal having an aspect ratio of 4: 3 is input, the output from the CPU is switched to a high level so that the vertical filter functions as a two-tap filter and the sampling frequency of the vertical sampling circuit is 1 /. As a result, an image having an aspect ratio of 4: 3 is displayed on the child screen as shown in FIG. 8D.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a television receiver according to an embodiment of the present invention.

FIG. 1 shows an embodiment of the present invention.

First, an input video signal of a main screen is demodulated by a first demodulation circuit 1, converted into a digital signal by an A / D converter 2, and processed by a video signal processing circuit 3 for digital signal processing on the main screen. (For example, digital Y / C separation processing) is performed. Then, in the scan conversion circuit 4, the number of scan lines is increased from 525 to 735 by multiplying the clock from the clock generation circuit 7 by ／ and input to the synthesis circuit 5.

On the other hand, an input video signal of a small picture is previously supplied to a horizontal low-pass filter (hereinafter abbreviated as horizontal LPF) 1.
The band is limited in the horizontal direction by 1 and is sampled in the A / D converter 12 in the horizontal direction by 1/3 by the clock of the write clock generation circuit 16.

The digital signal from the A / D converter 12 is band-limited in the vertical direction by a vertical low-pass filter (hereinafter abbreviated as vertical LPF) 13. The vertical LPF 13 switches the filter characteristics by switching between a two-tap filter coefficient or a three-tap filter coefficient according to the input signal.

The output from the vertical LPF 13 is input to a vertical sampling circuit 14, and the vertical sampling circuit 14 samples the data in the vertical direction by 1/2 or in the vertical direction by 1/3 according to the input signal. Output to Further, in the memory 15, writing and reading are performed based on the clock from the memory control circuit 9 synchronized with the synchronization signal of the main screen, and the result is output to the synthesizing circuit 5.

The synthesizing circuit 5 outputs a digital signal obtained by synthesizing the above-mentioned parent screen and child screen to the D / A converter 6 and converts the digital signal into an analog signal by the D / A converter 6, and then displays the analog signal. (Not shown) is displayed on two screens. At this time, the number of scanning lines of the main screen is changed from 525 to 735.
The number of sub-screens is 5 /
It is displayed as if it were compressed 7 times. That is, the synthesis circuit 5
Then, a video signal (small screen) having a 4: 3 aspect ratio by horizontally compressing a video signal having an aspect ratio of 16: 9 is
After being sampled 1/3 times horizontally and vertically,
By compressing vertically by a factor of 5/7, a child screen having an aspect ratio of about 16: 9 is obtained. A video signal (small screen) having an aspect ratio of 4: 3 is 1/3 times in the horizontal direction.
After being sampled by a factor of １ ／ in the vertical direction and compressed by a factor of 5/7 in the vertical direction, a child screen having an aspect ratio of about 4: 3 is obtained.

Next, the vertical LPF 13 will be described with reference to FIGS.
The operation of will be described.

FIG. 2 is a block diagram of the vertical LPF 13.
FIG. 3 is a diagram showing a relationship between scanning lines and filter coefficients of the two-tap filter and the three-tap filter. FIG. 4 is a timing chart when the three-tap filter is selected. FIG. 5 is a timing chart when the two-tap filter is selected. Is shown.

In FIG. 2, a vertical LPF 13 is a line memory 30 composed of a first delay line 30a, a second delay line 30b, and a changeover switch 30c.
A first delay circuit 31 for delaying the output from the line memory 30 by one clock, a first multiplication circuit 32 for doubling the input signal, and an output from the first multiplication circuit 32 based on an aspect switching signal from the CPU 17. Controlling AND circuit 33
A first adding circuit 34 for adding the outputs from the line memory 30 and the AND circuit 33; a second multiplying circuit 35 for halving the signal from the first adding circuit 34;
The signal is changed to the second multiplication circuit 3 by the aspect switching signal from
5, a first switch 36 for selecting whether or not to pass through
An inverter 37 for inverting the aspect switching signal from the PU 17; a second delay circuit 38; a third multiplication circuit 39 for halving the signal from the second delay circuit 38;
The third multiplication circuit 3
9, a second switch for selecting whether or not to pass through the second switch, a second addition circuit 41 for adding the outputs of the first switch 36 and the second switch 40, and a second switch for halving the output of the second addition circuit 41. And a 4 multiplication circuit 42.

The line memory 30 is used for the horizontal scanning period 1
This is a ready-made one-chip memory capable of multiplexing and outputting delayed data for one line and two lines in clock units.

Next, the operation of the vertical LPF 13 will be described.

First, a case where a video signal (squeeze image) having an aspect ratio of 4: 3 by horizontally compressing a signal having an aspect ratio of 16: 9 as an input signal is input to an input terminal of a small screen will be described.

In this case, a low-level (hereinafter abbreviated as L) signal is input from the CPU 17 as an aspect switching signal. For this reason, the gate of the AND circuit 33 is open, and the switch 30c is switched up and down based on CLK1. In addition, the first and second
Switches 36 and 40 are switched to the b side.

The input signal j is input to the line memory 30, and the data (B ₀ , B ₁ ,
B ₂ ,...) Are delayed by one line, and the data (A ₀ , A ₁ , A ₂ ,.
Is further delayed by one line, and B ₀ , B ₀ ,
_{A 0, B 1, A 1} , B 2, A 2, and output are multiplexed in the order of ....

Here, C input to the line memory 30
The LK1, WE, reset signal and output signal of the memory have the timing shown in the timing chart of FIG.

Therefore, the output signal k from the line memory 30 is latched by CLK1, and after being delayed by one clock of CLK1 by the first delay circuit 31,
The signal is doubled by the multiplication circuit 32 and is given as the signal l.
Is input to The AND circuit 33 outputs the signal 1 to the first adding circuit 34 because the aspect switching signal is L. The signal k is input to the other input of the first adder circuit 34. Here, since the first switch 36 is switched to the b side by the aspect switching signal,
The output from the adder circuit 34 is divided into 1 /
The signal is multiplied by two and output to the second addition circuit 41 as a signal m.

On the other hand, the input signal j passes through the delay circuit 38, makes the delay amount in-phase with the signal m by CLK2, and is then multiplied by で in the third multiplication circuit 39.
A signal n (current signals C ₀ , C ₁ , C ₂ ,...) Passes through the second side, and this signal n is input to the second addition circuit 41.

Then, the signal m and the signal n are added in the second adder circuit 41, and the signal is further multiplied by に よ り by the fourth multiplier circuit 42, and the signal p (A ₀₎ is output as the output of the vertical LPF 13.
/ 4 + B _0/2 + C _0/4 ,...) Are output to the vertical sampling circuit 14. Here, the filter tap coefficients are the coefficients shown in FIG. 3A.

Next, a case where a video signal having an aspect ratio of 4: 3 is input to an input terminal of a sub-screen as an input signal will be described.

In this case, a high-level (hereinafter abbreviated as H) signal is input from the CPU 17 as an aspect switching signal. Therefore, the gate of the AND circuit 33 is closed, and the changeover switch 30c is fixed to the upper side. The first and second switches are switched to the a side.

The input signal j is input to the line memory 30, and the data (B ₀ , B ₁ ,
B ₂ ,...) Are output after being delayed by one line.

However, as described above, the AND circuit 33
Is closed, the AND circuit 33 outputs the first addition circuit 3
4 is not supplied with output. The signal k is input to the other input of the first adder circuit 34. Here, the first
Since the switch 36 has been switched to the a side by the aspect switching signal, the output from the first addition circuit 34 is the second
The signal is multiplied by に よ り by the multiplication circuit 35 and output to the second addition circuit 41 as a signal m.

On the other hand, the input signal j passes through the second delay circuit 38, makes the delay amount in-phase with the signal m by CLK2, and then outputs the signal n (current signal) via the a side of the second switch 40.
C ₀ , C ₁ , C ₂ ,...), And this signal n is input to the second addition circuit 41.

In the second adder circuit 41, the signal m and the signal n are added, the signal is further multiplied by １ ／ by the fourth multiplier circuit 42, and the signal p (B ₀₎ is output as the output of the vertical LPF 13.
/ 2 + C _0/2 ,...) Are output to the vertical sampling circuit 14. Here, the filter tap coefficients are the coefficients shown in FIG. 3B.

Next, FIG. 6 shows another embodiment of the vertical filter 13.

FIG. 6 differs from FIG. 2 in that the line memory 30 is a ready-made one-chip memory capable of multiplexing and outputting delayed data for one line and two lines in a horizontal scanning period in clock units in FIG. FIG. 6 differs from the embodiment in that two line memories are used.

With this configuration, two independent memories are required, but the first delay circuit 31 can be omitted.

The circuit operation is the same as that of the vertical filter circuit 13 shown in FIG.

Next, the schematic operation of the vertical sampling circuit 14 will be described with reference to FIGS.

FIG. 7A is a block diagram of the vertical sampling circuit 14, and FIG. 7B is a diagram for explaining vertical sampling in the first field and the second field.

The vertical sampling circuit 14 includes a first sampling circuit 20 for sampling one of the input scanning lines, a second sampling circuit 21 for sampling one of the input scanning lines, and an aspect switching signal from the CPU 17. And a switch circuit 22 for switching an output signal in response to the signal.

When a video signal having an aspect ratio of 4: 3 is input to the input terminal of the sub-screen,
The switch 22 is switched upward by the aspect switching signal from U17, and the video signal from the vertical LPF 13 is sampled by the first sampling circuit 20 in the vertical direction as shown in FIG.

When a video signal having an aspect ratio of 4: 3 by horizontally compressing a signal having an aspect ratio of 16: 9 as an input signal is input to an input terminal of a small screen, the CPU
The switch 22 is switched to the lower side by the aspect switching signal from the LCD 17 and the video signal from the vertical LPF 13 is
As shown in FIG. 7B, sampling is performed by the sampling circuit 21 in the vertical direction to 1/3.

[0044]

According to the present invention, when the video signal having the aspect ratio of 4: 3 is input by horizontally compressing the video signal having the aspect ratio of 16: 9 by the above-described configuration, the small picture is displayed. Automatically switches to a display image having an aspect ratio of 16: 9, and the vertical low-pass filter performs optimal filter processing using a 3-tap vertical filter coefficient. Also, when a video signal having an aspect ratio of 4: 3 is input, the child screen automatically changes to an aspect ratio of 4: 3.
, And the vertical low-pass filter performs optimal filter processing using a 2-tap vertical filter coefficient.

[Brief description of the drawings]

FIG. 1 is a diagram showing a television receiver of the present invention.

FIG. 2 is a vertical view used in the television receiver of the present invention .
FIG. 3 is a block diagram illustrating an LPF.

FIG. 3 is a diagram showing filter coefficients of a vertical LPF shown in FIG . 2;
It is.

FIG. 4 shows a vertical LPF shown in FIG . 2 as a 3-tap filter;
6 is a timing chart in the case of using the device.

FIG. 5 shows a vertical LPF shown in FIG . 2 as a two-tap filter;
6 is a timing chart in the case of using the device.

FIG. 6 shows another example used in the television receiver of the present invention .
It is a block diagram of a vertical LPF.

FIG. 7 is a vertical view used in the television receiver of the present invention .
FIG. 3 is a block diagram illustrating a sampling circuit.

FIG. 8 is a diagram illustrating a two-screen display state in the television receiver.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first demodulation circuit 3 video signal processing circuit 4 scan conversion circuit 5 synthesis circuit 10 second demodulation circuit 13 vertical low-pass filter 14 vertical sampling circuit 15 memory 17 CPU

Claims (2)

(57) [Claims] An aspect ratio of 4: 3 and the number of scanning lines is 525.
The first video signal is converted into a video signal having an aspect ratio of 4: 3 and the number of scanning lines is 735.
6: 9 or 4: 3 aspect ratio 4: 3 and 525 scanning lines
In a television receiver adapted to reduce and project a second video signal of a book, a first demodulation means for demodulating a first video signal, a second demodulation means for demodulating a second video signal, Horizontal sampling means for sampling the second video signal from the second demodulation means at a sampling frequency of 1/3 of the sampling frequency of the first video signal; and scanning the second video signal from the horizontal sampling means on a scanning line basis. Vertical sampling means for sampling at the same time, a CPU for switching the sampling frequency of the vertical sampling means, a memory for storing a second video signal from the vertical sampling means, an output from the first demodulation means and a signal from the memory. Combining means for combining outputs,
When a signal obtained by horizontally compressing an image having an aspect ratio of 16: 9 to an aspect ratio of 4: 3 is input as a second video signal according to a control signal from the CPU, the vertical sampling means converts the second horizontal scanning line into three second horizontal scanning lines. One horizontal scan line of the video signal of the normal aspect ratio 4:
A television receiver characterized in that when three signals are inputted, one vertical scanning line of a second video signal is created from two consecutive horizontal scanning lines by the vertical sampling means. 2. The number of scanning lines is 525 with an aspect ratio of 4: 3.
The first video signal is converted into a video signal having an aspect ratio of 4: 3 and the number of scanning lines is 735.
6: 9 or 4: 3 aspect ratio 4: 3 and 525 scanning lines
In a television receiver configured to reduce and project a second video signal of a book, first demodulation means for demodulating a first video signal, second demodulation means for demodulating a second video signal, Horizontal sampling means for sampling the second video signal from the second demodulation means at a sampling frequency of 1/3 of the sampling frequency of the first video signal, and vertically converting the second video signal from the horizontal sampling means. A vertical low-pass filter for band limiting, vertical sampling means for sampling the second video signal from the vertical low-pass filter in units of scanning lines, and a CPU for switching a sampling frequency of the vertical sampling means and a filter characteristic of the vertical low-pass filter. A memory for storing a second video signal from the vertical sampling means; A synthesizing means for synthesizing an output from the output from stage memory, the aspect ratio as the second image signal by the control signal from the CPU 16: 9
When a signal obtained by horizontally compressing an image having an aspect ratio of 4: 3 is input, one horizontal scanning line of a second video signal is created from three consecutive horizontal scanning lines by the vertical low-pass filter and the vertical sampling means. When a signal having a normal aspect ratio of 4: 3 is input, the vertical low-pass filter and the vertical sampling means successively output two signals.
A television receiver for generating one horizontal scanning line of a second video signal from a horizontal scanning line.