JP2896003B2 - Two-screen TV circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-screen television circuit, and more particularly to a high-quality two-screen television circuit in which the number of vertical scanning lines of a main screen is increased by scanning line interpolation.

[0002]

2. Description of the Related Art In a conventional two-screen television circuit 1 shown in FIG.
/ D conversion, and then digital video signal processing (for example, digital Y / C separation processing)
The signal is A-converted and input to the synthesis circuit 2.

On the other hand, after the child screen signal is band-limited in the horizontal direction by the horizontal low-pass filter circuit 3 in advance, for example, when a child screen having an area ratio of 1/9 with respect to the parent screen is created, A
Is sampled in the horizontal direction by the / D converter 4 to 1/3,
Further, after the band is limited in the vertical direction by the vertical low-pass filter circuit 5, 1 /
3 sampled. The vertical sampling circuit 6 performs vertical sampling as shown in FIG. That is, in each of the first field and the second field, the vertical low-pass filter circuit 5 sets three adjacent scanning lines as a set of three scanning lines to form a tap region. And
Sampling is performed with the tap coefficient of the central scanning line of each tap region, that is, the weighting is set to 1/2, the tap coefficients of the scanning lines above and below are set to 1/4, and the position of the central scanning line is set as a sampling point. The child screen data sampled by the vertical sampling circuit 6 is then input to the field memory 7.

[0004] The child screen data input to the field memory 7 is read from the field memory 7 by a read clock synchronized with the parent screen created by the read clock generation circuit 8, D / A converted, and then synthesized. 2
Is input to Then, the main screen signal and the sub-screen signal are synthesized by the synthesizing circuit 2, and a synthesized video signal is output. Note that the timing of writing the sub-screen data to the field memory 7 and reading it from the field memory 7 are as follows.
It is controlled by the memory control circuit 9 in accordance with the respective synchronization signals of the main screen and the sub-screen.

[0005]

However, when the number of vertical scanning lines of the main screen is increased by scanning line interpolation in a two-screen television circuit, the processing of the sub-screen data is not performed by the conventional sub-screen data processing method. Since the conversion of the number of scanning lines of the screen data is not supported, sampling of 1/3 in the vertical direction causes the child screen to be shrunk in the vertical direction to the extent that the number of scanning lines of the child screen is smaller than the parent screen. I will be. Further, the vertical low-pass filter circuit 5 requires a 3-tap filter circuit. Further, when the parent screen and the child screen are combined with an analog signal, a memory read clock generation circuit and a D / A converter dedicated to the child screen data are required.

[0006] Therefore, a main object of the present invention is to provide a two-screen television circuit in which a child screen does not shrink in the vertical direction even when a parent screen has high image quality. Another object of the present invention is to provide a two-screen television which does not require a read clock generation circuit dedicated to a small screen.

[0007]

SUMMARY OF THE INVENTION The present invention provides a two-screen television which compresses a second television screen at a fixed rate into a part of a first television screen serving as a parent screen, and inserts and displays it as a child screen. A clock generating means (22 , 24) for generating a predetermined clock, based on the predetermined clock, the field frequency of the main screen data is constant and the number of vertical scanning lines is set to n / m (n / m> A scanning line converting means (18) for converting 1, 2, and n into positive integers, and converting the child screen to an area ratio of about 1 / x ² (x is a positive integer of 2 or more) of the parent screen. When displaying, the first sampling means (28, 30) for sampling the sub- screen data in the horizontal direction at about 1 / x,
The output of the pulling means is approximately (1 / x) · (n /
m) second sampling means (32, 34) for sampling to 1 / k (k is a positive integer of 2 or more );
Sampling by means and second sampling means
Memory (36) for storing the
To the sub screen data read from the memory and the scanning line conversion means
Therefore, the synthesizing means (2) for synthesizing the converted main screen data
0) is a two-screen television circuit.

[0008]

The main screen signal is converted into a digital signal (main screen data) by an A / D converter, and the scanning line converting means keeps the field frequency constant and the number of vertical scanning lines to n /
Create parent screen data converted to m times. On the other hand, when the child screen is displayed at a size of about 1 / x ^{2 in} area ratio with respect to the parent screen, the child screen signal is horizontally output by about 1 / x by the first sampling means including an A / D converter. Sampling. Then, the data is sampled in the vertical direction by about (1 / x) · (n / m) ≒ 1 / k by the second sampling means and written into the memory. Thus, the first and second
2) Sample screen data is sampled by sampling means
By doing so, the image quality of the child screen is also improved along with the image quality improvement of the parent screen, and the child screen does not shrink in the vertical direction. This
Child screen data read from the memory of
Therefore, the parent screen data converted by the scanning line conversion means
The parent screen and the child screen are combined on the TV screen.
Is displayed.

According to the second aspect of the present invention, when reading the sub-screen data from the memory, a predetermined clock, that is, n is sent to the scanning line conversion means for converting the main screen data into n / m times the number of scanning lines. A clock from a clock generating means for generating a clock of / m times is used. Therefore, a memory read clock generation circuit dedicated to small screen data can be omitted. Further, since the vertical sampling frequency of the small screen data is increased, the number of taps of the vertical low-pass filter circuit at the preceding stage of the second sampling means is reduced.

[0010]

According to the first aspect of the present invention, even when the image quality of the parent screen is improved, the child screen can be prevented from being shrunk in the vertical direction and displayed, and the vertical resolution of the child screen is improved.
According to the second aspect of the present invention, a memory read clock generation circuit dedicated to small-screen data can be omitted, and the number of taps of the vertical low-pass filter circuit for small-screen data can be reduced. A television screen can be obtained with a simple circuit configuration.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0012]

Referring to FIG. 1, a two-screen television circuit 10 of this embodiment includes an input terminal 12 to which a main screen signal is input. The main screen signal input from the input terminal 12 is converted into a digital signal by the A / D converter 14, and the video signal processing circuit 1
6 is input. In the video signal processing circuit 16, the main screen data is processed by digital signal processing (for example, digital Y / Y).
C separation processing, etc.). And the parent screen data is n /
The signal is input to an m-times (here, 7/5 times) scanning line conversion circuit 18 and the number of vertical scanning lines is converted to 7/5 times. That is, in this case, the number of 525 scanning lines is usually 735. Thereafter, the parent screen data is input to the synthesis circuit 20. The clock used for the main screen data processing is generated based on the main screen signal input from the input terminal 12. That is, the main screen signal is output from the clock generation circuit 2
2 and based on the clock generated here, A
The A / D conversion operation in the / D converter 14 and the main screen video signal processing in the video signal processing circuit 16 are performed. And
The output from the clock generation circuit 22 is also input to the 7 / 5-times clock generation circuit 24, where the clock is multiplied by 7/5 and sent to the 7 / 5-times scanning line number conversion circuit 18. The 7 / 5-times scanning line number conversion circuit 18 performs the scanning line number conversion process based on the 7 / 5-times clock.

On the other hand, a small picture signal is inputted from an input terminal 26. After the band is limited in the horizontal direction by the horizontal low-pass filter circuit 28 in advance, the first sampling means
A / D converter 30 that functions as
(Here, 1/3). Then, the small-screen data is band-limited in the vertical direction by the vertical low-pass filter circuit 32, and then the second sampling is performed.
In the vertical sampling circuit 34 functioning as a means, it is sampled in the vertical direction at about (（) ３ (７) ≒ and stored in the field memory 36.

In the vertical 1/2 sampling circuit 34, FIG.
The vertical sampling shown in FIG. That is,
In each of the first field and the second field, the vertical low-pass filter circuit 32
A set of two scanning lines is set as a tap region. Then, the tap coefficient of each of the two scanning lines in each tap region, that is, the weight is set to １ ／, and a scanning line indicated by a mark x in FIG. 2 is created, and is used as a sample point. Accordingly, in this case, since the vertical sampling is の, the vertical low-pass filter circuit 32 may have two taps. That is, only one line memory is required to obtain a delay of one horizontal period, and the number of line memories is smaller than that of the conventional vertical low-pass filter circuit which requires three vertical tap low-pass filter circuits and two line memories. Yes.

A write clock for writing the sub-screen data to the field memory 36 is generated by a write clock generating circuit 38 based on the sub-screen signal from the input terminal 26.
The clock is also supplied to the D converter 30. A clock from the 7 / 5-times clock generation circuit 24 is given as a clock for reading the small screen data from the field memory 36. Then, the small-screen data read from the field memory 36 is input to the synthesizing circuit 20. Writing of the sub-screen data in the memory 36 and the memory 36
The timing of reading from the memory control circuit 40 depends on the synchronization signal between the parent screen signal and the child screen signal.
Controls.

In the synthesizing circuit 20, the master screen data from the 7 / 5-times scanning line converting circuit 18 and the field memory 3 are stored.
6 are combined. Thereafter, the combined two-screen video data is converted into an analog signal by the D / A converter 42 and output from the output terminal 44 as a two-screen video signal. In this way, if the parent screen and the child screen are both digitally synthesized, a conventional D / A converter dedicated to the child screen is not required.

In the above embodiment, n / m = 7 /
5, although the area ratio of the child screen was 1 / x ² = 1/9, the general formula (1 / x) · (n / m) ≒ 1 / k (where x, n, m and k are positive 2 or more) If n / m> 1) is satisfied, the same effect can of course be obtained. 1
In another example where / x is “１ ／”, “１ ／ × 7”
/ 5 = 7/20 ", which is approximated as 1 / k = 1/3.
You. However, these numbers are not
It is appropriately selected in consideration of the rate. For example, scanning the parent screen
When the number of lines is multiplied by n / m, the number of vertical lines
If left untouched, the child screen will shrink vertically by 1 / (n / m) times or more.
Will be reduced. Therefore, in practice, a suitable size
Select the numerical value so that the child screen of
You.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a state of vertical sampling in the embodiment shown in FIG. 1;

FIG. 3 is a block diagram showing a conventional technique.

FIG. 4 is an illustrative view showing a state of vertical sampling in the conventional technique shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... 2 screen television circuit 14, 30 ... A / D converter 18 ... 7/5 times scanning line number conversion circuit 20 ... Synthesizing circuit 24 ... 7/5 times clock generation circuit 32 ... Vertical low-pass filter circuit 34 ... Vertical 1 / 2 sampling circuit 36 ... field memory 42 ... D / A converter

Claims (2)

(57) [Claims] 1. A two-screen television circuit for compressing a second television screen at a fixed rate into a part of a first television screen serving as a main screen and inserting and inserting the same as a child screen, wherein a predetermined clock clock generating means for generating a (22, 24), on the basis of the predetermined clock, and a constant field frequency for the parent screen data vertical scanning line number n / m
(N / m> 1, n and m are positive integers) A scanning line converting means (18) for converting the number of times to a multiple of about 1 / x ² (x is a positive integer of 2 or more ) of the parent screen in area ratio ), The first sampling means (28, 30) for sampling the sub- picture data at about 1 / x in the horizontal direction, and the output of the first sampling means at about ( 1/1 / x ) in the vertical direction.
x) · (n / m) ≒ 1 / k (k is a positive integer of 2 or more), the second sampling means (32, 34), the first sampling means and the second sampling means
Store sub screen data sampled by means
Memory (36), and children read from the memory
Screen data and the parent converted by the scanning line converting means.
A two-screen television circuit comprising a synthesizing means (20) for synthesizing screen data . 2. The memory is read by the predetermined clock.
Was Suyo, 2-screen television circuit as claimed in claim 1, wherein.