JP2907305B2 - Sub screen display circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small-screen display circuit, and more particularly to a circuit for displaying a small-screen by synthesizing a standard television signal for displaying a main screen converted into a line-sequential scanning system.

[0002]

2. Description of the Related Art Conventionally, when a standard television signal for a main screen display converted to a line-sequential scanning system is displayed on a small screen, a standard television signal for a small screen is displayed on a small screen. In both the horizontal direction and the vertical direction, a signal thinned out to about 1/3 is converted at a 6-times speed and output, and combined with a main screen display signal.

[0003]

Accordingly, since the sub-screen signal is created by simply performing the thinning process on the scanning line of the transmitted video signal, the transmitted information is lost. There was a point. The present invention, instead of thinning processing a video signal scan line, by decimating by interpolation of the scanning lines, using all of the scanning lines that have been transmitted, it is possible to create a signal for the child screen display, An object of the present invention is to provide a small-screen display circuit with less information loss.

[0004]

A horizontal processing circuit for thinning out the current standard television signal by about 1/3 in the horizontal direction and outputting the signal;
A vertical processing circuit for thinning out about 1/3 in the vertical direction and outputting the signal, and storing the signal thinned out in about 1/3 in both the horizontal and vertical directions in a memory, and writing from the same memory six times that in writing.
By reading at the clock frequency and converting it to 6 times speed
A circuit for converting to a line-sequential scanning method and outputting the same, and synthesizing the output with a standard television signal for parent screen display converted to a line-sequential scanning method, and a sub-screen display circuit for displaying a sub-screen; The vertical processing circuit skips in each field
525 scanning lines that are not transmitted due to the scanning method are formed from the scanning lines before and after the scanning line and interpolated.
Of the scanning line, consists circuit for outputting a first scanning line of the same 525 lines every three scanning lines, water than the horizontal processing circuit
The signal output by thinning out about 1/3 in the horizontal direction,
Output as a signal thinned down to about 1/3 in the vertical direction,
Number is updated for each field and written to the memory
This is a small screen display circuit. Further, the vertical processing circuit delays the signal input from the horizontal processing circuit by 1H.
And the 1H delay circuit that, Shin was 1H delay at the same 1H delay circuit
An adder for adding said input signal and No., the added
Multiplies the signal from the divider by 1/2 and performs weighted averaging to run for interpolation
A multiplier that forms a scan line and an interpolating scan line from the multiplier
Constituted by a switcher and output sequentially switches the scanning line of the input signal, input from the horizontal processing circuit
Scanning for interpolation of 525 scanning lines from the signal
Forming a line, and a scanning line for the input signal,
525 scanning lines by sequentially switching between the scanning lines
, One scanning line is output every three scanning lines.

[0005]

According to the present invention, the scanning line is reduced by about 1 /
FIG. 2 is an explanatory diagram for explaining the operation of the small-screen display circuit of the present invention. The current standard television signal uses the interlaced scanning method, and FIG. As shown in the column as numbers, the odd fields are
262.5 scanning lines of odd numbers such as 1, 3, 5, 7, 9, 11 are transmitted, and in the even fields, 0, 2, 4,.
Even numbered scan lines 262.5, such as 6, 8, 10
A book has been sent.

If one scanning line is output every three scanning lines in order to reduce the number of scanning lines to about 1/3, as shown in FIG. The odd-numbered scanning lines and the even-numbered scanning lines alternate. Therefore, as shown in the left column of FIG. 2C, in the odd field, the scanning lines such as 1 and 7 are output as they are, and the scanning lines (4, 10, etc.) during which no transmission is made are transmitted. For the preceding and succeeding scanning lines, for example, for 4 scanning lines, weighted averaging of 3 and 5 scanning lines is performed to interpolate and output one scanning line. Similarly, for 10 scanning lines, 9 and 11
Scan lines are weighted and averaged to interpolate and output one scan line.
, A child screen for one screen in the line-sequential system is constructed from the signals of the above. Similarly, in the even field, the scanning lines such as 4 and 10 are output as they are, and the scanning lines (1, 7 and the like) before being transmitted are 0 for the preceding and succeeding scanning lines, for example, one scanning line. And 2 scanning lines are weighted and averaged so that one scanning line is interpolated and output. Similarly, for 7 scanning lines, 6 and 8 scanning lines are weighted and averaged to obtain one scanning line. Is interpolated and output, and a thinning process is performed in order to obtain one screen in the line sequential system from the signal of the even field.
A sub screen is configured. Therefore, the number of scanning lines is reduced to 1/3 by the scanning line interpolation processing, and the generated small-screen display signal uses all the transmitted scanning lines, so that there is little information loss. It becomes possible to display a small screen.

[0007]

FIG. 1 is an electric circuit block diagram of a small screen display circuit showing one embodiment of the present invention. Reference numeral 1 denotes an input terminal to which a current standard television signal is inputted as a small screen display signal. The same input is applied to the horizontal processing circuit 2 via the input terminal 1, and the horizontal processing circuit 2 thins out about 1/3 in the horizontal direction and outputs it. The output from the horizontal processing circuit 2 is branched, the first branch is input to one end of the switch 5, the second is input to the 1H delay circuit 3, the third is input to the adder 4, and the addition is performed. The output from the delay circuit 3 is added to the output from the delay circuit 3 by a multiplier 4, and the output is input to a multiplier 6. The output is halved by the multiplier 6 and input to the other end of the switch 5. And output alternately, so that the standard TV signal 5
For 25 scanning lines, for scanning lines that are not transmitted for each field, the scanning lines are interpolated from the scanning lines before and after the scanning line, and one scanning line is output for every three scanning lines. .

Reference numeral 8 denotes an address control circuit to which a horizontal synchronizing signal, a vertical synchronizing signal, and a clock pulse synchronized with the small-screen display signal are input as input signals. The control signal is applied to the switch 5 and the memory 7 by counting the vertical synchronizing signal, and the output of the switch 5 is written to a predetermined address portion of the memory 7 using the clock pulse. Further, a horizontal synchronizing signal, a vertical synchronizing signal, and a clock pulse synchronized with the main screen display signal are input to the memory 7 as read control signals to the address control circuit 8. FIG. 3 is an explanatory view showing one display example of the child screen with respect to the parent screen. The child screen B is displayed with respect to the parent screen A, and the horizontal synchronization signal and the horizontal synchronizing signal input as the control signal for reading are displayed. By counting the vertical synchronizing signal and reading it out at a predetermined reading position using a clock pulse for reading, a sub-screen can be displayed at a designated position on the main screen.

[0009] The memory 7, one frame signal, horizontal and vertical directions, thinning-out to approximately 1/3, field
It is updated and written every time, and by reading from the same memory 7 using a clock pulse of 3 × 2 = about 6 times faster than the write clock pulse, The screen display signal can be converted to a line-sequential scanning signal reduced to about 1/3 of the original image.
You. Reference numeral 9 denotes an input terminal of a standard television signal for displaying a main screen, which is input to the line-sequential scanning conversion circuit 10 via the input terminal 9, and the inter-line scanning signal is input to the line-sequential scanning conversion circuit 10. Is converted into a signal of the line-sequential scanning system and input to the synthesizing circuit 11, and the synthesizing circuit 11 synthesizes and outputs the sub-screen display signal of the line-sequential scanning system read from the memory 7. The child screen can be displayed on the parent screen based on the output.

[0010]

As described above, according to the present invention,
A sub-screen in which a signal of the current standard system is converted to a line-sequential system can be displayed on a main screen of the current standard system converted to a line-sequential system. Using all the scan lines that have been
The sub-screen display signal is created by thinning out by scanning line interpolation processing, and it is possible to provide a sub-screen display circuit with less information loss, which contributes to improving the performance of the sub-screen display circuit. large.

[Brief description of the drawings]

FIG. 1 is an electric circuit block diagram of a small-screen display circuit, showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating an operation of a small-screen display circuit according to the present invention.

FIG. 3 is an explanatory diagram showing a display example of a child screen with respect to a parent screen.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Horizontal processing circuit 3 Delay circuit 4 Adder 5 Switcher 6 Multiplier 7 Memory 8 Address control circuit 9 Input terminal 10 Line-sequential conversion circuit 11 Synthesis circuit

Claims (2)

(57) [Claims] 1. The current standard television signal is horizontally shifted by about 1 /
A horizontal processing circuit for thinning out the output to 3 and about 1 in the vertical direction
A vertical processing circuit for thinning out to / 3 and outputting the signal, and a signal thinned to about １ ／ in both the horizontal and vertical directions are stored in a memory.
And at a clock frequency six times that of writing from the same memory
Read and convert to 6x speed for line-sequential scanning
A sub-screen display circuit that converts the output to a standard television signal for main screen display converted to a line-sequential scanning method and displays a sub-screen. Scanning lines that are not transmitted due to the interlaced scanning method in each field from the scanning lines before and after the scanning lines.
By forming and interpolating, 525 scanning lines are obtained.
A circuit that outputs 525 scanning lines, one for every three scanning lines , is about one third in the horizontal direction from the horizontal processing circuit.
The signal output after being thinned out is further reduced by about 1 /
Output as a signal thinned to 3 and output the same signal for each field
A small-screen display circuit, wherein the small-screen display circuit is updated and written in the memory . 2. The vertical processing circuit according to claim 2, wherein
And a 1H delay circuit for delaying the input signal by 1H.
The signal delayed by 1H by the 1H delay circuit and the input signal
And an adder for adding the signal
Multiplier for multiplying by weighting and forming a scanning line for interpolation
And the interpolation scanning line from the multiplier and the input signal
It consists of a switching unit that sequentially switches and outputs the scanning lines
And, from the signal input from the horizontal processing circuit, 525
A scanning line for interpolation for forming a single scanning line is formed, and
The scanning line of the input signal and the interpolation scanning line
In other words, from 525 scanning lines to 1 every 3 scanning lines
2. A scanning line is output.
The described small screen display circuit.