JPH05137085A - Slave screen display circuit - Google Patents

Abstract

PURPOSE:To generate a slave screen signal using all the scanning lines and to reduce the omission of information by converting the scanning line of a reference television(TV) signal into a line sequential signal by thinning by applying interpolation processing. CONSTITUTION:The reference TV signal is added on a horizontal processing circuit 2 as a signal for slave screen display. The circuit 2 issues output by thinning to nearly 1/3 in the horizontal direction, and directly inputs it to one terminal of a switch 5, and also, inputs it to another terminal of the switch 5 after adding the output of a 1H delay circuit 3 and thinning to 1/2 by a multiplier 6. The switch 5 outputs both input alternately, and interpolates the scanning line from the scanning lines before and behind the scanning line of the reference TV signal, and outputs one scanning line at every three scanning lines. The output of the switch 5 is written on the prescribed address of memory 7 by thinning to nearly 1/3 in both horizontal and vertical directions. The output is read out by using a clock pulse at speed of around three times the one for write and is compressed to a slave screen, and is synthesized with the reference TV signal for master screen display at a synthesis circuit 11 via a line sequential scan conversion circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a child screen display circuit, and more particularly to a circuit for combining a standard television signal for parent screen display converted into a line-sequential scanning system to display a child screen.

[0002]

2. Description of the Related Art Conventionally, when displaying a standard TV signal on a standard TV signal for main screen display converted into a line-sequential scanning system as a sub-screen, a standard TV signal for sub-screen display is In each of the horizontal and vertical directions, a signal decimated to about ⅓ is converted at 6 times speed and output, and is combined with the main screen display signal.

[0003]

Therefore, since the scan line of the transmitted video signal is simply thinned to create the sub-screen signal, the transmitted information is lost. There was a point. According to the present invention, instead of thinning out the video signal scanning lines, the scanning lines are thinned out by interpolation processing, and all the transmitted scanning lines can be used to create the child screen display signal. It is an object of the present invention to provide a small screen display circuit capable of causing little information loss.

[0004]

FIG. 1 is an electric circuit block diagram of a small screen display circuit showing an embodiment of the present invention. As shown in FIG. A horizontal processing circuit 2 that thins out to 1/3 and outputs, and a vertical processing circuit that thins out to about 1/3 in the vertical direction and outputs (see FIG.
, The delay circuit 3, the adder 4, the switcher 5,
It is composed of a multiplier 6) and a circuit (memory 7 in FIG. 1) for converting the signal thinned out to about 1/3 in both the horizontal and vertical directions and outputting the converted signal at 6 times speed. In the sub-screen display circuit for synthesizing into the standard TV signal for main screen display converted into the sub-screen and displaying the sub-screen, the vertical processing circuit for each field for 525 scanning lines of the standard TV signal For scan lines that have not been transmitted, scan lines are interpolated from scan lines before and after the scan line, and 3
One scanning line is output for each scanning line, and the scanning lines are thinned out to about 1/3.

[0005]

According to the present invention, with the above-mentioned configuration, the scanning line is reduced to about 1 /
2 is an explanatory diagram for explaining the operation of the child screen display circuit of the present invention, in which the current standard television signal uses the interlaced scanning method, and the left side of FIG. The odd fields, as indicated by the numbers in the columns,
262.5 of the odd-numbered scan lines are sent such as 1, 3, 5, 7, 9, and 11, and 0, 2, 4 ,, as shown in the right column of the even field by numbers.
Even numbered scan lines 262.5
Books are being sent.

If one scan line is output for every three scan lines in order to thin out the scan lines to about ⅓, odd numbers such as 1, 4, 7, and 10 are output as shown in FIG. Scan lines and even-numbered scan lines alternate. Therefore, (C)
As shown in the left column of the figure as numbers, the scan lines such as 1 and 7 are output as they are in the odd field, and the scan lines (4, 10, etc.) while they are not transmitted are the scan lines before and after, for example, For the 4 scan lines, the 3 and 5 scan lines are weighted averaged to interpolate and output one scan line. Similarly, for the 10 scan lines, the 9 and 11 scan lines are output. The scanning lines are weighted and averaged so that one scanning line is interpolated and output, and the thinning process is sequentially performed to form an odd field screen. Similarly, in even fields, scan lines such as 4 and 10 are output as they are, and the scan lines (1, 7, etc.) that are not transmitted are 0 for the preceding and following scan lines, for example, the scan line of 1. And scan lines 2 and 2 are weighted average to interpolate and output one scan line. Similarly, for scan line 7, scan lines 6 and 8 are weighted average to obtain one scan line. Are interpolated and output, and thinning processing is sequentially performed to form an even field screen.
Therefore, the number of scanning lines is thinned out to 1/3 by the interpolation processing of the scanning lines, and the created child screen display signal uses all the transmitted scanning lines, so that there is little loss of information. It is possible to display a sub screen.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an electric circuit block diagram of a child screen display circuit showing an embodiment of the present invention. Reference numeral 1 is an input terminal to which a current standard television signal is inputted as a child screen display signal. , The same input is applied to the horizontal processing circuit 2 via the input terminal 1, and the horizontal processing circuit 2 thins out approximately 1/3 in the horizontal direction and outputs. The output from the horizontal processing circuit 2 is branched, the first branched is input to one end of the switching device 5, the second is input to the 1H delay circuit 3, and the third is input to the adder 4 for addition. The adder 4 adds the output from the delay circuit 3 and inputs the output to the multiplier 6. The multiplier 6 halves the input to the other end of the switch 5, and the switch 5 inputs both inputs. Of the standard TV signal by switching
With respect to the 25 scanning lines, for the scanning lines that are not transmitted for each field, the scanning lines are interpolated from the scanning lines before and after the scanning lines, and one scanning line is output for every 3 scanning lines. .

Reference numeral 8 denotes an address control circuit, which receives as input signals a horizontal synchronizing signal, a vertical synchronizing signal and a clock pulse which are synchronized with the child screen display signal. A vertical synchronizing signal is counted and a control signal is applied to the switch 5 and the memory 7, and the output of the switch 5 is written in a predetermined address portion of the memory 7 by using the clock pulse. Further, the address control circuit 8 is supplied with a horizontal synchronizing signal, a vertical synchronizing signal and a clock pulse, which are synchronized with the parent screen display signal, to the memory 7 as read control signals. FIG. 3 is an explanatory diagram showing a display example of the child screen with respect to the parent screen, in which the child screen B is displayed with respect to the parent screen A, and the horizontal synchronization signal and the horizontal synchronization signal input as the control signal for reading. The vertical synchronizing signal is counted and read at a predetermined reading position using a clock pulse for reading, so that the child screen can be displayed at the designated position of the parent screen.

The write signal for the memory 7 is thinned out to about 1/3 in both the horizontal and vertical directions, and about 3 in both the horizontal and vertical directions with respect to the write clock pulse. By using a clock pulse of double speed, the sub-picture display signal is reduced to about 1/3 of the original picture, and the interlace scanning method signal is converted to the line-sequential scanning method signal. For conversion, the speed of the read clock pulse with respect to the write clock pulse is set to 6 times. 9
Is the standard TV signal input terminal for the main screen display,
It is input to the line-sequential scanning conversion circuit 10 through the same input terminal 9, and the line-sequential scanning conversion circuit 10 converts the interlaced scanning system signal into a line-sequential scanning system signal and inputs it to the synthesizing circuit 11. Therefore, in the synthesizing circuit 11, the child screen display signals read from the memory 7 are combined and output, and the child screen can be displayed on the parent screen based on the output.

[0010]

As described above, according to the present invention,
The main screen of the current standard method converted to the line-sequential method can display the child screen of the signal of the current standard method converted to the line-sequential method, and instead of simply thinning out the scanning lines of the video signal, transmission Using all the scan lines that have been
The sub-screen display signal is created by thinning out by the interpolation processing of the scanning lines, and it is possible to provide a sub-screen display circuit with less information loss, which contributes to improving the performance of the sub-screen display circuit. large.

[Brief description of drawings]

FIG. 1 is an electric circuit block diagram of a child screen display circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating an operation of a child screen display circuit of the present invention.

FIG. 3 is an explanatory diagram showing a display example of a child screen with respect to a parent screen.

[Explanation of symbols]

 1 Input Terminal 2 Horizontal Processing Circuit 3 Delay Circuit 4 Adder 5 Switcher 6 Multiplier 7 Memory 8 Address Control Circuit 9 Input Terminal 10 Line Sequential System Conversion Circuit 11 Compositing Circuit

Claims (2)

[Claims] 1. A current standard television signal is approximately 1 / horizontal.
Horizontal processing circuit that thins out to 3 and outputs, and about 1 in the vertical direction
It is composed of a vertical processing circuit for thinning out to / 3 and outputting, and a circuit for converting the signals thinned out to about ⅓ both in the horizontal and vertical directions to output at 6 times speed, and the same output is converted into a line sequential scanning system. Combined with the standard TV signal for main screen display,
In a small screen display circuit for displaying a small screen, the vertical processing circuit responds to 525 scanning lines of a standard television signal,
For a scan line that is not transmitted in each field, a scan line is interpolated from scan lines before and after the scan line, and a circuit that outputs one scan line for every three scan lines is provided. Display circuit. 2. The vertical processing circuit branches an input circuit, inputs the branched first into one end of a switching device, inputs the second into a 1H delay circuit, and inputs the third into an adder. , Add to the output from the delay circuit by the adder and input to the multiplier, halve by the multiplier and input to the other end of the switch, and switch and output the input of the switch. The child screen display circuit according to claim 1, wherein