JPH06276462A - Plasma display device - Google Patents

Abstract

PURPOSE:To input a converted video signal different from a display picture element number, a scanning line number and a scanning frequency for each scanning line to the plasma display device. CONSTITUTION:The plasma display device 21 in which display picture element number, a scanning line number and a scanning frequency for each scanning line are set to prescribed values is provided with a vertical filter circuit 7 converting the scanning line number of a video signal input different from display picture element number, a scanning line number and a scanning frequency for each scanning line to provide an output, a field memory 8 writing/ reading an output from the vertical filter circuit 7 to provide an output, a horizontal filter circuit 9 converting the picture element number for each scanning line of the signal read from the field memory 8, and a line memory 10 writing/reading the signal from the horizontal filter circuit 9 to provide an output, then the video signal input with a different system is converted and the converted signal is inputted to the plasma display device 21, on which the picture is displayed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal input circuit for a plasma display display device.

[0002]

2. Description of the Related Art In a conventional plasma display device, since a video signal is driven by a digital signal, the number of display pixels for each scanning line, the number of scanning lines and the scanning frequency are set to predetermined values in advance. Has been done.

[0003]

Therefore, the standard video signals that can be input are limited, and a video signal input conversion circuit has been required in order to be able to input video signals of different systems. It is an object of the present invention to convert a video signal having a different number of display pixels, a different number of scanning lines and a different scanning frequency for each scanning line so that it can be input to a plasma display device.

[0004]

As shown in FIG. 1, a plasma display device 2 in which the number of display pixels for each scanning line, the number of scanning lines, and the scanning frequency are set to predetermined values in advance.
1, a vertical filter circuit 7 that converts and outputs the number of display pixels for each scanning line, the number of scanning lines, and the number of scanning lines of a video signal input having different scanning frequencies, and the output from the vertical filter circuit 7 is written, read, and output. Field memory 8
And a horizontal filter circuit 9 for converting the number of pixels of each scanning line of the signal read from the field memory 8 and outputting the converted signal, and a line memory 10 for writing and reading the signal from the horizontal filter circuit 9 for output. Different video signal inputs are converted and input to the plasma display device 21 for image display.

[0005]

According to the present invention, the plasma display device 2 having the above-mentioned structure is used to convert the video signal input of different system.
1, the vertical filter circuit 7 converts the number of scanning lines of the video signal input, the horizontal filter circuit 9 converts the number of pixels for each scanning line, and the field memory 8 displays the plasma display device. Since the scanning frequency is converted by reading out at the vertical frequency set to 21 and reading out at the horizontal frequency set to the plasma display display device 21 with respect to the line memory 10, the plasma display display device 21 is converted. It becomes possible to input and display an image.

[0006]

FIG. 1 is a block diagram of an electric circuit of a plasma display device showing an embodiment of the present invention. A standard signal set in the plasma display device 21 and a video signal B having a different number of pixels for each scanning line, scanning line number and scanning frequency are input to an input terminal 6, and a horizontal synchronizing signal (H1) of the video signal B is input. It is input to the input terminal 1 and the vertical synchronizing signal (V1) is input to the input terminal 2. Reference numeral 7 denotes a vertical filter circuit which converts the number of horizontal scanning lines of the video signal B input through the input terminal 6 and outputs the converted signal to the field memory 8. The field memory 8 writes, reads, and outputs the input. , To the horizontal filter circuit 9. The horizontal filter circuit 9 converts the number of pixels for each scanning line of the signal read from the field memory 8 and outputs the converted signal to the line memory 10. The line memory 10 writes, reads, and outputs the same input to the switch 11. is doing. The switching device 11 includes the plasma display device 2
The standard video signal A set to 1 is input through the input terminal 12, and by switching the switch 11, the signal input to the plasma display display device 21 can be selected.

The horizontal synchronizing signal (H1) inputted via the input terminal 1 is branched and one of them is inputted to the phase synchronizing circuit 3,
The other is input to the phase synchronization circuit 5, and in the phase synchronization circuit 3, the phase of the clock signal (f1) is synchronized with the input horizontal synchronization signal (H1) and output, and the vertical filter circuit 7 and the horizontal filter circuit 9 are output. To the clock signal (f1) necessary for digital signal processing. The vertical synchronizing signal (V1) inputted via the input terminal 2 is inputted to the phase synchronizing circuit 4, and the synchronizing signal generating section 1 of the plasma display device 21 inputted by the same phase synchronizing circuit 4
Taking the least common multiple with the vertical sync signal of frequency f3 from 5, outputting the signal of frequency f2, writing the data in the field memory 8 with the signal of the same frequency f2, and reading it as the vertical sync signal of frequency f3. Thus, the vertical frequency set in the plasma display device 21 is converted. In the phase synchronization circuit 5, the input horizontal synchronization signal (H1) and the same phase synchronization circuit 5
The horizontal common sync signal of the frequency f5 from the sync signal generator 15 of the plasma display device 21 input to is taken as the least common multiple, and the signal of the frequency f4 is output, and the data of the same frequency f4 is stored in the line memory 10. Writing is performed and reading is performed with a horizontal synchronizing signal having a frequency f5, so that the horizontal frequency is set to the plasma display display device 21.

The vertical synchronizing signal of the video signal A is input terminal 13
The horizontal sync signal is input to the input terminal 14, and the sync signal generator 15 generates a vertical sync signal and a horizontal sync signal in synchronization with the sync signals input from the input terminals 13 and 14, and outputs the vertical sync signal. The phase synchronization circuit 4 and the field memory 8 are input, the horizontal synchronization signal is input to the phase synchronization circuit 5 and the line memory 10, and the vertical synchronization signal and the horizontal synchronization signal are input to the data control unit 16. The input signal from the switching device 11 is input to the data control unit 16, and the vertical and horizontal synchronizing signals from the synchronizing signal generating unit 15 are detected, and an address signal is output and input to the memory control unit 17 for switching. The input signal from the device 11 is output in dot units and input to the memory 19. As the memory 19, for example, a frame memory using a D-RAM is used, and a signal input in dot units from the data control unit 16 is written in a predetermined position according to an address input via the memory control unit 17. There is.

The memory control unit 17 inputs a read signal to the memory 19 at a predetermined timing after writing one frame of the image signal to the memory 19 and reads and outputs the image signal written to the memory 19. It is input to the driver control unit 18. Driver controller 18
Repeatedly reads an image signal from the memory 19 at a predetermined timing and inputs the image signal to the plasma display panel 20, and based on the address signal input from the memory control unit 17, the driver control unit 18 causes the scan data signal and the driving pulse to be output. To the plasma display panel 20, an image signal is input to a predetermined address portion of the plasma display panel 20, electric charges are accumulated at the same address portion, and the drive pulse is arranged in an XY matrix. To discharge an electric discharge cell provided at the address portion to display an image.

FIG. 2 is an electric circuit block diagram showing an embodiment of the vertical filter circuit 7 and the horizontal filter circuit 9 of FIG. 1, in which the same components as those shown in FIG. 1 are designated by the same symbols. It shows with. In the vertical filter circuit 7, the video signal B is branched and the first signal is input to one end of the switch 28, the second signal is input to the multiplier 23, and the third signal is input to the line memory 22. It is multiplied by a predetermined coefficient set in the register 24, input to the adder 27, the horizontal scanning line is delayed by 1H in the line memory 22 and output, and input to the multiplier 25. The multiplier 25 sets it in the register 26 in advance. It is multiplied by the determined predetermined coefficient and input to the adder 27. In the adder 27, the inputs from the multipliers 23 and 25 are added and input to the other end of the switching device 28, and the switching device 28 alternately switches and outputs the video signal B and the input from the adding device 28. In this way, the scanning lines are interpolated so that the number of scanning lines of the video signal B is doubled and output, and the result is input to the field memory 8.

In the horizontal filter circuit 9, the pixel data of the horizontal scanning line is read from the field memory 8 and branched, the first is input to one end of the switch 35, and the second is the multiplier 3.
2 and the third is input to the latch circuit 29. The multiplier 32 multiplies a predetermined coefficient set in the register 33 in advance, inputs the result to the adder 34, the latch circuit 29 delays the pixel data of the horizontal scanning line by one pixel, and outputs the delayed pixel data to the multiplier 30. In the multiplier 30, a predetermined coefficient preset in the register 31 is multiplied and the result is input to the adder 34. In the adder 34, the inputs from the multipliers 30 and 32 are added and input to the other end of the switch 35, and the switch 35 alternately switches the input signal and the input from the adder 34 to output. Then, the pixels are interpolated to double the number of pixels for each scanning line and output, and the result is input to the line memory 10.

Therefore, it becomes possible to convert the scanning line number of the video signal input, the number of pixels for each scanning line, and the scanning frequency for the video signal input of different systems.
It becomes possible to input to the plasma display display device 21 and display an image. The vertical filter circuit 7 interpolates the scanning lines to convert the number of scanning lines into two and output it. However, the interpolation is performed according to the difference between the standard setting signal and the video signal input of a different system. The number of scanning lines to be processed and converted may be changed, or the number of scanning lines may be thinned to match the number of scanning lines of a standard setting signal and a video signal of a different system. Similarly, in the horizontal filter circuit 7, pixels are interpolated to double the number of pixels for each scanning line and output. However, there is a difference between a standard setting signal and a video signal input of a different method. Accordingly, the number of pixels for each scanning line to be converted by interpolation processing may be changed,
Alternatively, the number of pixels may be thinned out so that the number of pixels of a video signal of a different system from that of the standard setting signal is matched.

[0013]

As described above, according to the present invention,
For a video signal input of a system different from the standard video signal set in the plasma display display device, the number of scanning lines, the number of pixels per scanning line, and the scanning frequency set in the plasma display display device should be matched. Since the conversion is performed, it is possible to display an image on the plasma display display device, and it is possible to provide a plasma display display device with improved versatility.

[Brief description of drawings]

FIG. 1 is a block diagram of an electric circuit of a plasma display device according to an embodiment of the present invention.

FIG. 2 is an electric circuit block diagram showing one embodiment of the vertical filter circuit 7 and the horizontal filter circuit 9 of FIG.

[Explanation of symbols]

 1 input terminal 2 input terminal 3 phase synchronization circuit 4 phase synchronization circuit 5 phase synchronization circuit 6 input terminal 7 vertical filter circuit 8 field memory 9 horizontal filter circuit 10 line memory 11 switcher 12 input terminal 13 input terminal 14 input terminal 15 synchronization signal Generation unit 16 Data control unit 17 Control unit 18 Driver control unit 19 Memory 20 Plasma display panel 21 Plasma display display device 22 Line memory 23 Multiplier 24 Register 25 Multiplier 26 Register 27 Adder 28 Switcher 29 Latch circuit 30 Multiplier 31 Register 32 Multiplier 33 Register 34 Adder 35 Switch

Claims (4)

[Claims] 1. A plasma display device in which the number of display pixels for each scanning line, the number of scanning lines, and the scanning frequency are set to predetermined values in advance. The vertical filter circuit that converts and outputs the number of scanning lines of different video signal inputs, the field memory that writes and reads the output from the same vertical filter circuit, and the number of pixels per line of the signal read from the same field memory A horizontal filter circuit for converting and outputting and a first line memory for writing and reading a signal from the horizontal filter circuit and outputting the same are provided, and a video signal input of a different system is converted and input to a plasma display display device. A plasma display device characterized by displaying an image. 2. The frequency of writing to the field memory is a common multiple of the vertical frequency of the plasma display device and the vertical frequency of the video signal input,
The reading is the vertical frequency of the plasma display display device, the writing frequency to the first line memory is the common multiple of the horizontal frequency of the plasma display display device and the horizontal frequency of the video signal input, and the reading is the plasma display display device. 2. The plasma display device according to claim 1, wherein the scanning frequency is converted as the horizontal frequency of the. 3. A circuit for inputting the video signal input into three branches by the vertical filter circuit, the circuit being input to one end of the first switching device, the first multiplier, and the second line memory, and the first multiplier. A circuit for multiplying by a predetermined coefficient and inputting to the first adder, and a horizontal scanning line for inputting a video signal in the second line memory are
A circuit for delaying and outputting, multiplying with a predetermined coefficient by a second multiplier and inputting to the first adder, and a circuit for adding the inputs from the first and second multipliers by the first adder A circuit for inputting to the other end of the first switch, the video signal input and the first
The first output for alternately switching the inputs from the adder
The plasma display device according to claim 1, comprising a switch. 4. The horizontal filter circuit branches the signal input into three and inputs the signal to one end of the second switching device, the third multiplier and the latch circuit, and a predetermined coefficient in the third multiplier. And a circuit for multiplying and inputting the result to the second adder and the latch circuit delaying the pixel of the horizontal scanning line of the video signal input by one pixel and outputting the delayed signal, and multiplying by a predetermined coefficient by the fourth multiplier. A circuit for inputting to the adder and the second and third adders add the third and fourth
The circuit includes a circuit for adding the inputs from the multipliers and inputting it to the other end of the second switching unit, and the second switching unit for alternately switching between the signal input and the input from the second adding unit and outputting it. The plasma display device according to claim 1.