JP3356183B2 - Scan converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan converter suitable for converting non-interlaced video data output from, for example, a personal computer to interlaced NTSC video data.

[0002]

2. Description of the Related Art A video signal output from a personal computer is of a non-interlaced type, and its horizontal scanning frequency and vertical scanning frequency are different from those of a normal NTSC video signal, for example. Therefore, for example, computer graphics (CG)
When combining image data designed in a device with an image captured by a normal video camera or the like, CG
It is necessary to convert the image obtained in the system into NTSC video data.

[0003]

However, the conventional scan converter has a problem that an image becomes unclear due to system conversion.

The present invention has been made in view of such circumstances, and aims to obtain a clear image.

[0005]

A scan converter according to the present invention comprises a filter 4 as suppression means for applying a coefficient to at least three lines of non-interlaced continuous video data to perform processing for flicker suppression; 4 as a converting means for converting the video data processed in step 4 into interlaced video data, and an emphasizing means for emphasizing the outline of the video data converted into the interlaced type by the memory 10. Used for vertical emphasis circuit 13 and memory 10
Timing as a means for generating a timing signal
Generator 17 and non-interlaced video
Judge the cycle of the data line and respond to the judgment result
Determining means for controlling the timing generator 17
And a determination circuit 31 as described above.

[0006]

[0007]

[0008]

In the scan converter having the above-described structure, the processing for suppressing flicker is performed by the filter 4, and then the non-interlaced video data is converted into the interlaced video data in the memory 10. Thereafter, a process of enhancing the contour is performed by the vertical enhancement circuit 13. Therefore, with a simple configuration, flicker can be suppressed and a clear image can be obtained.

When the filter 4 processes at least three lines of data, flicker can be suppressed more effectively.

Further, when the timing generator 17 is controlled in accordance with the line cycle of the non-interlaced video data, the timing generator 17 is automatically controlled regardless of the type of the input non-interlaced video data. In addition, non-interlaced video data can be converted to interlaced video data.

[0011]

FIG. 1 is a block diagram showing the configuration of an embodiment of a scan converter according to the present invention. R, G, and B analog video signals output from the personal computer 1 are supplied to an encoder 2 and converted into a luminance signal Y and a chroma signal C. The luminance signal Y is input to the A / D converter 3, A / D converted, and then supplied to the filter 4. The filter 4 performs a process for suppressing flicker on the input video data.

The data output from the filter 4 is supplied to an adder 7, where the black level line output from the black signal generating circuit 8 is added as required. That is, this ensures the necessary number of lines as the number of lines for one field of the NTSC system. The data output from the adder 7 is supplied to a memory 10 via a switch 9 which is switched upward or downward in the figure every 1H. The memory 10 includes memories 10A and 10B. The memory 10A stores video data of odd fields, and the memory 10B stores video data of even fields.

The video data read from the memory 10A or 10B is supplied to a vertical emphasizing circuit 13 via a switch 12 which is switched upward or downward in the figure for each field. The vertical emphasis circuit 13 performs a process of emphasizing the outline of the input data. The video data output from the vertical emphasis circuit 13 is supplied to a D / A converter 14.
After the D / A conversion, the data is output to a circuit (not shown).

On the other hand, a synchronization signal output from the personal computer 1 is input to a synchronization separation circuit 15, where a horizontal synchronization signal and a vertical synchronization signal are separated. Sync separation circuit 1
The horizontal synchronization signal (H) separated by 5 is supplied to the PLL circuit 16 and the determination circuit 31. PLL circuit 16
Generates a clock synchronized with the input horizontal synchronization signal and outputs the clock to the timing generator 17. The timing generator 17 generates various timing signals in synchronization with the clock supplied from the PLL circuit 16. In the timing signals, the memories 10A, 10A
A write clock supplied to B is also included.

The memory 32 stores the frequency (cycle) of the horizontal synchronizing signal output from various personal computers. For example, PC98, MACII, IBMPC
(Trademark) horizontal scanning frequency of 24.826 kHz
z, 35 kHz or 31.469 kHz is stored. The determination circuit 31 compares the data stored in the memory 32 with the data supplied from the synchronization separation circuit 15 and, in accordance with the determination result, determines whether the timing generator 1
7 is controlled.

On the other hand, the phase comparator 18
5 compares the phase of the vertical synchronizing signal (V) output by the D / A converter 14 with the phase of the vertical synchronizing signal included in the video signal output by the D / A converter 14, and determines that the phase error is a predetermined value (eg,
H) When it becomes equal to or more than the above, a control signal is output to the write / read control circuit 19. At this time, the write / read control circuit 19 controls so that the read operation of the memories 10A and 10B does not overtake the write operation.

On the other hand, an oscillator (VXO) 21 performs an oscillating operation and generates a clock having a constant frequency. The synchronization generation circuit 22 generates various synchronization signals synchronized with the clock, and the timing generator 23 generates various timing signals synchronized with the synchronization signal generated by the synchronization generation circuit 22. In this timing signal, the memory 1
The read clock supplied to 0A and 10B is included.

Next, the operation will be described. The analog R, G, B signals output from the personal computer 1 are supplied to the encoder 2 and converted into a luminance signal Y. The luminance signal Y is A / D converted by the A / D converter 3 and supplied to the filter 4. This filter 4
For example, it is configured as shown in FIG.

That is, the input data is supplied to a multiplier 43, multiplied by a coefficient of 0.25, and supplied to an adder 46. After the input data is delayed by 1H by the 1H delay circuit 41, the input data is multiplied by a coefficient 0.5 by the multiplier 44 and supplied to the adder 46. Furthermore, 1H delay circuit 4
After the data delayed by 1 is further delayed by 1H by the 1H delay circuit 42, the coefficient of 0.25
Are supplied to the adder 46. The adder 46
The outputs of the multipliers 43 to 45 are added and output.

That is, as shown in FIG. 3, of the three continuous lines, the first line is weighted by 0.25, the middle line is weighted by 0.5,
The last line is weighted by 0.25, and they are added to form one line. If there is a sudden change between successive lines, flicker will be noticeable. Thus, by calculating three lines in this way to generate a new line, a rapid change between lines is suppressed, and as a result, the occurrence of flicker is suppressed. .

The data output from the filter 4 is supplied to an adder 7, where a black level line is added as necessary. That is, as shown in FIG. 4, for example, pixels (a) in the horizontal direction and the vertical direction of the effective screen of the personal computer are displayed.
× b) is, for example, 640 × 400, M
ACII and IBMPC are 640 × 480. On the other hand, when video data for one frame of the NTSC system is sampled at a frequency of _4fsc ( _fsc is the frequency of the color subcarrier), 760x480
It becomes a pixel. For example, when input is video data of 400 lines, video data for one frame is short of 80 (= 480−400). Therefore, the missing lines are added above and below the 400 lines in the adder 7, respectively. When the number of lines of the video signal of the input personal computer is 480, the number of lines is the same as that in the NTSC system, so that it is not necessary to add a new line in the adder 7.

The video data output from the adder 7 is
The data is supplied to the memory 10A or 10B via the switch 9 and is written. At this time, a necessary write clock is generated by the timing generator 17. The switch 9 is alternately switched to the memory 10A or 10B every 1H. As a result, the data of the odd field of 240 lines is stored in the memory 10A,
In B, data of an even field of 240 lines is written.

The data written in the memories 10A and 10B in this manner is read out in synchronization with a read clock output from the timing generator 23. The write and read operations for the memories 10A and 10B will be further described with reference to FIGS.

Now, for example, the frame frequency of the video data output from the personal computer 1 is 55.4.
Hz, the field frequency of the NTSC system is 59.94 Hz. Therefore, as shown in FIG. 5, a time corresponding to one frame period of the personal computer 1 is applied to the memories 10A and 10B for one frame. When data is read with the period corresponding to the field of the NTSC system as a cycle while writing the data, the read operation is faster than the write operation, so that the read operation overtakes the write operation at a predetermined time as shown in FIG. . For example, as shown in FIG. 5, in the period T ₁ writes one frame of data, it is assumed that read data of one field with a period T _2. Even initiated delayed by time T ₀ from the operation of the write operation of the read, one day will be the operation of reading overtakes the operation of writing.

Therefore, in the present embodiment, the phase comparator 1
In step 8, when the phase difference between the vertical scanning cycle of the personal computer 1 and the two fields (one frame) of the NTSC system output from the D / A converter 14 is detected, and the phase difference becomes, for example, 3H or more. And the read / write control circuit 19 to control reading from the memories 10A and 10B. That is, as shown in FIG. 6, when the read operation is about to overtake the write operation, the same memory is repeatedly read before the read operation is performed, thereby prohibiting the read operation from overtaking the write operation.

The data read from the memory 10A or 10B via the switch 12 is supplied to a vertical emphasizing circuit 13, where a process for emphasizing the outline component is executed. That is, as shown in FIG. 7, data (A) to (C) are generated in which the input data is sequentially delayed by a predetermined clock. Then, a signal obtained by subtracting the signal shown in FIG. 7A from the signal shown in FIG. 7B and a signal obtained by subtracting the signal shown in FIG. 7C from the signal shown in FIG. , A signal of a contour component as shown in FIG. By adding this signal to the signal shown in FIG. 7B, a video signal in which the outline component shown in FIG. 7E is emphasized can be obtained.

As described above, when the processing for removing the flicker component by the filter 4 is performed, the processing is performed between adjacent lines, so that the resolution is reduced. Thus, the vertical emphasis circuit 13 emphasizes the contour components so that a clearer image can be obtained.

The video data output from the vertical emphasizing circuit 13 is D / A converted by the D / A converter 14 and output to a circuit (not shown) for display.

FIG. 8 shows a second embodiment of the filter 4. In this embodiment, the data output from the A / D converter 3 is supplied to a multiplier 63, and a coefficient of 0.2
After being multiplied by 5, it is supplied to an adder 71,
The multipliers 66 and 67 multiply the coefficients by 0.25 or 0.5, respectively, and output the result to the adder 70. The data output from the A / D converter 3 is delayed by 1H by the 1H delay circuit 62 and then supplied to the multiplier 64, 65 or 68, where the coefficient is 0.25, 0.5 or 0.25, respectively. Is multiplied.

The outputs of the multipliers 64 and 65 are supplied to an adder 69 and added. The output of the multiplier 68 is supplied to an adder 72 and added to the output of the adder 70. . The adder 71 adds the output of the multiplier 63 and the output of the adder 69. The controller 73 controls the multipliers 63 to 68 to be enabled at a predetermined timing (every 2H).

In this embodiment, the adder 7
Since data for two lines (data for odd lines and data for even lines) are simultaneously generated by 1 and 72, the adder 7 shown in FIG. 1 is divided into adders 7A and 7B. The black level lines output from the black signal generation circuit 8 are added to the outputs of the adders 71 and 72, respectively, and output to the memory 10A or 10B.

Next, the operation will be described. In this embodiment, the input data is delayed by 1H by the 1H delay circuit 62.
When the +1 line is being input, the 1H delay circuit 62 outputs the nth line 1H before. Therefore, the output of the multiplier 63 is set to 0.
The weighted data is 25. The multiplier 64
And 65 are data obtained by weighting the n lines by 0.25 and 0.5. The adder 69 includes a multiplier 64
And 65 outputs are added, the output is obtained by adding 0.75 weight to the data of n lines. The adder 71 combines the data obtained by adding the weight of 0.75 to the n lines and the line obtained by adding the weight of 0.25 to the n + 1 line in order to add the output of the multiplier 63 and the output of the adder 69. Line (in FIG. 9, a line indicated by a broken line)
Output data.

On the other hand, the multipliers 66 and 67 output data obtained by weighting 0.25 and 0.5 on the (n + 1) th line, respectively, and this output is added by the adder 70.
The data output from the adder 70 is 0.75 on the (n + 1) th line.
Is weighted data. On the other hand, the output of the multiplier 68 is data in which n lines are weighted by 0.25. Since the adder 72 adds the output of the adder 70 and the output of the multiplier 68, the output data of the adder 72 is added to the data of the n-th line as shown by a dashed line in FIG.
This is data obtained by combining data weighted by 25 and data weighted by 0.75 on the (n + 1) th line. As a result, as shown in FIG. 9, the data output from the adder 71 and the adder 72 is about 0.5H.
The data is weighted so as to have an interval of (= 0.75 to 0.25).

That is, as shown in FIG. 10, when the data of each line is inputted from the A / D converter 3 as 1, 2, 3, 4, 5,..., The 1H delay circuit 62 Data 1
Output with H delay. As a result, the adders 71 and 72
At the timing when the data of the even line is input to the filter 4, the data of the odd line and the data of the even line are simultaneously output.

The data of the odd lines and the data of the even lines are written into the memory 10A or 10B after a predetermined number of black level lines are added by the adders 7A and 7B, respectively. Thus, as in the case described above, the number of lines written to the memory 10A or 10B is reduced to に. As a result, data of the number of lines (240 lines) for one field is written in the memory 10A or 10B.

FIG. 11 schematically shows how lines are generated in the embodiment of FIG.

FIG. 12 shows a third embodiment of the filter 4. In this embodiment, the data output from the A / D converter 3 is supplied to the contact a of the switch 84 and is also input to the 1H delay circuit 82 to be delayed by 1H. The output of the 1H delay circuit 82 is supplied to multipliers 85 and 86 and also to a 1H delay circuit 83. The multipliers 85 and 86 multiply input data by a coefficient of 0.25 or 0.5, respectively, and output the result to the adder 88. Adder 88
Add the outputs of the multipliers 85 and 86 and output the result to the adder 89.

Incidentally, the coefficients of the multipliers 85 and 87 and the multiplier 86 can be set to, for example, 0.125 and 0.75, respectively. These values are preferably digitally processed in the form of 2 ⁿ .

The 1H delay circuit 83 supplies the input data to the contact point b of the switch 84 with a delay of 1H. The data output from the switch 84 is output to the multiplier 87
Is multiplied by a coefficient of 0.25 and supplied to the adder 89. The adder 89 adds the data supplied from the adder 88 and the data supplied from the multiplier 87 and outputs the result to the adder 7 (FIG. 1).

In this embodiment, when data of each line of 1, 2, 3, 4,... Is input from the A / D converter 3, the 1H delay circuit 82 converts the data of each line to 1
The output is sequentially delayed by H, and the 1H delay circuit 83 delays the output of the 1H delay circuit 82 further by 1H and outputs it (FIG. 13). That is, when the 1H delay circuit 82 outputs the data of the first line, the data of the second line is input as the input data. At this time, the switch 84
Is switched to the contact a side. As a result, the multiplier 87
Weights the data of the second line by 0.25 and outputs the result to the adder 89.

The multipliers 85 and 86 weight the data of the first line by 0.25 and 0.5, respectively, and output the result. The adder 88 adds the outputs of the multipliers 85 and 86, and the output is added to the data of the first line by 0.7.
5 is obtained. As a result, the output of the adder 89 is obtained by combining the data obtained by weighting the data of the first line with 0.75 and the data obtained by weighting the data of the second line with 0.25.

When the time of 1H further elapses, the 1H delay circuit 82 outputs the data of the second line, and the 1H delay circuit 83 outputs the data of the first line. At this time, the switch 84 is switched to the contact b side. As a result, the multiplier 87 outputs the first signal supplied from the 1H delay circuit 83.
The data of the line is weighted by 0.25 and output. The adder 88 weights the data of the second line output from the 1H delay circuit 82 by 0.75 and outputs the data. As a result, the adder 89 combines the data obtained by weighting the data of the first line with 0.25 and the data obtained by weighting the data of the second line with 0.75, and generates a new line data. Generate data.

In the same manner, the switch 84 is switched to the contact a side or the contact b side every 1 H, and the adder 8
9 outputs data of one line in 1H. This data is stored in the memory 10A or 10B as described above.
Are written alternately as odd-line data or even-line data.

FIG. 14 schematically shows a process of generating data between the respective lines in this case.

The embodiment of FIG. 12 performs substantially the same operation as the embodiment of FIG. However, FIG.
Since the number of adders can be reduced as compared with the embodiment, more accurate calculation can be executed.

In the above, the case where the PC 98 is used as the personal computer 1 has been described as an example.
Alternatively, when IBM PC is used, the memory 10
The frequency of the clock supplied to A and 10B and the timing of writing and reading are different. Therefore, in the present embodiment, the determination circuit 31 uses the horizontal synchronization signal supplied from the synchronization separation circuit 15 to determine what is connected as the personal computer 1 in the memory 32.
Is determined from the data stored in advance.

That is, the determination circuit 31 compares the frequency (period) of the horizontal synchronization signal stored in the memory 32 in advance with the frequency (period) of the horizontal synchronization signal separated by the synchronization separation circuit 15, and The type of the personal computer 1 is determined from the comparison result. Then, the timing of the timing generator 17 is switched according to the determined result. Thus, the correct conversion process can always be automatically performed regardless of the type of the personal computer 1.

[0048]

As described above, according to the scan converter of the present invention, the processing for suppressing flicker is performed, and then the processing for enhancing the contour is performed. It is possible to reproduce a clear image while suppressing flicker.

Further, when a process for suppressing flicker is performed using data of at least three lines, the occurrence of flicker can be suppressed more effectively.

Further, when the timing signal is controlled according to the line cycle of the non-interlaced video data, the conversion operation is automatically realized regardless of the type of the non-interlaced video data. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a scan converter according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of a filter 4 of FIG.

FIG. 3 is a diagram illustrating a weighting process of the embodiment in FIG. 2;

FIG. 4 is a diagram illustrating the operation of the adder 7 of FIG.

FIG. 5 is a timing chart illustrating the operation of the memories 10A and 10B in FIG. 1;

FIG. 6 is a timing chart illustrating the operation of the memories 10A and 10B of FIG. 1;

FIG. 7 is a waveform diagram illustrating an operation of the vertical emphasis circuit 13 of FIG.

FIG. 8 is a block diagram showing a configuration of a second embodiment of the filter 4 of FIG. 1;

FIG. 9 is a diagram illustrating a weighting process in the embodiment of FIG. 8;

FIG. 10 is a diagram illustrating the output of each unit in the embodiment of FIG.

FIG. 11 is a diagram illustrating a weighting process in the embodiment of FIG. 8;

FIG. 12 is a block diagram showing a configuration of a third embodiment of the filter 4 of FIG. 1;

13 is a diagram illustrating the output of each unit in the embodiment of FIG.

FIG. 14 is a diagram illustrating a weighting process in the embodiment of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Personal computer 2 Encoder 4 Filter 7 Adder 10A, 10B memory 13 Vertical emphasis circuit 15 Synchronization separation circuit 17 Timing generator 18 Phase comparator 23 Timing generator 31 Judgment circuit 32 Memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/00-9/78 H04N 11/00-11/22

Claims (1)

(57) [Claims] 1. A suppression means for applying a coefficient to at least three lines of non-interlaced continuous video data to perform processing for flicker suppression, and converting the video data processed by the suppression means into an interlaced video signal. conversion means for converting the video data, and enhancement means for performing a process for emphasizing the outline for the converted video data into interlaced by the converting means, generating a hand for generating a timing signal to be used for the conversion unit
And the circumference of the line of the non-interlaced video data.
Period, and controls the generation means in accordance with the result of the determination.
A scan converter, comprising: a determination unit for controlling the scan converter.