KR920007917B1 - Progressive scanning circuit - Google Patents

Abstract

The circuit converts the interlace scan signal into the sequential scan signal by estimating the scan multiplication data of the Y/C signals according to the detected momentum. The circuit comprises two delay means for delaying the Y/C signals of the interlace scan signal for a predetermined time, means (30) for detecting and interpolating the momentum of the Y signal, means (40,70) for reproducing the interpolating signal by interpolating the delayed Y and C signals, and means for producing the scan multiplication signal by using the interpolated Y/C signals and the delayed Y/C signals.

Description

Sequential Scanning Signal Regeneration Circuit

1 is a circuit diagram of the present invention.

2 is a detailed circuit diagram of a first interpolation signal regenerator 40 of FIG.

3 is a detailed circuit diagram of a second interpolation signal regenerator 70 of FIG.

4 is a detailed circuit diagram of the first double scanning signal regenerator 60 of FIG.

5 is a detailed circuit diagram of the second double scanning signal regenerator 90 of FIG.

6 is a sample view seen from the vertical and time side of the NTSC signal according to the present invention;

* Explanation of symbols for main parts of the drawings

10, 20: first, second delay unit 30: motion signal detection and correction

40, 70: First and second interpolation signal regenerators 50, 80: Third and fourth paper research

60, 90: first and second scan signal regenerators

The present invention relates to a television (Television), and in particular, the interlaced scanning signal is estimated by estimating the scanning information of luminance (hereinafter referred to as Y) signal and chromaticity (hereinafter referred to as C) signal according to the detected amount of motion. The present invention relates to a circuit for converting a sequential scan signal.

In general, NTSC signals currently being broadcast are in the form of 2: 1 interlaced scan of 525 lines. In the 2: 1 non-circular scanning, there is a problem in that a flicker phenomenon is given to the eyes at a frequency of 30 Hz per frame. The frickering phenomenon is that the eyes do not feel when the 80HZ due to the characteristics of the eyes. Accordingly, an object of the present invention is to provide a sequential scan signal generation circuit capable of sequential scanning by estimating the scan information of the C signal of Y according to the amount of motion detected by a television.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a circuit diagram of the present invention, wherein the first delay unit 10 delays the luminance signal of the interlaced scan signal, the second delay unit 20 delays the chroma signal of the interlaced scan signal, and the change in the luminance signal. A motion signal detecting and correcting device 30 for detecting and correcting an exercise amount and outputting a motion signal M, and connected to the motion signal detecting and correcting device 30 and according to the motion signal M. A first interpolation signal regenerator 40 for generating an interpolation signal for luminance by interpolating the luminance signal through the unit 10 and an output signal of the first delay unit 10 by 1H and outputting a YD signal; The first delayed scanning signal regenerator (3) and the first multiplied scanning signal regenerator (100) configured to receive an output signal of the first interpolation signal regenerator (40) and an output signal of the third delay unit (50) to be sequentially scanned signals for sequentially scanning ( 60), the second signal is connected to the motion signal detection and corrector 30 and according to the motion signal M. The second interpolation signal regenerator 70 generates an interpolation signal for chromaticity by interpolating the chroma signal through the edge portion 20, and outputs a CD signal by delaying the output signal of the second delay unit 20 by 1H. A second double scan signal regenerator configured to receive a fourth delay unit 80, an output signal of the second interpolation signal regenerator 70, and an output signal of the fourth delay unit 80 to produce a scanning scan signal for sequentially scanning; 90).

2 is a detailed circuit diagram of the first interpolation signal regenerator 40, in which the luminance signal, that is, the Y signal, is not transmitted through the first delay unit 41 and the first delay unit 41. In FIG. A first adder 42 for adding up the signals, an amplifier 43 for amplifying the output signal of the first adder 42, a second delay unit 44 for delaying the input Y signal by 263H, A subtractor 45 for subtracting the output signal of the amplifier 43 and the output signal of the second delay unit 44, a multiplier 46 for multiplying the output signal of the subtractor 45 and the motion signal M; And a second adder 47 for outputting the interpolated luminance signal, that is, the YP signal, by adding the output signal of the multiplier 46 and the output signal of the second delay unit 44.

FIG. 3 is a detailed circuit diagram of the second interpolation signal regenerator 70 in FIG. 1, wherein an input chromaticity signal, that is, a C signal is a signal through the first delay unit 71 and a signal not through the first delay unit 71. A first adder (72) for summation, an amplifier (73) for amplifying the output signal of the first adder (72), a second delay unit (74) for delaying the input C signal by 263H, and A subtractor 75 for subtracting the output signal of the amplifier 73 and the output signal of the second delay unit 74, a multiplier 76 for multiplying the output signal of the subtractor 75 and the motion signal M, and And a second adder 77 for outputting the interpolated color signal, i.e., the CPU signal, by adding the output signal of the multiplier 76 and the output signal of the second delay unit 74.

FIG. 4 is a detailed circuit diagram of the first scanning signal signaling machine 60 of FIG. 1, and illustrates input signals of the first-4 1H memories 61-64 and the first and second 1H memories 61,62. The first switch SW1 to select, the second switch SW2 to select the input signals of the third and fourth 1H memories 63 and 64, and the outputs of the first to fourth 1H memories 61-64. It consists of a third switch (SW3) for selecting.

FIG. 5 is a detailed circuit diagram of the second double scanning signal regenerator 90 of FIG. 1 to select input signals of the 5-8 1H memory 91-94 and the 5,6 1H memory 91,92. The fifth switch SW5 to be input, the sixth switch SW6 to select input signals of the seventh and eighth 1H memories 93 and 94, and the outputs of the fifth to eighth 1H memories 91 and 94. The seventh switch SW7 is selected.

6 is a sample view of the NTSC signal processed according to the present invention in the vertical and time axis.

Based on the above configuration, the present invention will be described in detail with reference to FIGS. 1-5.

First, as shown in FIG. 1, the Y signal, which is an input luminance signal, is output with a predetermined delay through the first delay unit 10. The delay time is obtained by passing the Y signal through the motion signal detection and corrector 30. Delay by the time it takes to output the exercise signal (M). The first delay unit 10 may be implemented as a memory device. The output signal of the first delay unit 10 is input to the third delay unit 50 and the first interpolation signal regenerator 40, and the third delay unit 50 is connected to the first interpolation signal regenerator 40. The HD signal is output to the output terminal after delaying the interpolation signal YP by 1H.

Meanwhile, as shown in FIG. 2, the first interpolation signal regenerator 40 adds the Y-delayed Y signal and the non-delayed Y signal by the first adder 42 through the first delay unit 41. The amplifier 43 is applied to the amplifier 43, and the amplifier 43 outputs a half amplified output to which the first adder 42 is added. In other words, this means that the output of the first adder 42 is attenuated in half.

As shown in FIG. 6, the amplified signal is equal to 1/2 of the signal of point A plus the signal of point B. FIG.

이다.In other words

to be.

On the other hand, if the Y signal is delayed 263H through the second delay unit 44, it can be seen that the point C of FIG.

신호는 감산기(45)에서 감산되고, 이 감산된 신호와 운동신호 감지 및 보정기(30)를 통해 얻어지는 운동신호(M)는 곱셈기(46)에 의해 곱셈된다. 상기 곱셈된 신호는 상기 제2지연부(44)의 출력신호와 제2가산기(47)에서 합하여지고, 이에따라 보간 휘도신호 즉, YP신호가 출력되어진다. 상기 동작을 수식으로 나타내면 상기 감산기(45)의 입력신호를 α라 하고, 제2지연부(44)의 출력신호를 β할 경우 상기 YP신호는 하기(1)식과 같다.The signal at point C and the

The signal is subtracted by the subtractor 45, and the subtracted signal and the motion signal M obtained through the motion signal sensing and corrector 30 are multiplied by the multiplier 46. The multiplied signal is summed by the output signal of the second delay unit 44 and the second adder 47, thereby outputting an interpolation luminance signal, that is, an YP signal. When the operation is expressed by a formula, the input signal of the subtractor 45 is α, and when the output signal of the second delay unit 44 is β, the YP signal is expressed by Equation 1 below.

신호가 출력하게 되는데 이 동작을 수식으로 표현하면 하기 (2)식과 같다.That is, the components of α and β are distributed to the YP signal according to the exercise signal M. When the exercise signal M becomes larger, the components of α are included, and the components of β are increased when the components of α are increased. If there is no motion, β signal or β = C signal is output.

When the signal is output, this operation is expressed by the following formula (2).

The YD signal output from the third delay unit 50 of FIG. 1 and the YP signal output from the first interpolation signal regenerator 40 are applied to the first double scan signal regenerator 60. The first double scan Signal regenerator 60 is shown in FIG. As shown in FIG. 4, the first switch SW1 toggles the YD signal at an fn period. First, the first 1H memory 61 writes the YD signal, and then the second 1H memory 62 writes the YD signal. Similarly, the YP signal is also written to the third 1H memory 63 first through the second switch SW2 and then to the fourth 1H memory 64. At this time, the speed of the write of the memory is 4fsc = 4 × 3.18MHZ. Data of the first-4H 1H memory 61-64 outputs the Y1 signal through the third switch SW3, and the read order of the first-4H memory 61-64 is 1H memory. (61), the third 1H memory 63, the second 1H memory 62, and the fourth 1H memory 64, and the third switch SW3 switches to a 2fn rate. The speed at which each data is read is 8 fsc. The order in which the YD and YP signals output the Y1 signal is as follows.

First, when the information YD (1) signal of the first line of the YD signal is inputted, it is written to the first 1H memory 61, and at the same time, the information YP (1) of the first line of the YP signal is also written to the third 1H memory 63. do. After 1H, the second line information YD (2) of the YD signal is input to the second 1H memory 62, and the second line information YP (2) of the YP signal is input to the fourth 1H memory 64. At the same time, the data of the first and third 1H memories 61 and 63 output the Y1 signal through the third switch SW3 continuously (sequentially). When the information YD (3) of the third line is input, when the information YD (3) of the third line is input again to the first 1H memory 61, it is written back to the third 1H memory 63, and at the same time, the second, 4 1H memory (62, 64) data is sequentially output the Y1 signal through the third switch (SW3). The processing continues in this way, Y1 and Y1 than the input speed of the YP signal The output of the signal is double the data output. To do this, fn is the selection frequency of the first and second switches SW1 and SW2, the write clock of each 1H memory is 4fsc, the switch frequency of the third switch SW3 is 2fn, and the read clock of each 1H memory. 8 fsc.

The interlaced data is sequentially scanned by the operation of the first double scan signal regenerator 60 as described above.

Meanwhile, the process of outputting the C1 signal, which is the sequential scanning signal for the chroma signal in FIG. 1, is also the same as the process of outputting the Y1 signal, that is, the second and fourth delay units 20 and 80 and the second interpolation signal regenerator. 70 and the second scan signal regenerator 90 correspond to the first and third delay units 10 and 50, the first interpolation signal regenerator 40 and the first scan signal regenerator 60, respectively. The circuit configuration and operation shown in FIG. 3, which is a detailed circuit diagram of the interpolation signal regenerator 70, are the same as the circuit configuration and operation shown in FIG. 2, which is a detailed circuit diagram of the first interpolation signal regenerator 40, The circuit configuration and operation shown in FIG. 5, which is a detailed circuit diagram of the double scan signal regenerator 90, are the same as the circuit configuration and operation shown in FIG. 4, which is a detailed circuit diagram of the first scan signal regenerator 60. Omit.

As described above, the present invention eliminates the defect of interlaced scanning and determines the vertical resolution by changing the NTSC signal that is currently being broadcast, that is, the 525 line 2: 1 interlaced scanning to the 525 line 1: 1 sequential scanning. ) Increases the vertical resolution by increasing from 0.7 to 0.9. In addition, the NTSC signal was interlaced with the 525 line 2: 1, but the frequency per frame was 30Hz, which gave a fricker to the human eye, but the present invention improved this. That is, the flicker phenomenon is reversed by performing 1: 1 sequential scanning, and the line crawl phenomenon generated by the interline scan is also eliminated. As described above, the present invention senses the amount of motion for accurate data correction and actively reproduces the progressive scan interpolation signal based on the amount of motion, thereby faithfully reproducing the effect and improving the image quality.

Claims (3)

A television apparatus for converting an interlaced scan signal into a sequential scan signal, comprising: first delay means for delaying the luminance and color signals of the interlaced scan signal for a predetermined time, and detecting and correcting an amount of motion in response to a change in the luminance signal; The brightness and chromaticity of the motion signal detector and corrector 30 for outputting a motion signal and the first delay means and the motion signal detector and corrector 30 are delayed and output from the first delay means according to the motion signal. Interpolation signal reproducing means for generating interpolation signals by interpolating signals, second delay means connected to said first delay means for delaying said luminance and chroma signals, respectively, for a predetermined time, and said second delay means and said interpolation means. Connected to a signal reproducing means for inputting the interpolated luminance and chroma signals and the delayed luminance and chroma signals to sequentially scan signals Progressive signal reproduction circuit, characterized in that the ship consists of a lifting scan signal reproducing means. 2. The sequential scan signal reproducing circuit according to claim 1, wherein the first delay means are each constituted by a memory element, and the luminance and chroma signals are delayed by the time required to output the motion signal (M). 2. The sequential scanning according to claim 1, wherein the second delay means are respectively constituted by memory elements and delay the luminance and chromaticity signals of the first delay means by more than 1 H than the interpolation signals output from the interpolation signal reproducing means. Signal reproduction circuit.

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