JPS59153379A - Digital profile compensating circuit - Google Patents

Abstract

PURPOSE:To eliminate deterioration such as false profile or residual image or the like by supervising the strength of correlation between fields of a digital TV signal so as to decrease a value of constant multiplied with a vertical edge signal when the correlation between fields is weak. CONSTITUTION:A digital TV signal (a) applied to an input terminal 1 becomes a TV signal a' with one field delay by a field memory 20, and the signal a' becomes a TV signal a'' by being delayed for one field by a field memory 35. A frame difference signal (h) being subtraction 36 between the signals (a) and a'' is inputted to a vertical constant generator 37, which generates a constant n(h) being a small value when the signal (h) is increased, and the constant value is multiplied 23 with the vertical edge signal (d) from a vertical profile extracting circuit 21. The result of multiplication and a specific picture element K of the present field are added 33, and the result is added 15 with a horizontal profile compensating signal obtained from the horizontal profile extracting circuit 2, a horizontal constant generator 13 and a multiplier 14 to output a digital profile compensating signal (g).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to Previsionllll! This invention relates to a digital contour compensation circuit that digitizes a television signal and emphasizes the contours of a preview image in order to improve the sharpness of II images.

Conventional Structure and Other Points Generally speaking, the resolution of a picture tube deteriorates as the frequency of the video signal increases. Therefore, especially the outline of the image becomes unclear. Therefore, in order to improve this, a digital contour compensation circuit is used. In this way, by digitizing a television signal and performing contour compensation, for example, S/N+linearity is improved compared to an analog system.

Next, a conventional example of a digital contour compensation circuit will be explained. FIG. 1 is a block diagram showing the configuration of a horizontal digital contour compensation circuit. In FIG. 1, for example, a black and white television signal (hereinafter referred to as a TV signal) is
A digital TV signal a encoded with 8 bits per sample is applied to input terminal 1. The horizontal contour extraction circuit 2 extracts the horizontal edge component of the digital TV signal a and sends it out as a horizontal edge signal. The horizontal contour extraction circuit 2 is composed of an acyclic digital filter as shown in the figure. 3.4.5 and 6 are 8-bit registers, which collectively constitute a shift register, and sequentially shift the digital TV signal a applied from the upper side every clock. Furthermore, numerals 7, 8 and 9 are adders, and numeral 11 is a subtracter. Multiplier] 0 performs a 1-bit carry down in order to multiply by a coefficient. The multiplier 12 performs a 1-bit carry in order to multiply by a coefficient of 2.

For example, if the sample points of the TV signal are taken as shown in FIG. 2, the pixel X of the th line. The horizontal edge signal of is expressed as follows.

b=2x --・(x -1-x +x -1-x
) (1) 022-112 In FIG. 1, the horizontal constant generator 13 generates a constant m that determines the amplitude of the overshoot added in the horizontal direction.

Multiplier 14 multiplies the horizontal edge signal by a constant m and sends the result to adder 15 . Adder 15 outputs this multiplication result and pixel X. and the value of C to obtain an output signal C that has been subjected to contour compensation.

For example, when a step wave whose level changes from O to A as shown in FIG. 3(a) is applied to the input terminal 1 as the digital TV signal a, the edge signal level becomes as shown in FIG. 3(b). The output signal C obtained by adding the digital TV signal a and the edge signal S and compensating the contour becomes as shown in FIG.

Vertical contour compensation is similar to horizontal contour compensation. In other words, as shown in Figure 2, the sample points arranged in the vertical direction "j-21Y-1+X□ +y□, y
2 may be used. In FIG. 2, the sampling frequency is an integer multiple of the horizontal frequency fH, but if it is not an integer multiple, the sample points will not line up vertically, so a method such as interpolation from previous and subsequent sample points is used.

Furthermore, there are two methods of taking sample points in the vertical direction: a method of processing within a field, and a method of processing between fields. In contour compensation, if the enhancement ranges in the horizontal and vertical directions are not aligned, the screen will look unnatural. Therefore, in order to maintain a balance with the sample point interval in the horizontal direction, inter-field processing in which the vertical sample point interval is halved is better.

FIG. 4 is a block diagram showing the configuration of an interfield digital contour compensation circuit that performs contour compensation in the vertical and horizontal directions. In FIG. 4, a digital TV signal a is applied to input terminal 1. The field memo IJ 20 sends out a digital TV signal a' which is delayed by one field from the digital TV signal a. For example, as shown in FIG. 2, if the fcth line is -2, K, K+2 lines f, % field, the iil:, -1°K+1th line is the line of the previous field. Vertical contour extraction circuit 21i
Next, the vertical edge component of the digital TV signal a is extracted and sent as a vertical edge signal d. The vertical contour extraction circuit 21 is basically composed of the same acyclic digital filter as the horizontal contour extraction circuit 2 shown in FIG. However, in FIG. 1, the shift register 3 is delayed by 1 sample, and the soft register 22 is delayed by 4.5'elH period.
．． 23.24.

Further, the adders 25, 26, 27, the subtracter 292, and the multiplier 28.30 are respectively the adders 7.8 in FIG.
．． 9, subtractor 111 corresponds to multiplier 10.12. Taking the sample points shown in FIG. 2 as an example, first is pixel X of the line. The vertical edge signal d is expressed by the following equation.

d-2x□-■・< y-2+y l+y1+y2)
--- (2) In Figure 4, the constant n that determines the amplitude of the overshoot added in the vertical direction by the vertical constant generator 31
occurs. The multiplier 32 has a vertical edge signal d and a constant n.
, and sends the result to the adder 33. Adder 3
3 adds this multiplication result to the value of the pixel XO to perform contour compensation in the vertical direction.

The contour compensation in the horizontal direction is exactly the same as that explained using FIG. 1, so a detailed explanation will be omitted.

As described above, the output signal f subjected to contour compensation in the horizontal and vertical directions is expressed by the following equation based on equations (1) and (2).

f=(1+2m+2n)・x.

-f fist (x 2 + x 1 + Xl +
) Inter-field digital contour compensation has a large effect when the inter-field correlation is strong, but when the inter-field correlation is weak, for example when the contour part moves between fields, false contours occur and the image quality deteriorates significantly. do. −
As an example, as shown in Figure 5, the upper part is white (level 150) and the lower part is black (level 50), with the 1st line as the border.
Consider the screen. In this case, the digital TV signal aσ)
The table shows the brightness level of each line and the brightness level of the output signal f when contour compensation shown in equation (3) is performed (valid only in the vertical direction).

(Left below) When the input image is stationary as shown in Fig. 5, the first . -1 field and L-th field are repeated, and the output signal f also becomes L-th field.
By repeating 1 field and 2gL field, the vertical contour is effectively emphasized.

However, as shown in the table, when the boundary moves three lines from top to bottom for each field, the output signal f changes from the L+1th field to the L+3th field. In this case, the first line at the boundary between each field is emphasized 15 times as much as when it is stationary. In addition, considering the visual characteristics and the afterimage characteristics of the picture tube, the display screen is considered in one frame, and the change in brightness level oscillates, for example, from the 11th line to the +8th line in the L+1 field and L+2 field. ing. Therefore, on the display screen, false contours and afterimages such as ringing appear after the moving boundary, which deteriorates the image quality.

1, at a movement speed of about 3 lines in 1 field, u
This is a slow change that takes 5 seconds or more to move from the top to the bottom of the fii surface, and the visual characteristics do not deteriorate, so the above-mentioned deterioration is also very noticeable.

OBJECTS OF THE INVENTION An object of the present invention is to provide a digital contour compensation circuit that uses inter-field digital contour compensation for contour compensation in the vertical direction and can reduce deterioration that occurs when inter-field correlation is weak.

Structure of the Invention The digital contour compensation circuit of the present invention constantly monitors the strength of the inter-field correlation, and if the field memory is weak, it reduces the value of the constant n multiplied by the vertical edge signal d to eliminate the cause of deterioration. Reduces the emphasis of the contours.

In this case, the strength of the field correlation is determined by comparing the level with the sample point of Mf1 in one frame, and based on the difference.

As described above, by controlling the value of the constant n, it is possible to perform inter-field contour compensation without causing deterioration such as false contours or afterimages.

Description of examples Hereinafter, embodiments of the present invention will be described in detail with reference to figures.

FIG. 6 is a block diagram showing the configuration of an embodiment of the digital contour compensation circuit according to the present invention. In Figure 6,
The fc digital TV signal a is delayed by one field by the field memory 20 to become the digital TV signal a', and further delayed by the field memory 35 to become the digital TV signal a''.Digital TV signal a"ke digital T
This is a signal one frame before the V signal a. The subtractor 36 is
Sample point X on digital TV signal a. and sample point X one frame before. ' is subtracted (xO-xO') and a frame difference signal is sent out. The vertical constant generator 37 is set by the value of the frame difference signal t] and the constant n (
This is a ROM that generates h). Vertical contour extraction circuit 21° multiplier 32. Adder 33. Horizontal contour extraction circuit 2° multiplier 14. The adder 15 and the horizontal constant generator 13 are the same as those shown in FIG. 4, and their operations are also the same, so a detailed explanation will be omitted. In this embodiment, the output signal g subjected to contour compensation f-+ in both the horizontal and vertical directions is expressed by the following equation.

g2(1+2m+2n(h)) ・X(+−EPσ・(
Y-2 + Y-0 y + y, ) ... (4) No. 4
), the value of n (h) is controlled by the value of the frame difference signal, and is set so that as the value of h increases, the value of n (h) decreases.

FIG. 7 is a block diagram showing the configuration of a second embodiment of the digital contour compensation circuit according to the present invention. In FIG. 7, the same blocks as in FIG. 6 are indicated by the same numbers. Blocks that are not necessary for detailed explanations will be omitted. In FIG. 7, a comparator 38 compares the value of the frame difference signal, which is the output of the subtracter 36, with a preset value, and when the value of the frame difference signal is larger, the control signal i is output. Send. When the switch 39 receives the control signal i, it opens the circuit, interrupts the sending of data to the adder 33, and
Cancel vertical contour compensation.

FIG. 8 is a block diagram showing the configuration of a third embodiment of the digital contour compensation circuit according to the present invention. In FIG. 8, the same blocks as in FIG. 6 are indicated by the same numbers. Omit blocks that are not required for the cut iron gate. In FIG. 8, the digital TV signal a' delayed by one field by the field memory 20 is input to the IH shift register 40.
Then, the signals of the Kth line and the Kth line shown in FIG. 2 are obtained. Further, the digital TV signal a is delayed by the IH shift register 41 and becomes a line signal as shown in FIG. Adder 42nd digit K +
The signal of the first line and the signal of the 11th line are added 31', and the multiplier 13 multiplies the coefficient T by 1.
After all the bits are downgraded, the average value of the +1 line and the 11th line is calculated. The subtracter 44 first calculates the difference between the line signal and the above average value, and sends it out as a field difference signal j. At this time, the field difference signal jt'' is expressed by the following equation.

J − Operation C1 is similar to FIG. 7.

The IH shift registers 40 and 41 can also be used as the IH shift registers 22 and 23 in the vertical contour extraction circuit 2.

Note that in each embodiment, the constant generators 13, 3137 .
Although the multiplication of 45 and the edge signal is performed by the multiplier 14.32, it may also be constructed from a ROM in which the multiplication results are stored in advance as a table.

Also, in the vertical contour extraction circuit 21, a vertical edge signal d is obtained using the pixels of the current field and the previous field.
Although the signal is added to the signal of the current field, the same effect can be obtained even if the current field and the subsequent field are used.

Effects of the Invention According to the present invention, even if an inter-field digital contour compensation circuit is used in the duty direction, if the inter-field correlation becomes weak, it is detected by a frame difference signal or a field difference signal, and contour enhancement is performed. By adjusting the degree, deterioration such as false contours and afterimages due to excessive contour compensation can be removed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional example of a digital contour compensation circuit in the horizontal direction, Fig. 2 is a waveform diagram showing the operation of a model U4.8A3 illustrated digital contour compensation circuit showing the zumble point of the 'r■ signal, and Fig. 4 is a waveform diagram showing the operation of the digital contour compensation circuit. Figure 5 is a block diagram of a conventional example of an inter-field digital contour compensation circuit; Figure 5 is a schematic diagram showing a television picture im; Figure 6 is a block diagram of the first embodiment of the present invention; FIG. 8 is a block diagram of a third embodiment of the present invention. ]・Input terminal, 2 Horizontal contour extraction circuit, 3 to 6・Register, 7 to 9・Adder, ]0 Multiplier, 11・Subtractor, J
2 - Multiplier, 13 Horizontal constant generator, 14 - Multiplier, 1
5.Adder, 20 Field memory, 21.Vertical contour extraction circuit, 22-24 Shift register, 25-27...
Adder, 28... Multiplier, 29 - Subtractor, 30 Multiplier, 31 Vertical constant generator, 32... Next p unit; 33
Adder, 35...Field memory, 36, Subtraction 3"4
4] IH shift register, 42 Adder, 43 Multiplier, 14 Subtractor, 45 Vertical constant generator, 51st rule l No. 61 No. 1 J Σ+'5 7 l≦1

Claims (3)

[Claims] (1) A digital contour compensation circuit that processes a phase encoded television signal, which identifies a certain pixel in the current field, a plurality of pixels in the current field vertically adjacent to this specific pixel, and the current field. a vertical contour extraction circuit that creates an edge signal by extracting a vertical contour portion using a number of pixels of a previous field or a rear field that are vertically adjacent to a pixel of the current field; and a field of a specific pixel of the current field. a correlation calculation circuit that calculates inter-field correlation; a constant generation circuit that changes the magnitude of a constant that determines the sum of edge enhancement according to the strength of the inter-field correlation calculated by the correlation calculation circuit; A digital contour compensation circuit comprising a multiplier that performs multiplication and an adder that adds the multiplication result of this multiplier to a specific pixel of an All storage field. (2) The correlation calculation circuit is constituted by a frequency reducer that obtains a frame difference signal between a specific pixel in the current field and a pixel at the same position one frame before. The digital contour compensation circuit described in . (3) The correlation performance circuit generates a field difference signal between the average value of the specific pixel of the current field and two pixels of the previous field or the field after I''i that are vertically adjacent to the specific pixel of the current field. A digital contour compensation circuit according to claim 1, wherein the digital contour compensation circuit is constituted by a subtracter for determining the contour.