JP2944284B2 - Multi-screen display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen display device for displaying an image suitable for a video signal on a multi-screen composed of a plurality of displays, and more particularly, to an NTSC video signal and a high-vision video. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen display device capable of projecting an image on a multi-screen composed of a plurality of NTSC-type display devices with respect to various types of video signals such as signals or computer video signals.

[0002]

2. Description of the Related Art A conventional multi-screen display device is disclosed in Japanese Patent Application Laid-Open No. 2-243074 or Japanese Patent Application No. 2-262510. The former multi-screen display device is for enlarging and displaying an image that matches the NTSC video signal on a multi-screen, and the latter multi-screen display device is for displaying an image that matches the Hi-Vision video signal on a multi-screen. This is for enlarging the display. As described above, only a video signal of a single system is input, and video signals of various systems are not input.

[0003] Also, an image suitable for a video signal of a computer has different horizontal frequency, vertical frequency, the number of display pixels and the like depending on the model. Can not. Therefore, an image that matches the image signal of the computer is converted into an NTSC or Hi-Vision image signal using a scan converter, and then enlarged and displayed on a conventional multi-screen display device.

FIG. 1 shows an example of a system for displaying video signals of various types in a mixed manner on the same multi-screen. The NTSC video signal from the NTSC video source 51 is input to an NTSC multi-screen display device 52 dedicated to the NTSC system and subjected to interpolation processing and the like. The high-definition video signal from the high-definition video source 53 is once input to the video switcher 56. The video signal from the computer 54 is converted into a high-vision video signal by the scan converter 55 and then input to the video switcher 56. The video switcher 56 selects one of the high definition video signals, and the selected video signal is
The data is input to the high-vision multi-screen display device 57 dedicated to the high-vision system, and interpolation processing and the like are performed. In the video switcher 58, one video signal is selected from both the multi-screen display devices 52 and 57, and a video corresponding to the selected video signal is displayed on the multi-screen 59.

[0005]

According to the prior art, in order to simultaneously display NTSC video signals, Hi-Vision video signals or computer video signals on the same multi-screen, as shown in FIG. , Multi-screen display devices 52 and 57 and scan converters corresponding to each system
It requires a lot of equipment, such as 55, making it a very expensive system. In addition, as for the image of the computer, since the method of the image signal is once converted by the scan converter 55, the image quality is largely deteriorated.

[0006] The present invention has been made in view of the above-described circumstances, and an image is displayed on an NTSC system video signal, a high-vision system video signal, or a computer video signal on the same multi-screen with little deterioration in image quality. Can be displayed,
It is another object of the present invention to provide an inexpensive multi-screen display device.

[0007]

A multi-screen display device according to the present invention is a multi-screen display device for enlarging and displaying an image corresponding to an input analog video signal on a multi-screen composed of N NTSC display units. In the screen display device, a reference clock generating means for programmably generating a reference clock of an arbitrary frequency in synchronization with a horizontal synchronization signal of an input video signal, and an A / D converter for A / D converting the video signal with the reference clock D conversion means, a video signal obtained by N divided according to a / D converted video signal to said N display it
And N image memories for storing the, respectively, and a memory control means for controlling said each video memory to read out the video signal stored N divided into respective video memory in accordance with the scanning format of the NTSC system, the NTSC N interpolating means for creating interpolated video data in accordance with an enlargement ratio from each of the N-divided video signals read according to the scanning format, and N D / A for D / A converting the interpolated video signal Conversion means,
An image corresponding to the D / A-converted image signal is enlarged and displayed on the multi-screen.

[0008]

In the multi-screen display device according to the present invention, an input analog video signal is digitized by a reference clock generated in synchronization with a synchronization signal of the input video signal.
The scanning method of the digitized video signal is converted to the scanning method of the NTSC system, interpolation video data is created from the video signal after the scanning method conversion according to the required magnification, and the video signal after interpolation is converted to analog. Output to each multi-screen display.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments. FIG. 2 is a block diagram showing a basic configuration of one embodiment of the multi-screen display device according to the present invention.
Here, in order to facilitate the explanation, a case where an image is enlarged and displayed on a multi-screen constituted by N = 4, that is, four NTSC display units will be considered.

In FIG. 2, reference numeral 1 denotes an A / D converter for converting an input analog video signal into a digital signal. The A / D converter 1 converts the converted video signal into an NTSC signal. Output to four video memories 7a, 7b, 7c, 7d. Each of the video memories 7a, 7b, 7c, 7d stores a rectangular area of the input video signal to be displayed by the memory in an NTSC format. Reference numeral 2 denotes a synchronization separation circuit that separates a synchronization signal from an input video signal. The synchronization separation circuit 2 outputs the separated synchronization signal to the programmable PLL 3. The programmable PLL 3 generates a reference clock having an appropriate frequency according to the type of the input video signal,
The generated reference clock is output to the write control circuits 5a, 5b, 5c, 5d that control the timing of writing to each of the video memories 7a, 7b, 7c, 7d. The video signal input by the A / D converter 1 is A / D converted according to the reference clock, and the digitized video signal is stored in the video memory 7a,
Input to 7b, 7c, 7d.

4 generates an NTSC reference clock.
NTSC clock generation circuit, NTSC clock generation circuit 4
Generates a reference clock of usually 8 Fsc or 4 Fsc (Fsc is a subcarrier frequency), and outputs the respective video memories 7a, 7b, 7c,
The generated reference clock is output to read control circuits 6a, 6b, 6c and 6d for controlling the read timing from 7d. Then, according to this reference clock, each video memory
Video signals are read from 7a, 7b, 7c, 7d to each of the programmable two-dimensional interpolation filters 8a, 8b, 8c, 8d.

The programmable two-dimensional interpolation filters 8a, 8
b, 8c, 8d create interpolated video data according to the required enlargement ratio, and output the interpolated video data to video processing circuits 9a, 9b, 9
Output to c, 9d. The video processing circuits 9a, 9b, 9c, 9d perform processes such as adding blanking and output the processed video signals to the respective D / A converters 10a, 10b, 10c, 10d. D / A
The converters 10a, 10b, 10c, and 10d convert the input video signals into analog signals, and output four NTSC-type displays 13a, 13b, 13c, and 13d.
To the multi-screen 13 composed of The multi-screen 13 displays an image that matches the input image signal.

In FIG. 2, reference numeral 11 denotes a programmable P
LL3 and programmable two-dimensional interpolation filters 8a, 8b,
8c and 8d are controlled by the CPU 11.
Input means 12 such as a keyboard or a communication line for inputting values to be set to them is connected. FIG. 3 shows a configuration example of the programmable PLL 3. As shown in FIG. 3, the programmable PLL 3 includes a phase comparator 31 that compares the phase of the input horizontal synchronization signal with a signal generated by dividing the reference clock, and a low-pass that integrates the output of the phase comparator 31. Filter 32 and multiple voltage controlled oscillators (VCOs)
It comprises 33a, 33b, 33c, 33d and a programmable frequency divider 34 for dividing the reference clock generated by each VCO 33a, 33b, 33c, 33d. Here, by appropriately setting the frequency division ratio of the programmable frequency divider 34 in accordance with the input video signal, a reference clock having an arbitrary frequency synchronized with the video signal can be created.

A plurality of (four in this embodiment) VCs
The reason for providing O is that the range of the generated reference clock is wide ranging from several MHz to one hundred and several tens of MHz, and one V
This is because it is difficult to cover the entire range with CO. Therefore, a plurality of VCOs are switched as appropriate according to the frequency to be transmitted. FIG. 4 shows a configuration example of a vertical filter among the programmable two-dimensional interpolation filters 8a, 8b, 8c, and 8d. Note that the horizontal filter has substantially the same configuration, and a description thereof will be omitted. As an interpolation filter,
Although many types such as a linear interpolation filter can be considered, a tertiary interpolation filter will be briefly described here.

In FIG. 4, line memories 81a, 81b, which give a delay of one scanning line to an input video signal, respectively.
81c are arranged in series in this order. Reference numeral 7 denotes a line counter for selecting a multiplication coefficient based on the count value, and its cycle changes according to the enlargement ratio. For example, in the case of a 1.5-fold magnification in which three scanning lines are formed from two scanning lines, the line counter 7 operates as a ternary counter, and in the case of 1.4-times in which seven scanning lines are formed from five. Operates as a hex counter. That is, when making B books from A books, it operates as a B-ary counter. The line counter 7 supplies the information of the selected multiplication coefficient to the coefficient RAMs 83a, 83b, 83c, 83d which hold the multiplication coefficients. Each coefficient RAM 83a,
The contents of 83b, 83c, 83d are rewritten by the enlargement ratio. Video signal input to line memory 81a and coefficient RAM 83a
Is supplied to the multiplier 84a, where the video data and the coefficient are multiplied. Similarly, the video signal output from the line memory 81a and the coefficient from the coefficient RAM 83b are given to the multiplier 84b, and the video signal output from the line memory 81b and the coefficient from the coefficient RAM 83c are multiplied by the multiplier 84c.
, And the video signal output from the line memory 81c and the coefficient from the coefficient RAM 83d are supplied to a multiplier 84d, and the multipliers 84b, 84c, and 84d multiply the video data by the coefficient. The outputs of the multipliers 84a, 84b, 84c, 84d, that is, the video signals for the four lines to which the respective coefficients are multiplied, are added by the adders 85a, 85b, 86 to create interpolated video data. When the video signals of the same line are read from the video memories 7a, 7b, 7c, 7d, the line memories 81a, 81b, 81c are controlled so as not to be updated.

As described above, each of the programmable two-dimensional interpolation filters 8a, 8b, 8c, and 8d creates interpolated video data from the video signals of four lines before and after, and the cycle of the line counter and the contents of the coefficient RAM. Can be adjusted to various magnifications. The interpolation filter in the horizontal direction can be created with the same configuration. However, in the case of the horizontal direction, it is also possible to change the cycle of the read clock to change the enlargement ratio.

Next, the operation will be described. The synchronization signal separated from the input video signal by the synchronization separation circuit 2 is input to the programmable PLL 3, where a reference clock having an appropriate frequency is generated according to the type of the input video signal. According to this reference clock, A /
The video signal A / D converted by the D converter 1 is supplied to the video memory 7 by the control operation of the write control circuits 5a, 5b, 5c and 5d.
Input to a, 7b, 7c, 7d.

Reading from the video memories 7a, 7b, 7c, 7d must be performed by NTSC synchronization. Therefore, according to the NTSC reference clock generated by the NTSC clock generation circuit 4, the read control circuits 6a, 6b, 6c,
By the control operation of 6d, the video signals are converted from the video memories 7a, 7b, 7c, and 7d according to the preset horizontal enlargement ratio and vertical enlargement ratio independently by a programmable two-dimensional interpolation filter.
Read out to 8a, 8b, 8c, 8d. The NTSC reference clock may be created in synchronization with an externally supplied NTSC synchronization signal. Here, the number of horizontal pixels and the number of scanning lines of the input video signal are not necessarily integer multiples of the NTSC system, so the horizontal enlargement ratio and the vertical enlargement ratio are not integer multiples,
It must be able to be set arbitrarily to some extent.

As described above, the video memories 7a, 7b, 7c, 7d
The input and output video signals are scan-converted into NTSC horizontal and vertical frequencies by controlling the writing and reading of data. The video signals read from the video memories 7a, 7b, 7c, 7d are normally displayed as they are because the same video data is repeated multiple times or zero data is inserted according to the magnification. No, it is necessary to create interpolation data. Therefore, in the programmable two-dimensional interpolation filters 8a, 8b, 8c, and 8d, interpolated video data is created from the supplied video signal in accordance with the independently set horizontal enlargement ratio and vertical enlargement ratio.

The video signals of the NTSC system created in this way are subjected to processing such as addition of blanking in video processing circuits 9a, 9b, 9c and 9d, and then to D / A converters 10a, 10b and 10c. ,
D / A conversion is performed in 10d, and an image corresponding to the image signal is displayed on the multi-screen 13. By the way, in the case of a multi-screen display device, since there are a plurality of displays, it may be necessary to simultaneously display different images on a multi-screen. FIG. 5 shows the configuration in that case. As shown in FIG. 5, three A / D converters 1A, 1B, and 1C, synchronization separation circuits 2A, 2B, and 2C, and programmable PLLs 3A, 3B, and 3C correspond to each image (three types in this embodiment). And a switch circuit 14 for selecting an input for each video memory is inserted between these and each of the video memories 7a, 7b, 7c, 7d. With this configuration, multiple images can be simultaneously displayed on the multi-screen 13
Can be displayed.

Further, in the multi-screen display device of the present invention,
When displaying an image suitable for a video signal having a larger number of display pixels than the NTSC system on a single NTSC display, it is necessary to reduce the image. It is also possible to process the reduction of the image simply by thinning out the scanning lines or pixels. In that case,
Since the image information of the decimated portion is completely lost, the deterioration of the image quality is increased. It is also possible to reduce the size by a two-dimensional interpolation filter arranged at the subsequent stage of the video memory. In that case, however, it is necessary to store a portion of the display area larger than the display area of the NTSC system in the video memory in advance, It is necessary to increase the storage capacity of the video memory.

Therefore, a two-dimensional filter for reduction may be arranged at the preceding stage of the video memory. FIG. 6 shows a configuration example of the vertical reduction filter. The vertical reduction filters are K and 1 respectively.
Multipliers 1 and 4 having a coefficient of −K, an adder 2 that adds outputs of the multipliers 1 and 4, and a line memory 3 that delays a video signal by one line. The reduction ratio of this filter is fixed at な い し or 等, and the fine reduction ratio can be set in combination with an enlargement filter arranged at the latter stage of the video memory.

Here, for example, in the case of 1/2 reduction, if the values of the coefficients K and 1-K are changed for each line as shown in FIG. 7, an output obtained by averaging two lines every other line is taken out. By writing this output to a video memory, a reduction of 1/2 can be realized without losing video information. Also, K is 1, 1/2, 1/2 or 1, 2 /
If it is changed to 3, 1/4, 1/3 reduction can be realized.
Note that multiplication such as 1/2, 1/4, etc. can be easily realized without using a multiplier by bit shifting. Similar to the above operation, the horizontal direction can be reduced.

When an input video signal is obtained by interlaced scanning, a scanning line reversal phenomenon as pointed out in Japanese Patent Application Laid-Open No. 243074 is caused by the multi-screen display device of the present invention. But the same is true. Therefore, also in this case, if the A / D-converted video signal is first converted to motion-adaptive sequential scanning, and then time-base conversion and enlargement processing are performed, the scanning line reversal phenomenon can be prevented. The details of such processing are the same as in Japanese Patent Application Laid-Open No. 243074, and will not be described.

[0025]

As described above, in the multi-screen display device according to the present invention, the frequency of the reference clock is made programmable.
In addition to the NTSC system, various types of video signals are digitized, and the scanning method of the digitized video signals is changed to NTSC.
It converts to the SC system scanning method, creates interpolated video data from the video signal after the scanning method conversion according to the required enlargement ratio, converts the interpolated video signal into analog and displays it on the multi-screen, so that the NTSC system Video signals, not only images that match the high-definition video signals, but also images that match the video signals of various types such as computers can be expanded on the same multi-screen with a single device while minimizing image quality degradation. Can be displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a conventional system for displaying video on the same multi-screen for video signals of various types in a mixed manner.

FIG. 2 is a block diagram illustrating a basic configuration of a multi-screen display device according to the present invention.

FIG. 3 is a block diagram showing an internal configuration of a programmable PLL in FIG. 2;

FIG. 4 is a block diagram showing an internal configuration of a programmable two-dimensional interpolation filter in FIG. 2;

FIG. 5 is a block diagram showing a configuration of an embodiment of the present invention when a plurality of videos are simultaneously displayed.

FIG. 6 is a block diagram showing an internal configuration of a two-dimensional filter for reduction.

FIG. 7 is a diagram showing a change in a coefficient and a change in an output of the filter shown in FIG. 6;

[Explanation of symbols]

 1, 1A, 1B, 1C A / D converter 2, 2A, 2B, 2C Synchronous separation circuit 3, 3A, 3B, 3C Programmable PLL 4 NTSC clock generation circuit 5a, 5b, 5c, 5d Write control circuit 6a, 6b, 6c, 6d Readout control circuit 7a, 7b, 7c, 7d Video memory 8a, 8b, 8c, 8d Programmable two-dimensional interpolation filter 10a, 10b, 10c, 10d D / A converter 13 Multi-screen 13a, 13b, 13c, 13d Display vessel

Continuation of the front page (72) Inventor Yukio Fujise 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 5/45

Claims (1)

(57) [Claims] 1. A multi-screen display device for enlarging and displaying an image corresponding to an input analog video signal on a multi-screen composed of N NTSC display units, wherein a horizontal synchronization signal of the input video signal is provided. A reference clock generating means for generating a reference clock of an arbitrary frequency in a programmable manner in synchronization with the video signal;
D conversion A / D conversion means and the video signal obtained by N divided according to A / D converted video signal to said N indicator
, Respectively , memory control means for controlling each of the video memories so as to read out the N divided video signals stored in each of the video memories in accordance with the scanning format of the NTSC system, Read according to scanning format
Includes N number of interpolation means for generating an interpolation video data respectively in accordance with the enlargement ratio from the video signal of the N-divided that is, the N number of D / A converting means for the interpolated video signal to D / A conversion A multi-screen display device, wherein an image corresponding to the D / A-converted video signal is enlarged and displayed on the multi-screen.