JPH0759055A - Video signal system converter - Google Patents

Abstract

PURPOSE:To execute system conversion to a video signal of a high clock rate without distortion by using plural filters and switching any of various filters through a scanning line structure and motion discrimination signal so as to apply interpolation processing to horizontal and vertical signals. CONSTITUTION:An input video signal is converted into a digital signal with a clock signal generated by a programmable PLL circuit 3 from a synchronizing signal separated at a synchronizing separator circuit or the like. That is, a digitized input video signal has a prescribed number of video signal data D1, D2 per one scanning line. Then odd numbered video data D1, D3... are inputted to a 1st video memory 2A and even numbered video data D2, D4... are inputted to a 2nd video memory 2B by an S/P conversion circuit 13. Then the data are written in the memory 2A according to a write control signal being an output of control circuits 4A, 4B selected by a scanning line structure and motion discrimination signal to be received. Furthermore, the data are similarly written in the memory 2B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal system converter for converting an input video signal into a video signal of a different scanning system.

[0002]

2. Description of the Related Art A video signal system converter of this type is disclosed in Japanese Patent Laid-Open No. 1-295587 (H04N 9/0).
There is an invention of 0).

FIG. 8 shows a block diagram of this first conventional example.

A video signal (hereinafter referred to as an input video signal) input to the apparatus is synchronously separated by a synchronous separation circuit (not shown), and the separated horizontal synchronous signal generates a reference clock. A programmable PLL (Phase locked loop) 3 Is supplied to. It can oscillate at any frequency in synchronization with the horizontal sync signal, and the reference clock generated by the PLL3 is A
The input video signal is input to the / D converter 1 and analog / digital converted (hereinafter referred to as A / D conversion).

The input video signal is A / D converted by the A / D converter 1.
After being D-converted, it is written in the video memory 2 capable of asynchronously writing and reading with the size of the image of the video signal to be output.

The memory write control circuit 4 outputs the write control signal of the video memory 2 from the sync signal of the input video signal, and the memory read control circuit 5 outputs the sync signal of the video signal to be output from the device (hereinafter referred to as the output video signal). The read control signals of the video memory 2 are asynchronously generated.

Therefore, the A / D converter 1 causes the A / D converter to
The converted input video signal is once written in the video memory 2 by the write control signal generated by the memory write control circuit 4, and read from the video memory 2 by the read control signal generated by the memory read control circuit 5. The read control signal is a signal that changes depending on the enlargement ratio in order to enlarge the image according to the set enlargement ratio.

In accordance with the read control signal, the video signal read from the video memory 2 is supplied to the programmable interpolation filter 6, filtered, and then D / A changed by the D / A converter 7. The output from the D / A converter 7 is applied as an output video signal to a display device (not shown) corresponding to the video signal format to display a video.

However, according to this, when the video signal of the still image is converted by the interlace method, for example, one diagonal line is displayed on the original image. When this original image is interpolated by the above-mentioned circuit, the interpolated image is disturbed such as a three-fold diagonal line and a smooth line is not reproduced, so that it is converted into a low-quality video signal.

Therefore, the present applicant has previously proposed Japanese Patent Application No. 4-246713 as a second conventional example.

FIG. 9 is a block diagram showing a second conventional example. The same parts as those of the first conventional example are designated by the same reference numerals and the description thereof will be omitted.

The input video signal is A / D converted by the A / D converter 1.
After being D-converted, it is written in the video memory 2. still,
Unlike the first conventional example, the video memory has a capacity of at least one frame or more of the format of the video signal to be read from the video memory 2. A clock generated by a PLL3 as a clock generating means is used as a reference clock for A / D conversion by the A / D converter 1, and the PLL3 is generated by a synchronizing signal of an input video signal.

Reference numerals 51, 52 and 53 respectively denote memory read control circuits, but these all function as memory read control means.

The memory write control circuit 4 asynchronously controls the video memory write control signal from the input video signal sync signal, and the memory read control circuits 51, 52 and 53 asynchronously control the video memory read control from the output video signal sync signal. To generate.

However, the memory read control circuit 51 is used when the input video signal is the non-interlace type, and the memory read control circuit 52 is the memory read control circuit 5 when the input video signal is the interlaced type and is a moving image.
Reference numeral 3 outputs a memory read control signal when the input video signal is an interlace system and is a still image.

On the other hand, the input video signal is also given to the scanning line structure discriminating circuit 8 as the scanning line structure discriminating means and the motion discriminating circuit 9 as the motion discriminating means.

The scanning line structure determination circuit 8 determines whether the scanning line structure of the input video signal is the interlace system or the non-interlace system. Further, the motion determination circuit 9 determines whether the input video signal is a moving image or a still image.

The determination result of whether the video signal by both of the determination circuits 8 and 9 is an interlace system or a non-interlace system, and whether it is a moving image or a still image is determined by the memory as memory control switching means. Readout switching circuit 10
Given to.

The memory read switching circuit 10 supplies one of the memory read control signals output from each of the memory read control circuits 51, 52 and 53 to the video memory 2 in accordance with the result of the discrimination by the discrimination circuits 8 and 9. Switch.

Since there is no inter-field correlation in the interlaced video signal, only the information of one field video signal is used. In the interlaced still video signal, inter-field correlation is used. Therefore, the conversion to the non-interlace system is performed using the information of the video signals of both the odd and even fields.

In accordance with the video memory read control signal supplied from the memory read control switching circuit 10, the non-interlace type video signal read from the video memory 2 in this way is supplied to the programmable interpolation filter 6 as an interpolation means. After being supplied and filtered, the non-interlace / interlace system conversion circuit 11 converts the signal again into an interlace system signal, and the D / A converter 71
Is D / A converted in step S4 and output to a display device (not shown) corresponding to the converted video signal format.

As a result, even when the input video signal is a still image of the interlace system, a high quality image is obtained without causing an interference such as an image in which one line is overlapped or a slant line is not reproduced smoothly. It is possible to obtain the video signal of. Furthermore, by providing two D / A converters, a monitor compatible with standard-speed video signals can also be used.
It can also be displayed on a monitor that supports double-speed video signals.

[0023]

However, when video conversion is performed, an interpolation filter composed of a multiplier and an adder is required for the output video signal in order to perform distortion-free conversion. Then, a certain amount of time is required to perform these interpolation calculations. So NTSC, P
In the case of conversion to a video signal format with a low output clock rate such as AL (for example, NTSC has a clock rate of 4 fsc = 14.3 MHz), the required time does not matter much, but a high-definition video signal (clock In the case of converting to a rate: 72.25 MHz) and outputting, it becomes difficult to perform multiplication and addition within one clock because the clock rate is high. That is, it becomes extremely difficult to perform a moving image in real time.

Further, when converting an interlaced still image into a video signal as in the second conventional example, it is necessary to perform a filtering process using the correlation in the time axis direction. In this conventional example, the reading from the video memory is output at a double speed (non-interlace for NTSC, clock rate: 8 fsc = 28.6 MHz) which is the format of the output video signal, and the filtering process is performed. However, when converted into an output video signal of high-definition or the like, the clock rate of the filter processing becomes 148.5 MHz, and such a very fast clock cannot be operated, and output is performed without performing the filter processing. Therefore, a low-quality output video signal is obtained while leaving the aliasing distortion due to the interpolation in the neighborhood data.

The present invention is to solve the above problems.

[0026]

According to the present invention, there is provided clock generating means for generating a reference clock having an arbitrary frequency in synchronization with a horizontal synchronizing signal of an input video signal, and a reference clock generated by the clock generating means. A / D conversion means for A / D converting the video signal, video memory means for storing at least one frame of the video signal A / D converted by the A / D conversion means, and video for the video memory means Memory control means for scanning and converting an input video signal into a video signal having a different format by writing and reading signals asynchronously, and an interpolation means for interpolating the video signal read from the video memory means. And a D / A for D / A converting the video signal interpolated by the interpolating means.
In a video signal system converter provided with a converting means, a scanning line structure discriminating means for discriminating whether a scanning line structure of an inputted video signal is an interlace system or a non-interlace system, The motion discriminating means for discriminating whether the video signal is a moving image or a still image, a memory control switching means for switching the output of the memory control means by the two discriminating means, and the interpolating means are the video memory means. At least two pieces of video data read by the same are input at the same time, and the first switching means for switching at the outputs of the two determination means, and 1 / of the output video signal clock
The present invention provides a video signal system converter characterized by comprising n vertical interpolating means for performing data interpolation in the vertical direction of a video signal with n clocks.

Further, according to the present invention, a clock generating means for generating a reference clock having an arbitrary frequency in synchronization with the horizontal synchronizing signal of the inputted video signal, and an A / D video signal by the reference clock generated by the clock generating means. A / D conversion means for D conversion, video memory means for storing at least one frame of the video signal A / D converted by the A / D conversion means, and writing / reading of the video signal to / from the video memory means Are performed asynchronously to perform a scan conversion of the input video signal into a video signal of a different format, an interpolation means for interpolating the video signal read from the video memory means, and the interpolation means. In the video signal system conversion device including a D / A conversion unit for D / A converting the video signal interpolated by the above, the interpolation unit is the video memory. Second switching means for converting the video data read from the stage into at least two parallel video data and switching them in the horizontal direction, and data interpolation in the horizontal direction of the video signal with a clock of 1 / m of the output video signal clock. The present invention provides a video signal system conversion device characterized by comprising m horizontal interpolating means for performing.

Further, according to the present invention, the video signal is synchronized with the horizontal synchronizing signal of the input video signal, and the clock signal is generated by the clock generating means for generating the reference clock of an arbitrary frequency and the reference clock generated by the clock generating means. A / D for D / D conversion
Converting means, a video memory means for storing at least one frame of the video signal A / D converted by the A / D converting means, and writing and reading the video signal to and from the video memory means asynchronously The memory control means for scanning and converting the input video signal into a video signal having a different format, the interpolation means for interpolating the video signal read from the video memory means, and the video interpolated by the interpolating means. In a video signal system converter including a D / A converter for D / A converting a signal, it is determined whether the scanning line structure of the input video signal is an interlace system or a non-interlace system. The scanning line structure determination means, the motion determination means for determining whether the input video signal is a moving image or a still image, and the two determination means The memory control switching means for switching the output of the memory control means and the interpolating means simultaneously input at least two video data read from the video memory means, and first switching means for switching the output by the output of the two discriminating means. And n vertical interpolating means for interpolating data in the vertical direction of the video signal with a clock of 1 / n of the output video signal clock, and digital video data are converted into at least two parallel video signals and replaced in the horizontal direction. Second to do
A video signal system characterized by comprising switching means and m horizontal interpolation means for performing data interpolation in the horizontal direction of the video signal at a clock of 1 / m (including n = m) of the output video signal clock. A conversion device is provided.

Further, according to the present invention, a clock generating means for generating a reference clock having an arbitrary frequency in synchronization with the horizontal synchronizing signal of the input video signal, and an A / D video signal by the reference clock generated by the clock generating means. A / D conversion means for D conversion, video memory means for storing at least one frame of the video signal A / D converted by the A / D conversion means, and writing / reading of the video signal to / from the video memory means Are performed asynchronously to perform a scan conversion of the input video signal into a video signal of a different format, an interpolation means for interpolating the video signal read from the video memory means, and the interpolation means. In a video signal system conversion device including D / A conversion means for performing D / A conversion on the video signal interpolated by the above method, the scanning line structure of the input video signal A scanning line structure discriminating means for discriminating between the interlace system and the non-interlace system; a motion discriminating means for discriminating whether the input video signal is a moving image or a still image; The memory control switching means for switching the output of the memory control means by one discriminating means and the interpolating means simultaneously input at least two video data read from the video memory means, and output the two discriminating means. First to replace
A switching means, n vertical interpolating means for performing data interpolation in the vertical direction of the video signal with a clock of 1 / n of the output video signal clock, and digital video data are converted into at least two parallel video signals and horizontally A second aspect of the present invention is to provide a video signal system conversion device comprising: a second switching means for performing switching.

[0030]

According to the present invention, a plurality of filters are used, and various filters are switched depending on the scanning line structure and the motion discrimination to perform horizontal and vertical signal interpolation processing.

[0031]

1 is a block diagram of an embodiment of the present invention.
The same parts as those in the conventional example are designated by the same reference numerals and the description thereof will be omitted.

Reference numeral 13 is a serial / parallel (S / P) conversion circuit for processing the A / D converted input video signal at half the sampling clock thereof.

Reference numerals 2A and 2B are first and second video memories for storing the input video signal of half the clock in the S / P conversion circuit 13. The details of the first and second video memories are shown in FIG. That is, the write control signal causes the ODD portion and the EVEN portion of the video memory to be written at mutually inverted clocks, and the read operations are simultaneously controlled by the read control signal, so that they are read at the same timing. In addition, an enlarged video signal is output to read data according to the enlargement ratio.

Specifically, as shown in FIG. 2, for example,
The input video signal data sampled at 74.25 MHz (hereinafter referred to as the clock fa) is converted into the odd data D1,
The S / P conversion circuit 13 operates so that D3, D5, ... Are input to the first video memory 2A and even data D2, D4, D6 ,.

Reference numerals 4A and 4B denote circuits for controlling writing in the video memory, which are in synchronization with the sync signal of the input video signal and in which the input video signal is the non-interlace mode 1 and the interlaced still image mode. 2. The settings differ depending on various modes such as mode 3 which is an interlaced moving image.

14A and 14B are the respective video memories 2A,
2B odd field (ODD), even field (E
Matrix switches for switching the output of VEN) in a matrix manner, 61A and 61B are vertical interpolation filters for creating video data vertically interpolated by the outputs of the matrix switches 14A and 14B, and 15 is the output of two vertical interpolation filters. Parallel / serial (P /
S) A conversion circuit.

Reference numeral 16 enlarges the image at a predetermined enlargement ratio according to the settings of the viewer and the user, and also the horizontal interpolation filters 62A, 6A.
It is a horizontal enlargement / matrix switch circuit for switching the output to 2B. Reference numeral 17 is a parallel / series (P / S) conversion circuit that converts the outputs of the two horizontal interpolation filters into a series.

Next, the operation will be described with reference to FIG. The input video signal is a programmable PLL circuit 3 based on a sync signal separated by a sync separation circuit (not shown).
It is converted to a digital signal by the clock (here, the clock of the high-definition signal: 74.25 MHz) created in (4). That is, the number of digitized input video signals is about 2200 per scanning line (74.25 MHz / 33.75).
KHz (horizontal scanning frequency) video signal data D1, D
2, D3, D4, ... Then, the S / P conversion circuit 13 causes the odd-numbered video data D1, D3, ...
Are input to the first video memory 2A, and the even-numbered video data D2, D4, ... Are input to the second video memory 2B. Therefore, as shown in FIGS. 2c, 2d, and 2e, the clock frequency of the video memory is the clock (fa / 2), and the clock can be memorized with half the clock as compared with the memory memorized as it is.

Then, according to the scanning line structure and the motion discriminating signal inputted to the first video memory 2A, according to the writing control signal which is the output of the selected writing control circuit 4A, 4B, as shown in FIG. Written. Further, since writing is similarly performed in the second video memory 2B, the first video memory will be described here and the description thereof will be omitted.

In FIG. 3, numerals indicate scanning lines (lines). First, consider the case of mode 1 (non-interlace). Odd scanning lines are written in the ODD portion of the first video memory 2A, and even scanning lines are written in the EVEN portion. Then, in response to a read control signal from the read control circuit 5, two data in the ODD portion and the empty EVEN portion are simultaneously read. FIG. 3 shows reading at the same size as writing. Further, when the image is magnified at a magnification of several times instead of the same size, the same line is read continuously many times. That is, when enlarging by M / N times, enlarging is performed by increasing the number of scanning lines of the input video signal by M / N times.

ODD section and EVEN of the first video memory 2A
The signal read from the unit is the matrix switch 14A.
Are switched by the two discrimination signals and input to the vertical interpolation filter 61A.

Specifically, it is switched for each field by the discrimination signal, the matrix switch 14A is set to a: off, b: on, c: on, d: off in the odd field, and this switch 14A is set in the even field. It is set to a: on, b: off, c: off, d: on. As a result, in the odd field, scan lines of 1, 3, 5, ...
In the even field, the scanning lines of 4, 6, ... Are 2, 4, 6, ... From one output, and the scanning lines of 1, 3, 5 ,. Vertical interpolation filter 61
Input to A.

In the vertical interpolation filter 61A, the odd scanning lines and the even scanning lines are input to the vertical filter 64 and the line memories 63a and 63b, respectively, as shown in FIG.
These line memories 63a and 63b are switched between write enable / disable by write enable signals WE1 and WE2 created by a write signal generation ROM controlled by a CPU (control means, not shown), and one line Is to delay. Then, the data immediately before the data that is constantly updated is output.

As a result, four different scanning lines, for example, 3, 1, 4, and 2 scanning lines are input to the input terminals a, b, c, and d of the vertical filter 64, respectively. Then, the input scanning lines respectively change according to the enlargement ratio, and the coefficient obtained from the coefficient creating circuit 66 and the multiplication circuit 65.
It is multiplied by a, 65b, 65c and 65d. The multiplication output is added by the adder circuit 67, one scanning line is created from the data of these four scanning lines, and is output. here,
The line filter 63a, 63b does not output its output until it becomes a state different from the input, and the write control signal WE
Controlled by WE1 and WE2, input terminal a and input terminal b
The same input signal is input to the input terminal c and the input terminal d, which is unlikely to occur.

FIG. 4 shows one of the vertical interpolation filters, and two identical interpolation filters may be used to show the vertical interpolation filters 61A and 61B. Then, the outputs of the vertical interpolation filters 61A and 61B are converted into serial data by the P / S conversion circuit 15. This serial data is data that has been A / D converted by the clock fa, and is data that is obtained by vertically expanding and interpolating the data that has been input to the S / P conversion circuit 13.

Next, mode 2 (still image with interlace)
Think of when. In the ODD portion of the first video memory 2A, 1 to 512 scanning lines forming the first field are EV
513 to 1024 forming the second field in the EN section
Each scan line of the book is written. Then, it is read by the read control signal from the read control circuit 5. The signals read from the ODD section and the EVEN section of the first video memory 2A are switched by the two discrimination signals and input to the vertical interpolation filter 61A.

Specifically, switching is performed for each field as in the mode 1, and in odd-numbered fields, 1, 2, 3, 4, ...
The scanning lines 13, 514, 515, 516, ... 513, 514, 51 from one output in the even field.
The scanning lines of 5, 516, ...
The scanning lines of 2, 3, 4, ... Are vertical interpolation filters 61A.
Entered in.

Then, in the vertical interpolation filter 61A, 1, 2, 3, 4 are input to the input of the line memory 63A of FIG.
Of the scanning lines of 513 and 51 to the input of the line memory 63B.
4, 515, and 516 scanning lines are input, respectively.

As a result, four different scanning lines, for example, 2, 1, 514 and 513 scanning lines, respectively, are input to the input terminals a, b, c and d of the vertical filter 64. Then, the input scanning lines respectively change according to the enlargement ratio, and are multiplied by the coefficient obtained from the coefficient creating circuit 66 by the multiplying circuits 65a, 65b, 65c, 65d. The multiplication output is added by the adder circuit 67, one scanning line is created from the data of these four scanning lines, and is output.

Then, the vertical interpolation filters 61A and 61B
The output of is converted into serial data by the P / S conversion circuit 15. This serial data is A / at the clock fa
The data is D-converted data, which is data obtained by vertically expanding and interpolating the data input to the S / P conversion circuit 13.

Furthermore, mode 3 (interlaced video)
Think of when. At this time, the writing method in the memory is the same as that in the non-interlaced mode.
Odd scan lines are written in the ODD portion of A, and even scan lines are written in the EVEN portion. Then, the read control circuit 5
It is read by the read control signal from. The signals read from the ODD section and the EVEN section of the first video memory 2A are switched by the two discrimination signals and input to the vertical interpolation filter 61A.

However, at the time of reading, it is switched every time one line is read, and in the odd-numbered lines, the scanning lines of 1, 2, 3, 4, ... From one output are 2, 3, 4, 5, from the other output. The scanning lines of ... Are 513, 514, 515, 516, ...
Scan lines from the other output at 514, 515, 516,
The scanning lines 517 ... Are input to the vertical interpolation filter 61A.

Then, in the vertical interpolation filter 61A, 1, 2, 3, 4 are input to the input of the line memory 63A of FIG.
Scan lines of 2, 3, 4,
5 scanning lines are input respectively.

As a result, scan lines having the same b and c, for example, 1, 2, 2, and 3 scan lines are input to the input terminals a, b, c, and d of the vertical filter 64, respectively. Become. In the case of a moving image, since there is no correlation between fields, intra-field interpolation is performed, and scanning line 3 and scanning line 4 are data of scanning lines that are spatially separated from the scanning line to be interpolated. Because it is not very useful data. Therefore, the matrix switch is switched for each scanning line to interpolate such scanning lines and more scanning lines.

The input scanning lines change in accordance with the enlargement ratio, and are multiplied by the coefficients obtained from the coefficient creating circuit 66 by the multiplying circuits 65a, 65b, 65c and 65d. The multiplication output is added by the adder circuit 67, one scanning line is created from the data of these four scanning lines, and is output.

Then, the vertical interpolation filters 61A and 61B
The output of is converted into serial data by the P / S conversion circuit 15. This serial data is A / at the clock fa
The data is D-converted data, which is data obtained by vertically expanding and interpolating the data input to the S / P conversion circuit 13.

Next, the P / S converted signal is input to the horizontal enlargement / matrix switch circuit 16 to perform enlargement processing. This will be described in detail with reference to FIG.

The P / S converted signal is input to the delay circuits 20c and 20g of the horizontal expansion / matrix switch circuit 16. In the case of high-definition, the delay circuit 20g is a clock (fa / 2), and the delay circuit 20c is a bar (clock (fa / fa)
2)) is working. Further, the delay circuit 20d operates with the clock fa.

Then, the signals of FIGS. 6b and 6c are written in the line memories 20f and 20h at the clock (fa / 2), respectively. That is, the line memory 20f stores odd-numbered data D1, D3, D5, ...
The even-numbered data D2, D4, D6, ...
Written.

The written data is the OR circuit 20.
It is read by the outputs of a and 20b. Here, it is controlled by a CPU, which is not shown, as a control means, and Wait 1 and Wait from the Wait signal generating ROM according to the enlargement ratio.
The it2 signal and the clock (fa / 2) are used as inputs to the OR circuits 20a and 20b.

The Wait1 and Wait2 signals are shown in FIG.
The signals are shown as d and e, and change according to the enlargement ratio. That is, the Wait signal generation ROM stores the Wait signal according to each enlargement ratio for each address.

The signal obtained by performing the logical sum operation of the Wait1 and Wait2 signals and the clock (fa / 2) becomes the memory read signal shown in FIGS. 6f and 6g. here,
The magnification is shown as (16/15) times.

Therefore, the output h from the line memory 20f is not updated by one clock in the data D15 portion.
However, the output i which is not updated by one clock in the data D2 portion is read from the line memory 20h. That is, when the read signals f and g rise, the data stored in the line memories 20f and 20h are read, and the current data is held until the next rise.

The data read from the line memories 20f and 20h, respectively, are transferred to the matrix switch 20i at the matrix switch 20i.
The MX1 signal j for selection and the horizontal filter 6 on the side of the horizontal filter 62A from the ROM for creating a matrix switching signal according to the enlargement ratio, which is controlled by a CPU (not shown).
It is selectively output by the MX2 signal k for selection on the 2B side.

This selection is to supply either one of the outputs of the line memories 20f and 20h to the horizontal filters 62A and 62B depending on the combination of the MX1 and MX2 signals. That is, both the MX1 signal j and the MX2 signal k are at H level.
If it is a level, the output h of the line memory 20f is set as the switching output m, and the output i of the line memory 20h is set as the switching output n.
Are selected and output.

If the MX1 signal j is at H level and the MX2 signal k is at L level, the output h of the line memory 20f is selected and output as the switching outputs m and n.

Further, MX1 signal j is at L level, MX2
If the signal k is at H level, the output i of the line memory 20h is selected and output as the switching outputs m and n.

If both the MX1 signal j and the MX2 signal k are at the L level, the switching output m has the line memory 20.
The output i of h is selected and the output h of the line memory 20f is selected and output as the switching output n.

On the other hand, the input signal is input to the delay circuit 21, delayed by one data, and input to the horizontal enlargement / matrix switch 22 having the same circuit configuration as the horizontal enlargement / matrix switch 16, and the same as the above. Signal processing is performed. In this figure, the matrix switching signal M
The X, Wait signal and each clock are omitted.

Then, the processed signals are input to the horizontal filters 62A and 62B, respectively.

The signal delayed by the delay circuit 21 is further delayed by the delay circuit 23. Then, the signal processed by the horizontal enlargement / matrix switch 24 is input to the horizontal filters 62A and 62B.

In addition, the signal delayed by the delay circuit 23 is further delayed by the delay circuit 25. And
The signals processed by the horizontal enlargement / matrix switch 26 are input to the horizontal filters 62A and 62B.

As a result, four types of data are input to each horizontal filter. This input signal is sequentially input in the data string as shown in FIG. The horizontal filters 62A, 62B have a data string in which a predetermined coefficient group A,
It is a circuit that multiplies each coefficient of B and adds the obtained four data to create one data.

Therefore, for example, the first data output of the horizontal filter 62A is D1, D0, D (-1), D (-2).
It is the data obtained from the four data.

The signals obtained from the horizontal filters 62A and 62B are driven by the clock (fa / 2), and P / S
The conversion circuit 17 is driven by the clock fa which is a double clock of the clock. That is, the horizontal filter 62A interpolates odd-numbered data and the horizontal filter 62B interpolates even-numbered data, and the P / S conversion circuit 17 converts the odd-numbered data and the even-numbered data. Combined and converted to serial data.

In FIG. 7, the same data array (here, data D1, D0, (D-1), (D-1) in FIG. 7A and FIG. 9B is generated only once during the eight clock cycles of the clock (fa).
-2) and data D16, D15, D14, and D13). As a result, after P / S conversion, a video signal 16/15 times the input video signal is output.

Then, the serial data can be converted into analog by the D / A converter 7 to obtain an enlarged video signal.

Further, although two horizontal and vertical filters are respectively used for parallel processing, four or eight parallel processing may be performed depending on the relationship between the clock and the filter processing speed.

Further, in the embodiment, the video memory 2
Although writing is performed in parallel in A and 2B and interpolation processing is performed, it is possible to reduce the number of video memories to one by using a video memory that can operate at high speed. In this case, the S / P conversion circuit 13 at the input stage of the video memory
Is not required, but the S / Ps are respectively provided to the outputs of the matrix switches 14A and 14B connected to the two outputs of the video memory.
A conversion circuit is required. Then, one output of these S / P conversion circuits is input to the vertical interpolation filter 61A and the other output is input to the vertical interpolation filter 61B. Therefore, one input of each of the two S / P conversion circuits is connected to the vertical interpolation filter 61A so as to have two inputs, and the other input of each of the two S / P conversion circuits is connected to the vertical interpolation filter 61B. It has 2 inputs.

With this, the same effect can be obtained.

As another embodiment, the horizontal interpolation filters 62A and 62B may be deleted and the output of the horizontal expansion / matrix switch circuit 16 may be directly connected to the P / S conversion circuit 17. This is because the interpolation and enlargement operations are performed by the read control signals g and f of the circuit shown in FIG. 5, and the interpolation operation is performed without separately using the horizontal interpolation filters 62A and 62B as shown in FIG. Be seen.

[0082]

According to the present invention, it is possible to realize a high-definition video signal system converter which does not cause aliasing even in a video signal with a high clock.

Therefore, according to the present invention, when a high-definition video signal (clock rate: 72.25 MHz) is converted and output, the clock rate is high.
Multiplication and addition can be performed within the clock, and moving images can be processed in real time.

Further, according to the present invention, when an interlaced still image is converted into an output video signal of high-definition or the like, the clock rate of filter processing can be suppressed by parallel processing, and aliasing distortion due to interpolation in neighboring data can be prevented. be able to.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of the video memory according to the embodiment of the present invention.

FIG. 3 is a diagram showing each mode of the video memory according to the embodiment of the present invention.

FIG. 4 is a diagram showing a vertical filter according to an embodiment of the present invention.

FIG. 5 is a circuit block diagram of a horizontal expansion / matrix switch according to an embodiment of the present invention.

FIG. 6 is a time chart of the horizontal enlargement / matrix switch according to the embodiment of the present invention.

FIG. 7 is a time chart diagram of input of the horizontal filter according to the embodiment of this invention.

FIG. 8 is a circuit block diagram of a conventional example.

FIG. 9 is a circuit block diagram of another conventional example.

[Explanation of symbols]

 1 A / D converter 2A, 2B Video memory 3 Programmable PLL 4A, 4B Write control circuit 5 Read control circuit 61A, 61B Vertical interpolation filter 62A, 62B Horizontal interpolation filter 7 D / A converter 8 Scan line structure determination circuit 9 Motion Discrimination circuit 10 Switching circuit 13 S / P conversion circuit 14A, 14B Matrix switch circuit 15, 17 P / S conversion circuit 16 Horizontal enlargement / matrix switch circuit

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[Procedure amendment]

[Submission date] September 30, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0065

[Correction method] Change

[Correction content]

This selection is performed by the combination of the MX1 and MX2 signals into the horizontal filters 62A and 62B.
One of the outputs 0f and 20h is supplied. That is, when both the MX1 signal j and the MX2 signal k are at the H level, the output h of the line memory 20f is selected as the switching output m and the output i of the line memory 20h is selected as the switching output n and output.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0081

[Correction method] Change

[Correction content]

As another embodiment, the horizontal interpolation filters 62A and 62B may be deleted and the output of the horizontal expansion / matrix switch circuit 16 may be directly connected to the P / S conversion circuit 17. This is because the interpolation control and enlargement operations based on the neighborhood data are performed by the read control signals g and f of the circuit shown in FIG. 5, and the horizontal interpolation filters 62A and 62B are not separately used as shown in FIG. A low-order interpolation operation is performed.

Claims (4)

[Claims] 1. A clock generation means for generating a reference clock of an arbitrary frequency in synchronization with a horizontal synchronizing signal of an input video signal, and an A / D conversion of the video signal with the reference clock generated by the clock generation means. A / D conversion means, video memory means for storing at least one frame of the video signal A / D converted by the A / D conversion means, and writing and reading of the video signal to and from the video memory means are asynchronous Memory control means for scanning-converting the input video signal into a video signal having a different format, interpolation means for interpolating the video signal read from the video memory means, and interpolation processing by the interpolation means. In a video signal system conversion device including a D / A conversion means for D / A converting the input video signal, the scanning line structure of the input video signal is interleaved. A scanning line structure discriminating means for discriminating whether the input system is a video system or a non-interlace system; The memory control switching means for switching the output of the memory control means by one discriminating means, and the interpolating means simultaneously input at least two video data read from the video memory means, and output by the two discriminating means. A video signal system conversion device comprising: first switching means for switching and n vertical interpolation means for interpolating data in the vertical direction of the video signal with a clock of 1 / n of the output video signal clock. 2. A clock generating means for generating a reference clock of an arbitrary frequency in synchronization with a horizontal synchronizing signal of an input video signal, and an A / D conversion of the video signal with the reference clock generated by the clock generating means. A / D conversion means, video memory means for storing at least one frame of the video signal A / D converted by the A / D conversion means, and writing and reading of the video signal to and from the video memory means are asynchronous Memory control means for scanning-converting the input video signal into a video signal having a different format, interpolation means for interpolating the video signal read from the video memory means, and interpolation processing by the interpolation means. And a D / A conversion unit for D / A converting the generated video signal, wherein the interpolation unit reads from the video memory unit. Second switching means for converting the projected video data into at least two parallel video data and switching them in the horizontal direction, and performing data interpolation in the horizontal direction of the video signal with a clock of 1 / m of the output video signal clock. A video signal system converter comprising m horizontal interpolating means. 3. A clock generating means for generating a reference clock of an arbitrary frequency in synchronization with a horizontal synchronizing signal of an input video signal, and an A / D conversion of the video signal with the reference clock generated by the clock generating means. A / D conversion means, video memory means for storing at least one frame of the video signal A / D converted by the A / D conversion means, and writing and reading of the video signal to and from the video memory means are asynchronous Memory control means for scanning-converting the input video signal into a video signal having a different format, interpolation means for interpolating the video signal read from the video memory means, and interpolation processing by the interpolation means. In a video signal system conversion device including a D / A conversion means for D / A converting the input video signal, the scanning line structure of the input video signal is interleaved. A scanning line structure discriminating means for discriminating whether the input system is a video system or a non-interlace system, and a motion discriminating means for discriminating whether the input video signal is a moving image or a still image. The memory control switching means for switching the output of the memory control means by one discriminating means, and the interpolating means simultaneously input at least two video data read from the video memory means, and output by the two discriminating means. First switching means for exchanging, n vertical interpolating means for performing data interpolation in the vertical direction of the video signal with a clock of 1 / n of the output video signal clock, and digital video data converted into at least two parallel video signals,
It is composed of a second switching means for switching in the horizontal direction and m horizontal interpolating means for performing data interpolation in the horizontal direction of the video signal with a clock of 1 / m (including n = m) of the output video signal clock. A video signal system converter characterized by the above. 4. A clock generating means for generating a reference clock of an arbitrary frequency in synchronization with a horizontal synchronizing signal of an input video signal, and an A / D conversion of the video signal with the reference clock generated by the clock generating means. A / D conversion means, video memory means for storing at least one frame of the video signal A / D converted by the A / D conversion means, and writing and reading of the video signal to and from the video memory means are asynchronous Memory control means for scanning-converting the input video signal into a video signal having a different format, interpolation means for interpolating the video signal read from the video memory means, and interpolation processing by the interpolation means. In a video signal system conversion device including a D / A conversion means for D / A converting the input video signal, the scanning line structure of the input video signal is interleaved. A scanning line structure discriminating means for discriminating whether the input system is a video system or a non-interlace system, and a motion discriminating means for discriminating whether the input video signal is a moving image or a still image. The memory control switching means for switching the output of the memory control means by one discriminating means, and the interpolating means simultaneously input at least two video data read from the video memory means, and output by the two discriminating means. First switching means for exchanging, n vertical interpolating means for performing data interpolation in the vertical direction of the video signal with a clock of 1 / n of the output video signal clock, and digital video data converted into at least two parallel video signals,
A video signal system conversion device, comprising: a second switching means for switching in the horizontal direction.