JP2001022330A - Signal processor and display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display a high quality video signal by performing a noninterlace conversion, and an interpolation expansion or an interpolation contraction in a display device by expanding or contracting an interlace type video signal through its interpolation in the vertical direction, and conversion of its vertical frequency. SOLUTION: A vertical frequency and a horizontal frequency of an inputted interlace system video signal are converted into desired vertical and horizontal frequencies of the video signal by field memory 11, and a field discrimination signal Faw synchronized with the vertical frequency of the above desired video signal from a field discrimination signal Fac, and the outputs of vertical coefficient generation circuits 6, 24 for generating different vertical coefficients to a specific field and the other field respectively are selectively supplied to a vertical filter circuit 12 for expanding a video in the vertical direction by the field discrimination signal Faw.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for converting a horizontal frequency and a vertical frequency of a video signal, and expanding or reducing the number of pixels for display, and a display device using the same. The present invention is suitably applied to a signal processing device that converts a signal into a non-interlaced enlarged or reduced video signal and displays the converted video signal.

[0002]

2. Description of the Related Art Japanese Patent Laying-Open No. 6-276462 describes a method of converting the frequency and the number of pixels of a video signal. Further, Japanese Patent Application Laid-Open No. 7-095540 describes a method of setting an enlargement coefficient of the number of pixels. Further, when displaying an interlaced system such as a current color television signal on a display device of a non-interlaced system such as a liquid crystal display device, for example, Japanese Patent Laid-Open No. 3-258
177 can be converted from an interlace system to a non-interlace system.

FIG. 2 is a block diagram of a signal processing apparatus for converting the horizontal frequency and the vertical frequency and the number of pixels according to the prior art. In the figure, 1 is an input terminal of a video signal A, 2 is an input terminal of a horizontal synchronization signal HA and a vertical synchronization signal VA of the video signal A, 3 is an input control circuit, and 4 is a horizontal synchronization signal HB and a vertical synchronization signal of a video signal B. An input terminal of the signal VB, 5 is an output control circuit, 6 is a vertical filter coefficient generation circuit, 7 is an output terminal of the video signal B, 11 is a field memory, and 12 is a vertical filter circuit. The vertical filter circuit 12 includes a line memory 13, amplifiers 14, 15, and an adder 17.

First, a video signal A is supplied from an input terminal 1 to a field memory 11. On the other hand, the horizontal synchronization signal HA and the vertical synchronization signal VA of the video signal A are supplied from the input terminal 2 to the input control circuit 3. In the input control circuit 3, the terminal 2
A control signal is created from the synchronization signal from the controller and supplied to the field memory 11. On the other hand, the horizontal synchronization signal HB and the vertical synchronization signal VB of the video signal B different from the horizontal synchronization signal HA and the vertical synchronization signal VA of the video signal A are supplied from the input terminal 4 to the output control circuit 5. The circuit 5 creates a control signal from the synchronization signal from the terminal 4 and supplies the control signal to the field memory 11.

[0005] In the field memory 11, the video signal A from the terminal 2 is written by the control signal from the input control circuit 3 and the video signal B is read by the control signal from the output control circuit 5 to convert the horizontal frequency and the vertical frequency. Then, the obtained video signal B is supplied to the line memory 13 and the amplifier 14 in the vertical filter circuit 12. In the line memory 13, a video signal for one line is written and read, and a video signal delayed by one line is supplied to the amplifier 15.

On the other hand, in the vertical filter coefficient generation circuit 6,
The coefficient (M) of the vertical filter circuit synchronized with the horizontal synchronizing signal HB and the vertical synchronizing signal VB of the video signal B from the terminal 4
o, No) and supplies them to the amplifiers 15 and 14 in the vertical filter circuit 12, respectively.

The amplifier 14 multiplies the video signal input to the line memory 13, that is, the video signal of the current line (n line) by No. The amplifier 15 delays the video signal delayed by the line memory 13, ie, one line before (n -1 line)
Is multiplied by Mo and supplied to the adder 17. In the adder 17, the outputs from the amplifiers 15 and 16 are added,
The video signal B is subjected to vertical filter processing by the calculation of (video signal on the (n−1) th line) × Mo + (video signal on the nth line) × No, and is supplied to the output terminal 7.

In this way, the frequency conversion and the number of pixels of the video signal are performed so as to match the frequency of the display (not shown) connected to the terminal 7 and the number of display pixels.

[0009]

The above prior art is a method for converting the horizontal frequency and the vertical frequency and the number of pixels. Generally, a display device for receiving an output video signal (video signal B) is of a non-interlace type. . For this reason, when the input video signal (the video signal A) is of the interlace type, 1/1 is used in the first field and the second field.
Since the two lines are displaced, if the vertical filter processing is performed as it is, an undesired image which is displaced by ラ イ ン line for each field is displayed.

It is an object of the present invention to provide a signal processing device capable of displaying a high-quality image with no line shift even if an input video signal is of an interlace type, and a display device using the same.

[0011]

In order to achieve the object of the present invention, a signal processing apparatus according to the present invention is arranged to reduce the vertical frequency and horizontal frequency of an input interlaced video signal by the vertical frequency and horizontal frequency of a desired video signal. A field memory for converting to a horizontal frequency, interpolation and enlargement processing means for creating a new scanning line by interpolating video signals of horizontal scanning lines above and below the interlaced video signal and enlarging the image in the vertical direction, Means for obtaining a second field discrimination signal synchronized with the vertical frequency of the desired video signal from a first field discrimination signal synchronized with the vertical frequency of the input video signal; Vertical coefficient generating means for generating a coefficient, and an output of the vertical coefficient generating means is selected by the second field discrimination signal. Characterized in that it comprises a supply means for supplying to said interpolating enlargement processing means.

The means for obtaining the second field discrimination signal includes a memory, a means for writing the first field discrimination signal into the memory in synchronization with a vertical frequency of the input video signal, and Means for reading out the second field discrimination signal in synchronization with the vertical frequency of the desired video signal. The vertical coefficient generation means may include a first vertical filter coefficient generation circuit applied to a specific field of the second field determination signal and a second vertical filter coefficient generation circuit applied to another field of the second field determination signal. And a vertical filter coefficient generating circuit.

Further, the supply means includes a switch circuit, and controls the switch circuit by the second field discrimination signal. Further, the interpolation enlargement processing means is connected to an output of the field memory.
In the signal processing device, input control means for generating a control signal synchronized with a synchronization signal of an input video signal, and output control means for generating a control signal synchronized with a desired video signal are provided, Preferably, the field memory is controlled by means and the output control means.

In order to achieve the object of the present invention, a signal processing apparatus according to the present invention comprises a field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal; A signal processing device that receives an interlaced video signal, and obtains a non-interlaced video signal including an interpolation enlargement processing unit that creates a new scanning line by interpolation from upper and lower scanning lines and enlarges the image in a vertical direction A field discriminating means for discriminating a field from a synchronizing signal of an interlace method, and another means for outputting a discrimination result from the field discriminating means to a field discrimination signal synchronized with a vertical frequency of a signal converted by the field memory. Memory and the field memory from an interlaced synchronization signal. And input control means for controlling the field memory from a synchronizing signal of a non-interlace system, and vertical coefficient generating means for generating a plurality of coefficients and supplying the coefficients to the interpolation enlargement processing means. The coefficient from the vertical coefficient generating means is switched according to the output from the memory.

According to another aspect of the present invention, there is provided a signal processing apparatus for converting a vertical frequency and a horizontal frequency of an input interlaced video signal into a vertical frequency and a horizontal frequency of a desired video signal. A field memory, a video signal of a horizontal scanning line above and below the interlaced video signal, an interpolation reduction processing means for generating a new scanning line by interpolation processing and reducing a video in a vertical direction, and an interlaced video signal A field discriminating signal generating means for generating a field discriminating signal for discriminating a field from the synchronization signal, a vertical coefficient generating means for generating a different vertical coefficient for each specific field and each other field, and the vertical coefficient generating means Is selectively supplied to the interpolation reduction processing means according to the field determination signal. Characterized in that it comprises a feed means.

The supply means includes a switch circuit, and controls the switch circuit according to the field determination signal. Further, the field memory is connected to an output of the interpolation enlargement processing means. The signal processing device, further comprising: an input control unit that generates a control signal synchronized with a synchronization signal of the input video signal; and an output control unit that generates a control signal synchronized with a desired video signal. Preferably, the field control is controlled by the output control means.

In order to achieve the object of the present invention, a signal processing device according to the present invention comprises: a field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal; A signal processing device that receives an interlaced video signal and obtains a non-interlaced video signal including an interpolation reduction processing unit that creates a new scanning line by interpolation from upper and lower scanning lines and reduces the video in the vertical direction , A field discriminating means for discriminating a field from an interlaced synchronization signal, an input control means for controlling the field memory from an interlaced synchronization signal, and an output controlling means for controlling the field memory from a non-interlaced synchronization signal The interpolation reduction processing means for generating a plurality of coefficients. It consists vertical coefficient generator means for supplying, in accordance with a result from the field determination means, characterized by switching the coefficients from the vertical coefficient generator.

According to another aspect of the present invention, there is provided a signal processing apparatus for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal. Interpolation processing means for receiving interlaced video signals, creating new scanning lines from the upper and lower scanning lines by interpolation, and enlarging the image in the vertical direction, and new interpolation processing from the upper and lower scanning lines. Interpolation reduction processing means for creating a scanning line and reducing an image in the vertical direction, field determination means for determining a field from an interlaced synchronization signal, and a determination result from the field determination means converted by the field memory. The other memory for synchronizing with the vertical frequency of the signal and the interlaced synchronization signal Input control means for controlling the memory, output control means for controlling the field memory from a non-interlaced synchronization signal, first vertical coefficient generation means for generating a plurality of coefficients and supplying the coefficients to the interpolation enlargement processing means, It is characterized by comprising a second vertical coefficient generating means for generating a plurality of coefficients and supplying it to the interpolation reduction processing means.

In the signal processing device, it is preferable that the coefficient from the first vertical coefficient generating means is switched according to the result from the another memory. Further, in the signal processing device, it is preferable that a coefficient from the second vertical coefficient generating means is switched according to a result from the field determining means.

According to another aspect of the present invention, there is provided a display device for converting a vertical frequency and a horizontal frequency of an input interlaced video signal into a vertical frequency and a horizontal frequency of a desired video signal. Interpolating enlargement processing means for creating a new scanning line by interpolation processing of video signals of horizontal scanning lines above and below the interlaced video signal and enlarging the image in the vertical direction,
Means for obtaining a second field discrimination signal synchronized with the vertical frequency of the desired video signal from a first field discrimination signal synchronized with the vertical frequency of the input video signal; A vertical coefficient generating means for generating a vertical coefficient; a supply means for selectively supplying an output of the vertical coefficient generating means to the interpolation / enlargement processing means in accordance with the second field discrimination signal; and a display; The output of the processing means is supplied to the display.

In order to achieve the object of the present invention, a display device according to the present invention comprises a field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal, and an interlace. A display device that receives a video signal of a system and displays a non-interlaced video signal equipped with interpolation enlargement processing means for creating a new scanning line by interpolation from upper and lower scanning lines and enlarging the image in the vertical direction A field discriminating means for discriminating a field from an interlaced synchronizing signal; and another memory for outputting a field discriminating signal synchronized with a vertical frequency of a signal obtained by converting the discrimination result from the field discriminating means in the field memory. And control the field memory from the interlaced synchronization signal Input control means, an output control means for controlling the field memory from a non-interlaced synchronization signal, a vertical coefficient generation means for generating a plurality of coefficients and supplying to the interpolation enlargement processing means, and a display, The coefficient from the vertical coefficient generation means is switched according to the output from the other memory, and the output of the interpolation enlargement processing means is supplied to the display.

According to another aspect of the present invention, there is provided a display apparatus for converting a vertical frequency and a horizontal frequency of an input interlaced video signal into a vertical frequency and a horizontal frequency of a desired video signal. A field memory, interpolation reduction processing means for creating a new scanning line by interpolation processing of video signals of horizontal scanning lines above and below the interlaced video signal and reducing the video in the vertical direction, A field discrimination signal generating means for generating a field discrimination signal for discriminating a field from the synchronization signal; a vertical coefficient generation means for generating a different vertical coefficient for each specific field and each other field; A supply for selectively supplying an output to the interpolation reduction processing means in accordance with the field determination signal Comprising a stage, a display, and supplying the output of said field memory to the display.

In order to achieve the object of the present invention, a display device according to the present invention comprises a field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal; Display device that receives a video signal of a non-interlaced system, and includes an interpolation reduction processing means for reducing a video in a vertical direction by creating a new scanning line by interpolation processing from upper and lower scanning lines. A field discriminating unit that discriminates a field from an interlaced synchronization signal, an input control unit that controls the field memory from an interlaced synchronization signal, and an output control unit that controls the field memory from a non-interlaced synchronization signal. Generates a plurality of coefficients and supplies them to the interpolation reduction processing means. A vertical coefficient generating means, and a display, wherein a coefficient from the vertical coefficient generating means is switched according to a result from the field discriminating means, and an output of the field memory is displayed on the display. And

According to another aspect of the present invention, there is provided a display device comprising: a field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal; , Receiving an interlaced video signal, creating a new scanning line by interpolation from upper and lower scanning lines and enlarging the image in the vertical direction, and performing new scanning by interpolation from upper and lower scanning lines. Interpolation reduction processing means for creating a line to reduce an image in the vertical direction, field determination means for determining a field from an interlaced synchronization signal, and a signal obtained by converting the determination result from the field determination means in the field memory Field memory from another memory that synchronizes with the vertical frequency of the Input control means for controlling the field memory from a non-interlaced synchronization signal; first vertical coefficient generating means for generating a plurality of coefficients and supplying the coefficients to the interpolation enlargement processing means; A second vertical coefficient generating means for generating and supplying the coefficient to the interpolation reduction processing means, and a display, wherein an output of the interpolation enlargement processing means is displayed on the display.

[0025]

Embodiments of the present invention will be described below with reference to the drawings using some examples.
FIG. 1 is a block diagram showing one embodiment of a signal processing device according to the present invention. In this embodiment, a case where the number of pixels is increased will be described. Note that blocks having the same functions in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, 21 is a field discriminating circuit,
Reference numeral 22 denotes a memory, and reference numeral 25 denotes a vertical filter coefficient generation circuit corresponding to a field. The vertical filter coefficient generation circuit 25 includes a switch circuit 23 and vertical filter coefficient generation circuits 24 and 6. A terminal (7) is connected to a display (not shown), and a terminal 4 is supplied with a horizontal synchronizing signal HB and a vertical synchronizing signal VB of the display.

In FIG. 1, a field discriminating circuit 21 discriminates a field from a horizontal synchronizing signal HA and a vertical synchronizing signal VA of a video signal A from an input terminal 2 and supplies a field discriminating signal Fac to the memory 22. . Since the field discrimination circuit 21 is a known technique, detailed description will be omitted. The memory 22 is a field memory 1
In the same manner as in 1, the video signal B is written by the write control signal synchronized with the vertical frequency from the input control circuit 3 and read out by the read control signal synchronized with the vertical frequency of the video signal B from the output control circuit 5, thereby synchronizing with the video signal B. The generated field discrimination signal Faw is supplied to the switch circuit 23 in the vertical filter coefficient generation circuit 25 corresponding to the field.

The relationship between the vertical frequency conversion in the field memory 11 and the field discrimination signal will now be described with reference to FIGS.
This will be described with reference to FIG. 3A and 3B are schematic diagrams for explaining the conversion of the vertical frequency. FIG. 3A is a synchronization timing diagram of the vertical synchronization signal VA of the video signal A, and FIG. 3B is a schematic diagram of the video signal A. 3 (c) is a waveform diagram of the field determination signal Fac, FIG. 3 (d) is a synchronization timing diagram of the vertical synchronization signal VB of the video signal B, and FIG.
FIG. 3F is a schematic diagram of the video signal B.

In this embodiment, the vertical frequency is 60 Hz.
The relationship between the field discrimination signals Fac and Faw in the case where the video signal A is converted into a video signal B having a vertical frequency of 80 Hz will be described. In FIG. 3, the video signal A shown in FIG. 3B input from the terminal 1 is converted into a field memory by a write control signal synchronized with the vertical synchronization signal VA shown in FIG. 3 and a read control signal from the output control circuit 5 synchronized with the vertical synchronizing signal VB shown in FIG.
The vertical frequency is converted by reading the video signal B shown in (f) from the field memory 11. The conversion from the video signal A with the vertical frequency of 60 Hz to the video signal B with the vertical frequency of 80 Hz is performed by creating the video signal B for four fields from the video signal A for three fields. More specifically, the first field of the video signal A shown in FIG. 3A (O: Odd (ODD) field)
-2nd field (E: means even field (EVEN) field)-3 fields of 3rd field (O)
First field (O)-of video signal B shown in FIG.
By reading the second field (E) -the third field (O) -the third field (O), the video signal A for three fields is converted into the video signal B for four fields.

At the same time as this processing, a field discrimination signal Fac obtained by discriminating a field from the horizontal synchronization signal HA and the vertical synchronization signal VA of the video signal A is supplied to the memory 22.
A field discrimination signal Faw synchronized with the video signal B is created by writing in the memory 22 with a write control signal from the input control circuit 3 and reading from the memory 22 with a read control signal from the output control circuit 5. FIG. 3C shows the field discrimination signal Fac written to the memory 22, and FIG. 3E shows the field discrimination signal Faw read from the memory 22. As is clear from FIG.
The field discrimination signal Fac is read twice to form the field discrimination signal Faw shown in FIG. Thereby, the video signal B and the field discrimination signal Faw can be matched.

Next, the conversion of the video signal and the conversion of the field discrimination signal when the video signal A having a vertical frequency of 80 Hz is converted into the video signal B having a vertical frequency of 60 Hz will be described. FIG. 4 is a schematic diagram for explaining the conversion of the vertical frequency. FIG. 4A shows the vertical synchronization signal V of the video signal A.
FIG. 4B is a schematic diagram of the video signal A, FIG. 4C is a waveform diagram of the field determination signal Fac,
4D is a synchronization timing chart of the vertical synchronization signal VB of the video signal B, FIG. 4E is a waveform chart of the field discrimination signal Faw, and FIG. 4F is a schematic diagram of the video signal B.

In the figure, in order to convert a video signal A having a vertical frequency of 80 Hz to a video signal B having a vertical frequency of 60 Hz, a video signal B for three fields is created from a video signal A for four fields. Specifically, the first field (O) -second field (E) -third field (O) -fourth field (E) of the video signal A shown in FIG.
The fourth field is not read out of the four fields of
Alternatively, the writing is not performed, and the first field (O) -the second field (E) of the video signal B from other fields
-The video signal A for four fields is converted into the video signal B for three fields by reading out the third field (O).

In this case, the video signal B and the field discrimination signal Faw can be matched by the same operation as that described with reference to FIGS. That is, a field discrimination signal Fac (FIG. 4C) obtained by discriminating a field from the horizontal synchronization signal HA and the vertical synchronization signal VA of the video signal A is supplied to the memory 22, and the write control signal from the input control circuit 3 is supplied. 4, a field discrimination signal Faw (FIG. 4) synchronized with the video signal B by reading from the memory 22 with a read control signal from the output control circuit 5.
(E)) can be created. Therefore, as described with reference to FIGS. 3 and 4, in the embodiment shown in FIG. 1, the video signal B after the vertical frequency conversion and the field discrimination signal Faw are used regardless of whether the vertical frequency of the video signal A is increased or decreased.
And can be matched.

Next, the operation of the vertical filter coefficient generator 25 corresponding to the field will be described with reference to FIG. The vertical filter coefficient Mo from the vertical filter coefficient generator 6 and the vertical filter coefficient Me from the vertical filter coefficient generator 24 are supplied to the switch circuit 23 of the field corresponding vertical filter coefficient generator 25, and the field discrimination signal Fa
w, vertical filter coefficients (Mo, No), (Me,
Me) is switched and supplied to the vertical filter circuit 12.

Here, how to apply the vertical filter coefficient to the vertical filter circuit 12 will be described with reference to FIG. FIG. 5 is a schematic diagram for explaining the conversion of scanning lines when switching from the interlace method to the non-interlace method. FIG. 5A is a schematic diagram illustrating an interlaced horizontal scanning line, and FIG. 5B is a schematic diagram illustrating a non-interlaced horizontal scanning line. In FIG. 5A, 1o to 6o drawn by solid lines indicate predetermined fields of the video signal A, for example, odd fields, and 1o drawn by dotted lines.
o to 6o indicate other fields, for example, even fields.

FIG. 5 shows the scanning line positions when the video signal is enlarged 6/5 times in the vertical direction. When an input signal as shown in FIG. Then, for example, the first scanning line 1o is multiplied by 1/6,
The second scanning line 2o is multiplied by 5/6 and added to form a scanning line 2n as shown in FIG. 5B.
Similarly, 2/6 times the second scanning line 2o, 4/6 times the third scanning line 3o, 3/6 times the third scanning line 3o, and 3/6 times the fourth scanning line 4o. Times the fourth scanning line 4o
4/6 times, 2/6 times of the fifth scanning line 5o, 5/6 times of the 5th scanning line 5o, and 1/6 of the 6th scanning line 6o.
0/6 times the fifth scanning line 5o and the sixth scanning line 6
6/6 times o,...
, 4n, 5n, 6n, 7n,... are formed.

In other fields, for example, FIG.
The first scanning line 1e of FIG.
The second scanning line 2e in (b) is multiplied by 2/6 and added to each other to form a scanning line 2n as shown in FIG. 5 (b). Similarly, 5/6 times the second scanning line 2e, 1/6 times the third scanning line 3e, 0/6 times the second scanning line 2e, and 6/6 times the third scanning line 3e. 、 ４ times the fourth scanning line 4e and ／ times the fifth scanning line 5e,
2/6 times the fifth scanning line 5e, 4/6 times the sixth scanning line 6e, 3/6 times the fifth scanning line 5e, 3/6 times the sixth scanning line 6e,... Are sequentially added to form scanning lines 3n, 4n, 5n, 6n, 7n,... Sequentially. Therefore, the cycle of the interlaced scanning line is 1o to 5o.
Alternatively, there are five lines 1e to 5e, and the period of the sequential scanning line is six lines 1n to 6n.
That is a factor of five.

Here, an interpolation coefficient (Mo, No) given to two scanning lines on a predetermined field side for forming an interpolation scanning line corresponding to the above-mentioned sequential scanning line, and an interpolation coefficient on another field side are (Mo, No). Me, Ne). However, Mo,
Me represents the interpolation coefficient of the upper scanning line of the two scanning lines forming the interpolation scanning line, and No and Ne represent the interpolation coefficients of the lower scanning line of the two scanning lines.

As shown in FIG. 5, in order to realize the 6/5 magnification, interpolation coefficients (Mo, N) given to each scanning line of a predetermined field are used.
o) is (0, 1), (1/6, 5/6), (2/6,
4/6), (3/6, 3/6), (4/6, 2/6),
The sequence (5/6, 1/6) may be repeated.

If the input signal is non-interlaced, the same interpolation coefficient sequence may be given to other fields. However, if the input signal is interlaced, the center of gravity of the scanning line is shifted in other fields. Line flicker and the like occur. In FIG. 5, in order to solve this problem, the interpolation coefficient series (Me, N
e) are (3/6, 3/6), (4/6, 2/6), (5
/ 6, 1/6), (0, 1), (1/6, 5/6),
(2/6, 4/6). Here, from FIG. 5, while the interpolated scanning lines are at the same position regardless of the field, the difference between the position of the scanning line of the predetermined field and the position of the scanning line of the other field is １ ／. Circuit 24
Of the coefficient generated by the coefficient generation circuit 6 is 1 /
When two offsets are performed, the position of the center of gravity of the scanning line in the field coincides with the position of the scanning line in the non-interlaced system, which is optimal. Mo + No and Me + Ne are both 1.

Here, for example, the interpolation scanning line 5n is formed by a scanning line 4o immediately above the interpolation scanning line 5n and a scanning line 5o immediately below this scanning line 4n in a predetermined field, and interpolation scanning in another field. It is created from the scanning line 3e immediately above the line 5n and the scanning line 4e immediately below this scanning line 3e. Thus, the interpolated scan line is created from the scan line one above and one scan line below this interpolated scan line, regardless of the field. Therefore, when creating the (n + 1) th interpolation scan line, the interpolation coefficients Mo, No, M
e and Ne are the magnification of W times (W ≧ 1) and the M of the nth line
If the difference between o and Mo on the (n + 1) th line is S (0 ≦ S <1), then S = 1−1 / W Mo = nS− [nS] No = 1−Mo Me = Mo +／− 2− [Mo + 1 / 2] Ne = 1-Me (where 0 ≦ Mo, Me <1, 0 <No, Ne ≦ 1) (where [nS] and [Mo + 1/2] are nS,
Mo + 1/2).
With the interpolation coefficient sequence thus obtained, it is possible to create a scanning line that is optimal for the non-interlace method, regardless of whether the video signal is an odd field or an even field.

Here, the coefficient generating circuit 6 shown in FIG.
Then, a vertical filter coefficient Me of another field is generated. In the switch circuit 23, the field discrimination signal Faw
However, if the signal indicates a predetermined field, the terminal a is selected, and the coefficient (Mo, No) from the coefficient generation circuit 6 is selected. If the signal indicates another field, the terminal b is selected and the terminal b is selected. Are output to the vertical filter circuit 12.

The vertical filter circuit 12 performs vertical filter processing in accordance with the coefficient selected by the switch circuit 23, and then supplies the result to the output terminal 7. The video signal B taken out to the output terminal 7 is displayed on a display (not shown) connected to the terminal 7.

As described above, according to the present embodiment, when an interlaced video signal is enlarged and displayed in a non-interlaced format, an interpolation coefficient sequence that does not cause a shift in the center of gravity of a scanning line due to a field is provided. , And can supply a high-quality enlarged image.

Hereinafter, an embodiment in which the number of pixels is reduced will be described with reference to FIG. FIG. 6 is a block diagram showing another embodiment of the signal processing device according to the present invention. In the figure, the vertical filter circuit 12 and the field-specific vertical filter coefficient generation circuit 25 of FIG. 1 are arranged at the previous stage of the field memory 11 and are processed here. As a result, the number of lines can be reduced in the field memory 11 after the vertical filter processing in the circuit 12 to reduce the number of lines. In the figure, vertical filter coefficient generating circuits 6 and 2 in a field corresponding vertical filter coefficient generating circuit 25 are shown.
4 is supplied with a horizontal synchronizing signal HA and a vertical synchronizing signal VA to synchronize with the video signal A.

On the other hand, the field discrimination signal Fac from the field discrimination circuit 21 is supplied to the switch circuit 23 in the field corresponding vertical filter coefficient generation circuit 25.
The vertical filter coefficient (Mo, Mo) output from the vertical filter coefficient generation circuit 6 according to the determination signal Fac.
And the vertical filter coefficient (Me, Ne) output from the vertical filter coefficient generation circuit 24 and supplied to the vertical filter circuit 12. After the vertical filter processing in the vertical filter circuit 12, the frequency conversion and the number of pixels are reduced in the field memory 11. The relationship between the vertical frequency conversion in the field memory 11 and the field discrimination signal Fac is
This is the same as that shown in FIGS. 3 and 4 except that the field discrimination signal Faw is deleted.

Next, how to give coefficients to the vertical filter circuit 12 will be described with reference to FIG. FIG. 7 is a schematic diagram for explaining the conversion of scanning lines when switching from the interlace method to the non-interlace method. FIG. 7A is a schematic diagram showing an interlaced horizontal scanning line.
(B) is a schematic diagram showing a non-interlaced horizontal scanning line. It should be noted that FIG. 3 shows the scanning line positions when the video signal is reduced by a factor of 5/6 in the vertical direction.

In the same manner as in FIG. 5, a period of 5 lines of scanning lines 1n to 5n is formed sequentially from 6 lines of interlaced scanning lines 1o to 6o or 1e to 6e, and the video signal is multiplied by 5/6. As shown in FIG. 7, in order to realize 5/6 times, an interpolation coefficient (M
o, No) are (1, 0), (4/5, 1/5), (3
/ 5, 2/5), (2/5, 3/5), (1/5, 4 /
5), interpolation coefficient series of other fields (Me, Ne)
Are (5/10, 5/10), (3/10, 7/1)
0), (1/10, 9/10), (9/10, 1/1)
0), (7/10, 3/10).

In the case of forming the (n + 1) th interpolation scanning line in the same manner as in FIG. 5, the interpolation coefficients Mo, No, M
e and Ne are the magnification of W times (W ≦ 1), M of the nth line
If the difference between o and Mo on the (n + 1) th line is S (0 ≦ S <1), then S = 1 / W−1 Mo = 1−No No = nS− [nS] Me = 1−Ne Ne = No + 1 / 2- [No + 1/2] (where 0 <Mo, Me ≦ 1, 0 ≦ No, Ne <1) (where [nS] and [No + 1/2] are nS,
No represents the largest integer not exceeding +＋ １. ).
The interpolation coefficient series thus obtained is the same as the interpolation coefficient series in FIG. 3 in which Mo and No and Me and Ne are interchanged. Therefore, the vertical filter circuit 12 shown in FIG. 6 has Mo and No and Me and Ne compared to the embodiment of FIG.
The coefficient is replaced. Thereby, the video signal A
In either field, a scanning line optimal for the non-interlace method can be created.

Here, in the switch circuit 23 of FIG. 6, when the field discrimination signal Fac is a signal indicating a predetermined field, the terminal a is selected and the coefficients (No, Mo) from the coefficient generation circuit 6 are output. In the case of a signal indicating another field, the terminal b is selected and the coefficient (N
e, Me) to the vertical filter circuit 12. The vertical filter circuit 12 performs vertical filter processing in accordance with the coefficient selected by the switch circuit 23, supplies the result to the output terminal 7, and outputs it to a display (not shown) connected to the terminal 7.

As described above, according to the present embodiment, when an interlaced video signal is reduced and further displayed in a non-interlaced format, an interpolation coefficient sequence that does not cause a shift in the center of gravity of a scanning line due to a field is provided. Therefore, a high-quality reduced image can be supplied.

Next, an embodiment for enlarging and reducing the number of pixels will be described with reference to FIG. FIG. 8 is a block diagram showing still another embodiment of the signal processing device according to the present invention.

In the figure, 31 is a switch circuit, 3
Reference numerals 2 and 33 denote vertical filter coefficient generation circuits, 34 denotes a field-dependent vertical filter coefficient generation circuit, and 35 denotes a vertical filter circuit. The other blocks have the same functions as the blocks shown in FIG. 6, and thus the same reference numerals are given and the description thereof will be omitted.

The switch circuit 31 of FIG. 8 has the same function as the switch circuit 23 of FIG. 1, and the vertical filter coefficient generation circuits 32 and 33 of FIG. 8 have the same functions as the vertical filter coefficient generation circuits 6 and 24 of FIG. The field corresponding vertical filter coefficient generation circuit 34 of FIG. 8 has the same function as the field corresponding vertical filter coefficient generation circuit 25 of FIG. 1, and the vertical filter circuit 35 of FIG.
By performing the processing with the same function as that of the second embodiment, the horizontal scanning line can be enlarged.

The switch circuit 23, the vertical filter coefficient generators 6 and 24, the field-dependent vertical filter coefficient generator 25, and the vertical filter circuit 12 shown in FIG. Horizontal scanning line reduction processing can be performed. In this way, by switching the interpolation coefficient with an offset for each field, the interlace video signal is enlarged or reduced, and the horizontal frequency and the vertical frequency are converted and displayed in a non-interlaced manner. Irrespective of this, since a scanning line at a correct center of gravity can be secured, a high-quality image can be supplied.

[0055]

According to the present invention, when non-interlaced display is performed while enlarging or reducing an interlaced video signal and converting horizontal and vertical frequencies, there is no deterioration in image quality due to displacement of the center of gravity of scanning lines. High-quality video signals can be realized with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a signal processing device according to the present invention.

FIG. 2 is a block diagram of a signal processing apparatus that performs conversion of a horizontal frequency and a vertical frequency and conversion of the number of pixels according to the related art.

FIG. 3 is a schematic diagram for explaining vertical frequency conversion.

FIG. 4 is a schematic diagram for explaining vertical frequency conversion.

FIG. 5 is a schematic diagram for explaining scanning line conversion when switching from an interlace method to a non-interlace method.

FIG. 6 is a block diagram showing another embodiment of the signal processing device according to the present invention.

FIG. 7 is a schematic diagram for explaining scanning line conversion when switching from an interlace method to a non-interlace method.

FIG. 8 is a block diagram showing still another embodiment of the signal processing device according to the present invention.

[Explanation of symbols]

3: Input control circuit, 5: Output control circuit, 6, 24, 3
2, 33: coefficient generation circuit, 11: field memory, 1
2, 35 vertical filter circuit, 21 field discriminating circuit, 22 memory, 23, 31 switch circuit, 25,
34 ... vertical filter coefficient generation circuit corresponding to the field.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ryo Hasegawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Visual Information Media Division of Hitachi, Ltd. (72) Haruki Takada Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi Image and Media Division, Hitachi, Ltd. (72) Inventor Katsunobu Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd.Image and Media Division of Hitachi, Ltd. (72) Inventor Tatsuo Nagata Kanagawa 292 Yoshida-cho, Totsuka-ku, Yokohama F-term (reference) of Hitachi, Ltd. Video Information Media Division 5C058 BA17 BB13 BB15 BB16 BB18 BB23 BB25 5C063 AA07 BA04 BA09 CA01 CA05 EB46 5C082 AA01 AA02 BA12 BA41 BB15 BB25 BC05 BC32 CA84 DA55 DA56 DA61 MM10

Claims (20)

[Claims] 1. A field memory for converting a vertical frequency and a horizontal frequency of an input interlaced video signal to a vertical frequency and a horizontal frequency of a desired video signal, and a horizontal scanning line above and below the interlaced video signal. Interpolating and enlarging processing means for generating a new scanning line by interpolating the video signal and enlarging the video in the vertical direction; and obtaining the desired video signal from the first field determination signal synchronized with the vertical frequency of the input video signal. Means for obtaining a second field discrimination signal synchronized with the vertical frequency; vertical coefficient generating means for generating a different vertical coefficient for each specific field and other fields; and outputting the output of the vertical coefficient generating means to the second field. Supply means for selectively supplying the interpolation enlargement processing means with a field discrimination signal. . 2. A signal processing apparatus according to claim 1, wherein said means for obtaining said second field discrimination signal comprises: a memory;
Means for writing the first field discrimination signal into the memory in synchronization with the vertical frequency of the input video signal; and outputting a second field discrimination signal from the memory in synchronization with the vertical frequency of the desired video signal. A signal processing device comprising: a reading unit. 3. A signal processing apparatus according to claim 1, wherein said vertical coefficient generating means includes a first vertical filter coefficient generating circuit applied to a specific field of said second field discriminating signal; And a second vertical filter coefficient generation circuit to which another field of the field discrimination signal is applied. 4. The signal processing apparatus according to claim 1, wherein said supply means includes a switch circuit, and controls said switch circuit by said second field discrimination signal. 5. A signal processing apparatus according to claim 1, wherein said interpolation and enlargement processing means is connected to an output of said field memory. 6. A signal processing apparatus according to claim 1, wherein input control means for generating a control signal synchronized with a synchronization signal of the input video signal, and output control for generating a control signal synchronized with a desired video signal. Means for controlling the field memory by the input control means and the output control means. 7. A field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal, an interlaced video signal being received, and interpolation processing from upper and lower scanning lines. A signal processing device for obtaining a non-interlaced video signal having an interpolation / enlargement processing means for creating a new scanning line and enlarging an image in a vertical direction by using a field discriminating means for discriminating a field from an interlaced synchronizing signal; Another memory for outputting a field discrimination signal synchronized with a vertical frequency of a signal obtained by converting the discrimination result from the field discrimination means in the field memory, and an input for controlling the field memory from an interlaced synchronization signal. Before the control means and the non-interlaced synchronization signal Output control means for controlling the field memory, and vertical coefficient generating means for generating a plurality of coefficients and supplying the generated coefficients to the interpolation enlargement processing means, wherein the vertical coefficient generating means corresponds to an output from the other memory. A signal processing device characterized by switching a coefficient from a signal. 8. A field memory for converting a vertical frequency and a horizontal frequency of an input interlaced video signal into a vertical frequency and a horizontal frequency of a desired video signal; Interpolation reduction processing means for generating a new scanning line by interpolation processing of a video signal to reduce a video in the vertical direction, and field determination for generating a field determination signal for determining a field from a synchronization signal of an interlace video signal A signal generation unit, a vertical coefficient generation unit that generates a different vertical coefficient for each specific field and another field, and an output of the vertical coefficient generation unit selectively supplied to the interpolation reduction processing unit according to the field determination signal. A signal processing device comprising: 9. A signal processing apparatus according to claim 8, wherein said supply means includes a switch circuit, and controls said switch circuit by said field discrimination signal. 10. The signal processing device according to claim 8,
The signal processing device according to claim 1, wherein said field memory is connected to an output of said interpolation reduction processing means. 11. The signal processing device according to claim 8, wherein
Input control means for generating a control signal synchronized with a synchronization signal of the input video signal, and output control means for generating a control signal synchronized with a desired video signal, wherein the input control means and the output control means A signal processing device for controlling the field memory. 12. A field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal, and receiving an interlaced video signal and performing interpolation processing from upper and lower scanning lines. A signal processing device for obtaining a non-interlaced video signal having an interpolation reduction processing unit for reducing a video in a vertical direction by creating a new scanning line by using a field determination unit for determining a field from an interlace synchronization signal; Input control means for controlling the field memory from an interlaced synchronization signal, output control means for controlling the field memory from a non-interlaced synchronization signal, and a plurality of coefficients generated and supplied to the interpolation reduction processing means The field discriminating means comprises vertical coefficient generating means. A signal processing apparatus, wherein a coefficient from the vertical coefficient generating means is switched according to a result from a stage. 13. A field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal, and receiving an interlaced video signal, and performing interpolation processing from upper and lower scanning lines. Interpolation enlargement processing means for creating a new scanning line to enlarge the image in the vertical direction, and interpolation reduction processing means for creating a new scanning line by interpolation processing from the upper and lower scanning lines and reducing the image in the vertical direction. A field discriminating means for discriminating a field from an interlaced synchronizing signal, another memory for synchronizing a discrimination result from the field discriminating means with a vertical frequency of a signal converted by the field memory, and an interlaced synchronizing signal. An input control means for controlling the field memory and a non-interlaced synchronization signal; Output control means for controlling the field memory, first vertical coefficient generation means for generating a plurality of coefficients and supplying the results to the interpolation enlargement processing means, and second output means for generating a plurality of coefficients and supplying the results to the interpolation reduction processing means A signal processing device comprising: a vertical coefficient generating means. 14. A signal processing apparatus according to claim 13, wherein a coefficient from said first vertical coefficient generating means is switched according to a result from said another memory. 15. A signal processing apparatus according to claim 13, wherein a coefficient from said second vertical coefficient generating means is switched according to a result from said field discriminating means. 16. A field memory for converting a vertical frequency and a horizontal frequency of an input interlaced video signal into a vertical frequency and a horizontal frequency of a desired video signal.
The interpolation and enlargement processing means for creating a new scanning line by interpolating the video signal of the upper and lower horizontal scanning lines of the interlaced video signal and enlarging the video in the vertical direction, and synchronized with the vertical frequency of the input video signal Means for obtaining a second field discrimination signal synchronized with the vertical frequency of the desired video signal from the first field discrimination signal; vertical coefficient generation means for generating a different vertical coefficient for each specific field and each other field; Supply means for selectively supplying the output of the vertical coefficient generation means to the interpolation enlargement processing means in accordance with the second field discrimination signal, and a display, and supplies the output of the interpolation enlargement processing means to the display. A display device characterized by the above-mentioned. 17. A field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal, and receiving an interlaced video signal, and performing interpolation processing from upper and lower scanning lines. A display device for displaying a non-interlaced video signal provided with an interpolation enlargement processing unit for creating a new scanning line and enlarging an image in the vertical direction by a field discriminating unit for discriminating a field from an interlaced synchronization signal; Another memory for outputting a field discrimination signal synchronized with a vertical frequency of a signal obtained by converting the discrimination result from the field discrimination means in the field memory, and an input for controlling the field memory from an interlaced synchronization signal. Control means and non-interlaced synchronization signal Output control means for controlling the field memory, vertical coefficient generating means for generating a plurality of coefficients and supplying the coefficients to the interpolation enlargement processing means, and a display, and according to an output from the other memory, the vertical A display device for switching a coefficient from a coefficient generation unit and supplying an output of the interpolation enlargement processing unit to the display. 18. A field memory for converting a vertical frequency and a horizontal frequency of an input interlaced video signal into a vertical frequency and a horizontal frequency of a desired video signal.
Interpolation reduction processing means for creating new scanning lines by interpolation processing of video signals of upper and lower horizontal scanning lines of the interlaced video signal to reduce video in the vertical direction, and a field from a synchronizing signal of the interlaced video signal. A field discrimination signal generating means for generating a field discrimination signal for discriminating a field, a vertical coefficient generation means for generating a different vertical coefficient for each specific field and each other field, and an output of the vertical coefficient generation means for the field. A signal processing apparatus comprising: a supply unit that selectively supplies the interpolation reduction processing unit with a determination signal according to a determination signal; and a display, wherein an output of the field memory is supplied to the display. 19. A field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal, and receiving an interlaced video signal, and performing interpolation processing from upper and lower scanning lines. A display device for displaying a non-interlaced video signal comprising an interpolation reduction processing unit for reducing a video in a vertical direction by creating a new scanning line by: a field determination unit for determining a field from an interlace synchronization signal; Input control means for controlling the field memory from an interlaced synchronization signal, output control means for controlling the field memory from a non-interlaced synchronization signal, and a plurality of coefficients generated and supplied to the interpolation reduction processing means A vertical coefficient generating means and a display. A display device, wherein a coefficient from the vertical coefficient generating means is switched according to a result from the field discriminating means, and an output of the field memory is displayed on the display. 20. A field memory for converting a vertical frequency and a horizontal frequency of an input video signal into a vertical frequency and a horizontal frequency of a desired video signal, and receiving an interlaced video signal and performing interpolation processing from upper and lower scanning lines. Interpolation enlargement processing means for creating a new scanning line to enlarge the image in the vertical direction, and interpolation reduction processing means for creating a new scanning line by interpolation processing from the upper and lower scanning lines and reducing the image in the vertical direction. A field discriminating means for discriminating a field from an interlaced synchronizing signal, another memory for synchronizing a discrimination result from the field discriminating means with a vertical frequency of a signal converted by the field memory, and an interlaced synchronizing signal. An input control means for controlling the field memory and a non-interlaced synchronization signal; Output control means for controlling the field memory, first vertical coefficient generation means for generating a plurality of coefficients and supplying the results to the interpolation enlargement processing means, and second output means for generating a plurality of coefficients and supplying the results to the interpolation reduction processing means A display device comprising: a vertical coefficient generating means; and a display, wherein an output of the interpolation enlarging processing means is displayed on the display.