JP3083044B2 - Video composition circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video synthesizing circuit for synthesizing a non-interlaced video signal of a personal computer or the like with an interlaced video signal of a television or the like.

[0002]

2. Description of the Related Art Conventionally, a video signal of a personal computer is, for example,
According to the VGA (Video Graphics Array) standard, non-interlaced scanning is performed at a horizontal scanning frequency of 32 kHz. The horizontal scanning frequency of TV images etc. is 15.75
When a part of a kHz interlaced video signal is captured to generate and display a composite image, there is a problem that an unsightly flicker due to flicker or the like occurs in the captured screen portion. As a method of solving this problem, for example,
63-69385 ", which describes a method of converting an interlaced video signal into a non-interlaced video signal and then synthesizing the converted signal as a main technique.

FIG. 3 is a block diagram of a video synthesizing circuit for converting a general interlaced video signal into a non-interlaced video signal and synthesizing it. Reference numeral 1 denotes an input of an interlaced video signal such as a TV video signal. And
A synchronization unit that reads the synchronization of the interlaced video signal in phase with the synchronization signal of a non-interlaced video signal of, for example, a personal computer. Reference numeral 2 denotes a non-interlaced scan of the interlaced video signal supplied by the synchronization unit 1. Reference numeral 3 denotes a synchronization detection unit which receives a non-interlaced video signal from the personal computer or the like, detects a synchronization signal, and supplies a synchronization signal to the synchronization unit 1. Reference numeral 13 denotes a double speed conversion unit. A switching unit that switches between a non-interlaced video signal output from the conversion unit 2 and a non-interlaced video signal from the personal computer or the like based on a synthesis control signal supplied from another unit, and includes the above-described components.

[0004] The operation of the above-described general video synthesizing circuit will be described with reference to FIGS. 4 and 5. A non-interlaced video signal of a personal computer or the like and a video signal of a television or the like generally have an unrelated and asynchronous relationship with each other. Therefore, FIG.
As shown in (1), the synchronization unit 1 reads the synchronization of the input interlaced video signal of the television or the like based on the synchronization signal of the non-interlaced video signal of the personal computer or the like detected by the synchronization detection unit 3, and detects a predetermined phase difference. Synchronous conversion and output.

However, video signals from a personal computer or the like are not shown in FIG.
5A is a non-interlaced scan, and a video signal from a television or the like is the interlaced scan shown in FIG. This interlaced scanning is performed by the double speed conversion unit 2
When converted to non-interlaced scanning, the odd fields shown in (c) of FIG. 5 are added with newly generated scanning lines (marked with o in the figure) as shown in (d) of FIG. In the scanning state, the even-numbered field shown in FIG. 5E becomes a scanning state to which a newly generated scanning line (marked with a circle in FIG. 5) is added, as shown in FIG. That is,
When comparing (d) and (f) in FIG. 5 described above, a difference corresponding to one scanning line occurs, and these images are displayed on a personal computer or the like shown in (a) in FIG. When combined with a video signal, a phenomenon occurs in which scanning lines of the same pattern are displayed above and below by one scanning line for each of the odd and even fields. Therefore, in the prior art, the flicker problem remains in the synthesized display image.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a video synthesizing circuit capable of obtaining a high-quality synthetic image with a simple circuit.

[0007]

In order to achieve the above-mentioned object, there is provided a synchronizing method for synchronizing an input interlaced video signal so as to have a predetermined phase difference from a phase of a synchronizing signal of a non-interlaced video signal as a reference. Unit, a double-speed conversion unit that converts the interlaced video signal output by the synchronization unit to a non-interlace signal, detects a synchronization signal of the input non-interlace video signal as a reference, and transmits the synchronization signal to the synchronization unit. A synchronization detection unit to be supplied; an even / odd determination unit that determines whether an interlace video signal output by the synchronization unit is an even field or an odd field; and a non-interlace video signal output by the double speed conversion unit for a predetermined horizontal scanning period. A delay unit for delaying, a non-interlaced video signal from the delay unit, and the double speed conversion unit. Enter a non-interlaced video signal force, the discrimination result of the even-odd discrimination portion formed of a switching unit for selecting and outputting one.

[0008]

[Operation] With the above configuration, the synchronization unit
The input interlaced video signal is read out and output, for example, one horizontal scanning period earlier than the reference non-interlaced video signal, and, as shown in FIG. The non-interlaced video signal converted from the odd field is selectively output from the non-interlaced video signal delayed by one horizontal scanning period, and the non-interlaced video signal converted from the even field is left as it is. Is selected and output.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video synthesizing circuit according to the present invention will be described.
This will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a video synthesizing circuit according to the present invention. Reference numeral 1 denotes a synchronization unit configured to read out an input interlaced video signal of a television or the like based on a phase of a synchronization signal of a non-interlaced video signal of a personal computer or the like as a reference and perform synchronization, for example, configured by a field memory. Reference numeral 2 denotes a double speed conversion unit configured to convert the interlace video signal output from the synchronization unit 1 into a non-interlace signal, for example, a line memory. Reference numeral 3 denotes a synchronization detection unit that detects a synchronization signal of the input non-interlace video signal serving as a reference and supplies the synchronization signal to the synchronization unit 1. Reference numeral 4 indicates whether the interlaced video signal output from the synchronization unit 1 is an even field or an odd field, for example, by specifying specific data indicating an odd field on a first horizontal scanning line constituting a frame of a video signal of a television or the like in advance. An even / odd determination unit that superimposes the data and determines whether the field is even or odd by determining the data. Reference numeral 5 denotes a delay unit configured to delay the non-interlaced video signal output from the double-speed conversion unit 2 by a predetermined horizontal scanning period, for example, a line memory. 6 receives the non-interlaced video signal from the delay unit 5 and the non-interlaced video signal output from the double speed conversion unit 2 and selects and outputs one based on the determination result of the even / odd determination unit 4. This is the first switching unit. Reference numeral 7 denotes a second switching unit that switches between the non-interlaced video signal output from the first switching unit 6 and the reference non-interlaced video signal based on a synthesis control signal supplied from another unit and outputs the same.

The operation of the video synthesizing circuit according to the present invention is shown in FIG.
This will be described with reference to FIG. The interlaced video signal supplied to the field memory constituting the synchronization unit 1 is stored in the order of scanning lines, and based on the synchronization signal of the non-interlaced video signal of the personal computer detected by the synchronization detection unit 3, the interlaced video signal is stored. The video signal is read. The double speed conversion unit 2 stores the interlaced video signal output from the synchronization unit 1 in a line memory, reads out the interlaced video signal stored in the scanning line order twice in succession once for each horizontal scanning line, and performs double speed conversion. Convert. The synchronization detection unit 3 detects a synchronization signal of a non-interlaced video signal of a personal computer or the like serving as a reference, and supplies the synchronization signal to the synchronization unit 1. The even / odd determination unit 4 determines in advance a specific data indicating an odd field which is superimposed on a first horizontal scanning line forming a frame of the video signal in an interlaced video signal of a television or the like. Is determined. The delay unit 5 sequentially stores the input video signals in a line memory, delays the input video signals by one horizontal scanning period, and sequentially outputs the delayed video signals. Based on the determination of the even / odd determination unit 4, the first switching unit 6, as shown in FIG. The non-interlaced video signal converted from the odd field is selected and output as the non-interlaced video signal delayed by one horizontal scanning period, and the non-interlaced video signal converted from the even field is output as it is. In the second switching unit 7, a non-interlaced video signal output by the first switching unit 6
A non-interlaced video signal serving as a reference is, for example,
Switching is performed based on a synthesis control signal supplied from the CPU or the like (not shown) or the like, thereby displaying the image on a window screen or the like. Note that the even / odd determining unit 4 may execute a conventional method of distinguishing between odd-numbered frames and even-numbered frames from the form of the vertical synchronization signal.

[0011]

As described above, the present invention provides a video synthesizing circuit capable of obtaining a high-quality synthetic image with a simple circuit having a minimum memory configuration using one field memory and two line memories. I do. Therefore, for example, VGA (Vi
(deo Graphics Array) When capturing an image of an interlaced video signal such as a TV image into a video signal of a personal computer such as a standard, and generating and displaying a composite image, unsightly flicker caused by flicker etc. in the captured image portion There are merits that can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a video synthesizing circuit according to the present invention.

FIG. 2 is a detailed explanatory diagram of video synthesis of the video synthesis circuit according to the present invention.

FIG. 3 is a block diagram of an embodiment of a general video synthesizing circuit.

FIG. 4 is a time chart illustrating an operation of a synchronization unit of a general video synthesizing circuit.

FIG. 5 is a screen image diagram for explaining an operation of doubling the speed of a general video synthesizing circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 synchronization unit 2 double speed conversion unit 3 synchronization detection unit 4 even / odd discrimination unit 5 delay unit 6 first switching unit 7 second switching unit 13 switching unit

Claims (1)

(57) [Claims] 1. A synchronizing unit for synchronizing an input interlaced video signal so as to have a predetermined phase difference with a phase of a synchronizing signal of a non-interlaced video signal serving as a reference, and an interlaced video output by the synchronizing unit. A double-speed conversion unit that converts the signal into a non-interlace signal, a synchronization detection unit that detects a synchronization signal of the input non-interlace video signal serving as a reference, and supplies the synchronization signal to the synchronization unit, and the synchronization unit. An even / odd determining unit that determines whether the output interlaced video signal is an even field or an odd field; a delay unit that delays the non-interlaced video signal output by the double-speed conversion unit by a predetermined horizontal scanning period; Inputs interlaced video signals and non-interlaced video signals output by the double-speed converter In the video synthesizing circuit including a switching unit that selects and outputs one according to the determination result of the even / odd determination unit, the interlaced video signal input to the synchronization unit is converted into a reference non-interlaced video signal synchronization signal. A video synthesizing circuit for performing synchronizing for reading out one horizontal scanning period earlier than the synchronizing signal, and delaying the synchronizing signal by one horizontal scanning period.