KR0132433Y1 - Writing controll device of video field memory - Google Patents

Abstract

The present invention relates to a write control device of a video field memory that is suitable for a case of controlling the image memory asynchronously, and to read and scan the data of the second field at the time of writing the data of the first field in the current field memory. When the data between the fields is changed to make the screen appear to be shaking, in the present invention, when the data for the field is asynchronously written from the field memory, the write enable signal of the logic high is applied only to the starting point of one field. One frame is used to scan the image data by writing to the other field when the data of another field is written at the time of the currently being written field. The data changes between fields Even if the screen is shaken to prevent the effect.

Description

Write Control of Video Field Memory

1 is a block diagram of a general digital image signal processing apparatus.

2 is a detailed block diagram of the memory write controller of FIG.

3 is an output waveform diagram of each part of FIG.

4 is a block diagram showing a video field memory write control device of the present invention.

5 is an output waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

261: horizontal line selector 262: field selector

263: field determination unit 264: first flip-flop

265: memory reset section 266: field selection control section

266-1: AND gate 266-2: second flip-flop

266-3: Multiplexer

The present invention relates to a field memory control device for an image memory, and more particularly, to a write control device for a video field memory suitable for a case in which the image memory is to be controlled asynchronously.

The video signal is composed of analog signals, which has had many difficulties in its application, but recently, due to the development of digital video signal processing technology, many products using the same have been released. These products convert analog signals into digital signals. Then, according to the method of processing the converted video data, various other types of products can be produced.

In addition, the general video signal has the characteristics of interlaced scanning when it is displayed on a monitor or CRT. This interlaced scanning method scans a screen of one frame into two field screens. One frame is divided into odd and even fields. Is done.

A general digital video signal processing apparatus capable of converting an analog video signal into a digital video signal and processing the same according to a desired purpose is shown in FIG. 1. As shown in FIG. 1, the input signal processing unit 100 receives an analog video signal and receives a digital signal. Signal processing is performed to facilitate conversion to a signal, which is input to the analog / digital converter 110 and converted into a digital signal by the control signal fs of the memory write controller 160. The output of the input signal processor 100 is applied to the pulse generator 150 to generate four times the clock pulse 4fsc, the horizontal synchronous signal HD, and the vertical synchronous signal VD, and apply them to the memory write controller 160. do.

The memory write controller 160 receives the outputs 4fsc, HD, and VD of the pulse generator 150 to synchronize the clock signal CLK, the write reset signal RSTW, and the write enable. By generating and outputting the signal WE, the digital image signal of the analog / digital converter 110 is stored in the field memory 120.

In addition, in order to read the image data written to the field memory 120, the output pulse generator 180 generates a clock pulse 4fsc, a horizontal synchronous signal HD, and a vertical synchronous signal VD. The memory read control unit 170 generates a clock signal CLK, a read reset signal RSTW, a write enable signal WE, and outputs the generated clock signal CLK to the field memory 120. The digital image data is read, and the read digital image data is applied to the digital / analog converter 130 and converted into an analog signal by the clock signal CLK of the clock pulse generator 180.

The video data converted into the analog signal is applied to the output signal processor 140, and is processed and output as a composite video signal by the clock synchronization signal CSync of the output pulse generator 180.

Meanwhile, as shown in FIG. 2, the memory write control unit 160 receives the horizontal synchronization signal HD of the input analog video signal and receives the memory write control signals of even and odd lines of one frame. Receives the horizontal line selection unit 161 and the vertical synchronization signal VD and the horizontal synchronization signal HD of the input analog video signal, and determines whether the first field is the second field or the second field selection signal. A field decision unit 163 for outputting a signal and a memory write control signal of the horizontal line selection unit 161 are selected to output the write enable signal WE by an output of the field decision unit 163. A field selector 162, a flip-flop 164 that receives the write enable signal WE of the field selector 162 and detects a start point thereof, and a write when an output is applied from the flip-flop 164 Reset signal (RSTW) Generated is a memory reset section 165.

This will be described in detail as follows.

The horizontal line selector 161 receives the horizontal synchronization signal HD from the pulse generator 150 and counts it to generate a memory write control signal of each line of two fields constituting one frame. Normally minus the vertical blanking period, the first field uses lines 23 through 262 and the second field uses lines 22 through 261 because the video signal is interlaced to the monitor or CRT. to be.

The field determining unit 163 receives the vertical synchronizing signal VD and the horizontal synchronizing signal HD of the video signal and generates a field selection signal as shown in FIG. 3B to the field selector 162. Will be authorized.

Therefore, the field selector 162 selects and outputs a memory write control signal of two fields output from the horizontal line selector 161 by the field selector signal of the field determiner 163. If the field select signal is logic high in the field section and the logic low in the second field section, the memory write control signal for the first field is selected to display one frame in the field memory 120 as shown in FIG. The write enable signal WE is generated so that the data of the horizontal line for the first field of the video signal can be written.

On the other hand, the write enable signal WE of the field selector 162 is applied to the flip-flop 164 to detect a starting point for writing data to the field memory 120, as shown in FIG. As shown, when the write enable signal WE goes to the logic high state for the first time, its output also becomes the logic high state, at the end of the first field it receives the vertical synchronization signal VD, resets it, and then the second When the field is first started, it goes back to logic high to detect the starting point for writing the data in the two fields.

The memory reset unit 165 receives the output of the flip-flop 164 to generate a reset signal for every field as shown in FIG. 3d to reset the field memory 120.

In this case, however, if the input video signal and the output video signal are synchronized, the screen is not affected. However, in the case of asynchronous operation, data between fields of one frame is changed with time. Done.

That is, when the data of the second field is read and scanned at the time of writing the data of the first field in the current field memory, the data between the fields is changed so that the screen appears to be shaking.

Accordingly, in view of the above-described problems, the present invention applies a write enable signal of logic high only to the start of one field, and logic low for the other field when asynchronously writing data for a field from the field memory. The present invention has the object of preventing the shaking of an image by writing the data in another field when data of another field is written at the time of the currently being written field. It explains in detail.

As shown in FIG. 4, the video field memory write control device of the present invention receives a horizontal synchronization signal HD of an analog video signal input thereto and generates memory write control signals of odd and even lines of one frame. A horizontal line selector 261 and a vertical synchronization signal VD and a horizontal synchronization signal HD of an input analog video signal are input to determine whether the field is the first field or the second field. The field decision unit 263 for outputting the signals FLD1 and FLD2 and the memory write control signal of the horizontal line selector 261 are applied to select the field decision signal SEL of the field selection control unit 266. A field selector 262 for outputting a write enable signal WE and a flip-flop 264 for receiving a write enable signal WE of the field selector 262 and detecting a start point thereof; , Flip-flop 2 When the output is applied from 64, the memory reset unit 265 for generating the write reset signal RSTW, the read reset signal RSTR, and the discrimination signals FLD1 and FLD2 of the field determination unit 263 are output. A field selection control unit 266 outputs a selection control signal SEL for determining whether a field currently being written and being written is written so as to be written in its own field area even if data for another field is written.

On the other hand, the field selection controller 266 receives an AND gate 266-1 for combining and receiving the read reset signal RSTR and the first field read determination signal RDFLD1, and the AND gate 266-1. A flip-flop (266-2) for receiving a clock as an input and receiving a field discrimination signal (FLD1, FLD2) output from the field determination unit 263 to determine a field of image data currently being written to the field memory. And selecting the field discrimination signals FLD1 and FLD2 output from the field determination unit 263 by the output of the flip-flop 266-2 to apply the field selection signal SEL to the field selector 262. It consists of the multiplexer 266-3.

The present invention configured as described above will be described in detail with reference to FIGS. 4 and 5.

Assuming that the data of the input video signal currently being written to the field memory is the second field, the line of the second field is composed of lines 22 to 261.

The field determination unit 263 receives the horizontal synchronization signal HD and the vertical synchronization signal VD, and maintains a logic high section when the first field is written to the field memory as shown in FIG. The discrimination signal FLD1 is output, and the discrimination signal FLD2 for the second field maintains a logic low section, and as shown in (c), if the second field is being written to the field memory, The determination signal FLD2 for maintaining the high section is output, and the determination signal FLD1 for the first field outputs a signal for maintaining the logic low section.

Meanwhile, the AND gate 266-1 of the field selection controller 266 receives the read reset signal RSTR and the first field read determination signal RDFLD1 as shown in FIG. By combining, only the reset signal for the first field is output.

The flip-flop 266-2 receives the field discrimination signals FLD1 and FLD2 output from the field determination unit 263, and receives the output of the AND gate 266-1 as a clock to start the first field. Determines whether the image data to be read is from the first field or the second field.

Therefore, if the output of the flip-flop 266-2 is logic high, the data of the first field is read in the first field, whereas if the output of the flip-flop 266-2 is logic low, the data of the second field is read in the first field. In the present invention, the second field in the interval of the first field is taken as an example.

The multiplexer 266-3 receives the field selection signals FLD1 and FLD2 and outputs the field selection signal SEL by the output of the flip-flop 266-2. The logic high is applied to the control terminal S. When input, the lines 22 to 261 of the first field are selected by the field selector 262, and when logic high is input, the control signal SEL to select the lines 23 to 262 of the second field by the field selector 262. ) Will be printed.

Therefore, as shown in FIG. 5 (d), since the control signal of the logic low is input to the control terminal of the current multiplexer 266-3, the field selection signal for the discrimination signal (FLD1) for the first field ( SEL), which is a conventional case in which lines 22 to 261 are stored in a field memory and then lines 23 to 262 are stored in order, but in the present invention, lines 23 to 262 are stored by the field selection controller 266. In this case, the write enable signal WE of the field selector 262 is not selected in the first field as shown in FIG. 5E. Line data is selected only for the second field.

As described above, when the data of the second field is written at the time when the first field is written, the present invention has the effect of eliminating image blur by scanning the data into the first field.

Claims (2)

The horizontal line selector 261 that receives the horizontal sync signal HD of the input analog video signal and generates memory write control signals for odd and even lines of one frame, and the vertical sync signal of the input analog video signal. A field determination unit 263 which receives the VD and the horizontal synchronization signal HD and determines whether it is a first field or a second field and outputs field discrimination signals FLD1 and FLD2 for each field; The field selector 262 receives the memory write control signal of the line selector 261 and selects it by the field select signal SEL of the field selector 266 and outputs a write enable signal WE according thereto. And a flip-flop 264 that receives the write enable signal WE of the field selector 262 and detects a start point thereof, and a write reset signal RSTW when an output is applied from the flip-flop 264. Memory reset causing a Field 265, the read reset signal RSTW and the discrimination signals FLD1 and FLD2 of the field determination unit 263 are received to determine the field currently being written, even if data for the other field is being written. And a field selection control unit (266) for outputting a selection control signal (SEL) corresponding thereto to be written to the area. The field select controller 266 of claim 1, wherein the field select controller 266 receives the read reset signal RSTR and the first field read determination signal RDFLD1, and performs an AND combining operation on the AND gate 266-1, A flip-flop (266) which receives the output of 266-1 as a clock and receives the field discrimination signals (FLD1 and FLD2) output from the field determination unit 263 to determine a field of image data currently being written to the field memory. -2 and the field discrimination signals FLD1 and FLD2 output from the field determination unit 263 by the output of the flip-flop 266-2, and the field selector 262 selects the field selection signal SEL. And a multiplexer (266-3) for applying a video field memory write control device.