JP3297930B2 - Down converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a downconverter suitable for converting a high-definition television signal into another television signal.

[0002]

2. Description of the Related Art When a high-resolution television signal having a large number of lines (the number of horizontal scanning lines) such as a Hi-Vision signal is converted into a television signal of a smaller number of lines, such as an NTSC system or a PAL system, FIG. A conversion display mode as shown in FIG.

Hi-vision signal (original television signal)
A case where the wide aspect ratio is 16: 9 and this is converted into a television signal having a normal aspect ratio of 4: 3 (new television signal) will be described. FIG. 7A shows a conversion display mode called a letter box. It is. In the letterbox mode, the entire wide-area image having an aspect ratio of 16: 9 is compressed to 3/4 and displayed at the center of a screen having an aspect ratio of 4: 3. The image is displayed in a state where non-image portions are formed at the top and bottom of the screen.

FIG. 1B shows a conversion display mode called an edge crop. This is such that a part of the left and right parts of the high definition signal is cut and displayed.

FIGS. 1C and 1D show a conversion display mode called magnify. In this mode, a predetermined area, for example, a half area (shown by oblique lines) is extracted from the image area of the Hi-Vision signal and displayed at an arbitrary magnification, for example, twice.

[0006] As a down converter for converting into a new television signal corresponding to such various conversion display modes, a configuration as shown in FIG. 8 is known. A high vision signal is supplied to the terminal 11.

The pass band of the Hi-Vision signal is limited by the filter 12. When the conversion display modes are the three types described above, the sampling rates at the time of A / D conversion are different from each other, so that a low-pass filter characteristic according to the sampling rate is given. In this example, three types of filters, a letterbox filter 12a, an edge crop filter 12b, and a magnify filter 12c, are selected according to the conversion display mode. Reference numeral 13 denotes the selection switch.

The output of the selection switch 13 is the A / D converter 1
4 and is digitized by being sampled at a predetermined sampling rate. The sampling rate differs depending on the selected conversion display mode. The digitized Hi-Vision signal is supplied to the phase dividing circuit 15 and converted from one-phase to four-phase signals.

In the example shown in FIG. 8, sampling data is extracted one by one every three sampling data to form a four-phase Hi-Vision signal. Therefore, the first-phase sampling data (a-phase data) is 1, 5, 9,..., And the second-phase sampling data (b-phase data) is 2, 6, 1
0, etc.

Each of these four-phase (four-channel) divided signals (divided Hi-Vision signals), which has been compressed to one-fourth in the horizontal direction, is supplied to a phase conversion circuit 16 to be converted from four phases to two phases. You. In the letterbox mode or the edge crop mode, the signal is converted into a two-phase split signal of an a-phase split signal and a c-phase split signal or a b-phase split signal and a d-phase split signal.

In the case of the magnify mode, data of all four phases are used. In this example, however, the data is divided into two phases and output. Becomes Therefore, as shown in FIG.
, And the sampling data of the second phase is 2, 4,
6, ...

The reason why the data is divided into two phases and processed is that the processing speed in the signal processing system at the subsequent stage is reduced to half, so that a circuit system with a very high processing speed is not formed. This is to make it easier.

Each of the divided signals subjected to the two-phase conversion is supplied to a line number conversion circuit 17, where the line number is converted according to the conversion display mode. PA as a new television signal
If the signal is an L-type television signal, the signal is converted into 625 lines per frame.
Converted to a book.

After the number of lines is converted, it is supplied to a color corrector / enhancer 22 where color correction processing and the like are performed. Then, a new analog television signal is obtained at an output terminal 24 by a D / A converter 23. Parallel-to-serial conversion from two phases to one phase can be performed by the color corrector and enhancer 22.

When the new television signal is a component signal, and the Hi-Vision signal has a three-channel configuration including a luminance signal and a pair of color difference signals, the converter shown in FIG. 7 must also exist for three channels. However, the description is omitted.

In FIG. 8, reference numeral 20 denotes a conversion ratio control circuit, which controls the number of horizontal samples and the number of lines according to the conversion display mode. Reference numeral 21 denotes an extraction position control circuit, which also controls the cutout positions at both the horizontal position and the vertical position according to the conversion display mode.

[0017]

By the way, the horizontal conversion ratio is controlled in the letterbox mode so that the number of effective samples of the HDTV signal becomes the same as the number of effective samples of the output. In practice, the sampling process is performed at twice this sampling frequency in consideration of a magnify mode, for example, twice the magnify mode.

When converting from four phases to two phases, data is decimated on an individual basis.
2, band limitation corresponding to the thinning of the data is performed.

In the edge crop mode, the sampling frequency of the A / D converter 14 is selected so that 3/4 of the number of effective samples of the HDTV signal is equal to the number of effective samples at the output, and the horizontal and vertical cut-out positions are selected. Is performed by controlling the read address of the memory.

In the double magnification mode, phase conversion is performed in the phase conversion circuit 16 using all of the input data. The movement of the horizontal position is performed by controlling the write address of the memory in the phase conversion circuit 16, and the movement of the vertical position is performed by controlling the write address of the line number conversion circuit 17.

As described above, the conventional down converter 10
Although the horizontal position adjustment can be easily performed by controlling the address of the memory regardless of the selected conversion display mode, the horizontal sample conversion is performed by changing the sampling frequency for A / D conversion of the input analog signal. Is going. Therefore, as many types of low-pass filters 12 as the number of conversion display modes must be prepared. In particular, when an input signal is divided into several channels, low-pass filters are required for the number of channels.

For this reason, since the circuit scale becomes large, if a conversion display mode using a special conversion ratio such as zooming is mounted, more low-pass filters are provided. In practice, such a conversion display mode is employed. It is not possible. Further, the frequency characteristic becomes unstable due to the use of the low-pass filter.

The above-described method of changing the sampling frequency in the horizontal direction is effective only for analog input signals, and cannot be applied to digital input signals.

Also, it cannot be applied to a digital output in which a sampling frequency such as a 4: 2: 2 digital standard is defined.

Accordingly, the present invention has been made to solve such a conventional problem, and proposes a downconverter which does not require an analog filter circuit and can perform digital output in accordance with a digital standard.

[0026]

According to a first aspect of the present invention, there is provided a downconverter for downconverting a television signal having a large number of lines into a television signal having a small number of lines. A phase division circuit that divides a signal into N parts in the horizontal direction and simultaneously outputs N division television signals; and a N division division output from the phase division circuit with a conversion ratio corresponding to a conversion display mode to be downconverted. A line number conversion circuit for converting the number of lines of a television signal, and a memory, wherein a writing operation to the memory is controlled to convert the N-divided television signal output from the line number conversion circuit into an M-division television. Writing as a version signal and controlling the read operation from the memory to write to the line memory. A horizontal position control circuit for simultaneously outputting M-divided television signals, and a conversion ratio corresponding to a conversion display mode to be down-converted, the number of samples of the M-divided television signals output from the horizontal position control circuit is determined. It has a sample number conversion circuit for conversion, and a post-division number conversion circuit for converting the M-divided divided television signal output from the sample number conversion circuit into a one-phase television signal.

According to a second aspect of the invention, the line number conversion circuit and the sample number conversion circuit are reversed from the first aspect.

[0028]

FIG. 1 shows an example of the first invention. The digitized input television signal is supplied to a phase dividing circuit 30 to simultaneously output divided television signals divided into N in the horizontal direction. Each of the simultaneously outputted divided television signals is converted into a line number converting circuit 31. In, the number of lines is converted with a conversion ratio corresponding to the conversion display mode to be downconverted.

Next, the line number conversion output is passed through the horizontal position control circuit 50, and the sample number conversion circuit 60 performs horizontal sample number conversion in accordance with the conversion display mode. The divided television signal (example of M = N) is converted into a one-phase television signal. This is not a process of thinning out sampling data for forming a new television signal having the number of lines and a number of samples according to the conversion display mode, but a process of dividing the sampling data by N in the horizontal direction. The horizontal frequency division does not change its frequency characteristic.

Since the sampling data thinning process according to the conversion display mode is performed digitally by the sample number conversion circuit, the circuit scale does not increase even if the number of conversion display modes is large.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A case where an example of a downconverter according to the present invention is applied to the above-described downconverter for HDTV signals will be described in detail with reference to the drawings.

In the present invention, a television signal having a large number of lines is exemplified by a high vision signal. As a new television signal whose line number has been converted, a PAL television signal is exemplified. As described above, there are three types of conversion display modes: a letterbox mode, an edge crop mode, and a magnify mode (for example, a double magnify mode).

The HDTV signal has 11 horizontal lines.
25 lines, 60 Hz, 2: 1 interlace signal,
The number of effective samples in the horizontal direction is 1920. A PAL television signal has 625 horizontal lines and 5 horizontal lines.
This is an interlace signal of 0 Hz and 2: 1. The number of effective samples in the horizontal direction is 720.

In the down converter 10 according to the present invention shown in FIG. 1, the Hi-Vision signal supplied to the terminal 11 is first converted into a digital signal in the A / D converter 14. This digital conversion is constant regardless of the selected conversion display mode.

The digitized Hi-Vision signal is supplied to the phase dividing circuit 30 and divided into N parts in the horizontal direction (N
Is any integer). In this example, 4
Divided into two. Each divided television signal A ~
D (hereinafter, referred to as divided signals) are simultaneously output as parallel signals.

Each of the parallel divided signals A to D is supplied to a line number conversion circuit 31 and subjected to a line number conversion process according to the conversion display mode. In this example, a non-interlaced signal (625 lines / 60 Hz / 1) is used. : 1).

In the letterbox mode, the number of lines is converted from 1125 lines per frame to 625 lines per field, so that the line number conversion ratio is 6: 5.

Magnification mode For example, in the case of a twice-magnification mode, 1/2 of the image per field is used.
Is used to enlarge the image by a factor of two to obtain a new image after conversion. Therefore, the number of lines of the divided signals A to D is １ of one field, that is, (1125/2) / 2 lines. Become. Since the number of converted lines is 625, the line number conversion ratio is 9:20.

Since the edge crop mode is the same as the normal mode of the double magnification mode, the line number conversion ratio is 9:10.

The conversion of the number of lines is performed using a frame memory. By controlling the write address and read address of the frame memory,
Since the horizontal and vertical cutout positions for the divided signals can be controlled, the display position in each conversion display mode can be arbitrarily selected by adding an address control function.

The divided signals A to D whose number of lines have been converted in accordance with the conversion display mode are then supplied to the horizontal position control circuit 5.
0 is supplied. The horizontal position control circuit 50 is a circuit used particularly when the magnify mode is selected, and in other conversion display modes, the processing is normally fixed.

Assuming that the original image area is SN as shown in FIG. 3 and the image area when the double magnification mode is selected is SM, the original N divided signals A to D (N = 4), the new divided signal of M division in the magnify mode becomes like divided signals a to d when M = N. Therefore, when the magnify mode is selected, it is necessary to perform data conversion processing for associating the divided signals A to D with the new divided signals a to d. If the horizontal and vertical positions of the designated image area SM are different, it is natural that the data conversion processing for associating the divided signals A to D with the new divided signals a to d is different.

The processing system for executing the data conversion processing according to the image area SM is the horizontal position control circuit 50. In another conversion display mode, the relationship between the original divided signals A to D and the new divided signals a to d is as follows.
A is unchanged so that A corresponds to a.

FIG. 2 shows a specific example of the horizontal position control circuit 50.
B, each of which has the same number of changeover switches SWa to SWd as the number of divisions M (= N) and memories 51a to 51d.
It is composed of

One or more specific signals among the divided signals A to D input by the changeover switches SWa to SWd are selected. Each of the memories 51a to 51d is composed of two line memories connected in parallel.

An example of the horizontal position control will now be described with reference to FIGS. Assuming that the horizontal cutout position of the new image area SM is from the middle position of the divided area A as shown in FIG. 3, a signal relating to the new divided signal a is stored in the memory 51a as shown in FIG.
b stores a signal related to the new divided signal b, a memory 51c stores a signal related to the new divided signal c, and a memory 51d stores a signal related to the new divided signal d. SWd is controlled.

Since the divided signals A to D are simultaneous signals, the divided signal A will be described first. All new divided signals a are divided signals A (the signal at this time is a for convenience).
, The changeover switch SWa is controlled by the corresponding control signal Sa so that the divided signal A is written to the first memory MA1 by the write enable signal WA1 supplied to the first memory MA1. .

The new divided signal b is stored in the second memory 51b. As shown in FIG. 3, the first half of the new divided signal b is composed of the signal A2 in the second half of the divided signal A, and the second half is composed of the first signal B1 of the divided signal B. In the divided signals A2 and B1, the signal B
1 (because the divided signals A and B are simultaneous signals) and the divided signals B1 and A2 are separated by a predetermined time, so that the divided signal B1 is the second signal as shown in FIG.
The divided signal A2 is stored in the first memory MB1 after a lapse of a predetermined time after the end of the memory. Thus, the first changeover switch SWb is controlled by the control signal Sb.

Since the new signal c is composed of only the divided signal B (= B2) as shown in FIG. 3, in this case, the third changeover switch SWc is controlled so that the divided signal B
At the timing when 2 is supplied, the divided signal B2 is stored in the first memory MC1 constituting the third memory 51c as shown in FIG.

As for the new signal d, the signal B3 in the latter half of the divided signal B and the signal C in the former half of the divided signal C as shown in FIG.
In this case, as shown in FIG. 4, the fourth changeover switch SWd is controlled to supply the divided signal C1 to the first memory MD2 constituting the fourth memory 51d, as shown in FIG. The divided signal C1 is stored on the side.
Then, at the timing when the divided signal B3 is input, the fourth changeover switch SWd is controlled again, and the second memory MD
1, the divided signal B3 is stored.

When such processing is performed, all new divided signals a to d corresponding to one horizontal period are stored in the memory. Therefore, the signals a to d are used in the next one horizontal period.
The read operation is performed simultaneously on d (see FIG. 4).
In this case, when a signal is stored in each of the two memories connected in parallel, the first memory MA1,
Signals are read first from MB1, MC1, and MD1, and the second memories MA2, MB2, MC
2 and MD2 signals are read. The sum of each read time is one horizontal period.

In FIG. 1, 35 is a conversion ratio signal output circuit, and 36 is a position control signal output circuit. In the conversion ratio signal output circuit 35, a signal (conversion ratio signal) representing a conversion ratio with respect to the number of lines and the number of samples according to the selected conversion display mode is supplied to the line number conversion circuit 31 and the sample number conversion circuit 60.

Even in the position control signal output circuit 36, it is necessary to control the vertical and horizontal cutout positions and the like in accordance with the selected conversion display mode, so the control signal is sent to the line number conversion circuit 31 and the horizontal position control circuit 50. Is supplied.

FIG. 5 shows a specific example of the memory control signal forming circuit 70 for horizontal position control provided in the position control signal output circuit 36. This forming circuit 70 is a circuit that is particularly active when the magnify mode is selected.

A description will be given with reference to FIG. In FIG.
Assuming that the absolute address from the horizontal origin (scanning start point) to the horizontal cutout position in the magnify mode is H, the absolute address from this cutout position to each boundary point from each of the divided signals a to d is Pa to It is given by Pd.

In FIG. 5, reference numeral 71 denotes an absolute address Pa to
The Pd generation circuit generates an address corresponding to the conversion display mode from the terminal 72. This is because the boundary points of the divided signals a to d differ depending on the selected conversion display mode. These absolute addresses are the absolute addresses H indicating the horizontal cutout position from the input terminal 74 in the adder 73.
Is added.

This addition processing operation is managed by the transfer timing controller 75 so as to be performed during the vertical blanking period. Therefore, the controller 75 is supplied with the vertical synchronizing signal VP from the terminal 76, and also with the horizontal address data output from the horizontal counter 77, and in synchronism with the vertical synchronizing signal VP and the horizontal address data. Pd is output.

The output of the adder 73 is supplied to the ROM 78, and the absolute addresses Pa to Pd including the absolute address H are converted into relative addresses. The converted relative addresses (indicated as Pa to Pd for convenience) are stored in the corresponding registers 80a to 80d in the vertical blanking period in synchronization with the latch pulses La to Ld output from the controller 75.

The relative addresses Pa to Pd read from the registers 80a to 80d are compared with the comparators 81a to 81d, respectively.
d, the write enable signal W associated with the memories 51a to 51d for performing the processing shown in FIG.
A1 to WD2 are generated. Write enable signal WA
The detailed description of 1 to WD2 will be omitted because it will be the same as the description of FIG. Read enable signals RA1 to RD
The same applies to No. 2.

At the same time, it is also supplied to the switching signal forming circuits 82a to 82d, whereby switching control signals Sa to Sd for the switching switches SWa to SWd are formed.

By the above switch control operation and memory operation, a new divided signal a corresponding to the image area SM is obtained.
~ D is obtained.

The new divided signals a to d are supplied to the sample number conversion circuit 60 shown in FIG. 1, and the sample number conversion processing according to the conversion display mode is performed.

The sample number conversion circuit 60 includes digital filters DFa to DFd for each phase and line memories LMa to LMd and LM provided at the preceding and succeeding stages.
a 'to LMd'.

The digital filters DFa to DFd are for performing corresponding filter processing when data thinning processing in the conversion display mode is performed as described later. This means that the filter coefficient is controlled for each data to give a predetermined filter characteristic.

The line memories LMa to LMd in the preceding stage are 2
This is a line memory used when performing a magnification of twice or more (for example, triple magnification) (up-rate sampling mode).

Subsequent line memories LMa 'to LMd'
Is used for data thinning processing in accordance with the conversion display mode, and arbitrary data thinning can be realized by controlling the write address.

The sample number conversion circuit 60 performs a conversion process so that the number of samples becomes 960 regardless of which conversion display mode is selected. When the letterbox mode and the edge crop mode are selected, the conversion process of the number of samples is performed using all four phases of the four divided signals a to d as in the conventional case. The conversion process of the number of samples is performed using the two phases.

The number of effective samples of the HDTV signal is 19
Since it is 20, if it is divided into four in the horizontal direction, the number of signals becomes 480 samples per divided signal. 4 with converted number of samples
As shown in FIG. 1, the divided signal is then subjected to parallel-to-serial conversion by the phase conversion circuit 34 to return to a one-phase television signal. Therefore, when converting from 4 phases to 1 phase, 4
The number of samples of the divided signals a to d is 4 phases × 48
0 samples = 1920 samples, resulting in too much data.

From the above, in the letterbox mode or the edge crop mode in which all four-phase divided signals a to d are used, the sampling number conversion circuit 60 thins out data in each phase to １ ／. By this thinning-out processing, the number of samples after the parallel / serial conversion into one phase becomes the target 960 samples.

In the magnify mode, half of the effective sample 960 of the HDTV signal is cut out, so that the number of 240 samples per divided signal of the four-phase divided signals a to d is obtained. In this case, 240 samples × 4 phases = 960 samples even after one-phase conversion, so that the number of samples does not exceed the specified number. Therefore, the conversion of the number of samples is not performed in the double magnification mode.

Such a sample number conversion process is appropriately selected by a signal FS related to the selection of the conversion display mode as shown in FIG. WCK is a line memory LMa-L
The write clock for Md ', RCK is its read clock.

As shown in FIG. 1, after the conversion processing of the number of lines, the phase conversion processing is performed as described above, and the number of lines is 625, the field frequency is 60 Hz, and the non-interlace (1: 1) Thus, a television signal having 960 horizontal effective samples is output. Since the aspect ratio of the television signal remains at 16: 9, the television signal of this landscape screen is obtained at the output terminal 25.

Next, this television signal is supplied to a frame number conversion circuit 40, where 60 frames are converted into 50 frames so as to conform to the PAL system. Thereafter, the data is supplied to a post-processing circuit 41, where post-processing such as gamma correction and calorimetric conversion processing is performed. When the post-processing is completed, different processing is performed this time depending on the selection of the conversion display mode.

When the letterbox mode is selected, 960 samples are converted by the sample number conversion circuit 42 to PAL.
The number of valid samples is converted into 720 according to the method, and then output to the changeover switch 44 side.

In the edge cropping mode, the signal is supplied to the horizontal cropping position control circuit 43 to control from which position in the horizontal direction 3/3 is cropped by an external instruction.

In the magnify mode, since 960 samples themselves are used, the changeover switch 4 in the through state is used.
Output to the 4 side.

The changeover switch 44 selects a television signal for the designated conversion display mode,
The signal is supplied to the / A converter 23 to obtain an analog television signal. Therefore, this television signal
This is a PAL television signal having 625 lines, 50 Hz, 2: 1 (interlace signal) and an aspect ratio of 4: 3.

Since the television signal obtained at the output terminal 24 is a component signal, the structure shown in FIG. 1 actually has two channels of a luminance signal and a color difference signal. Are combined to obtain a final composite television signal of the PAL system.

In the above-described magnify mode, a description has been given of a double magnify mode. However, the display magnification is merely an example, and the same applies to other magnifications.

For example, when the triple magnification mode is selected, the write enable period for each of the memories provided in the line number conversion circuit 31, the horizontal position control circuit 50 and the sample number conversion circuit 60 is two.
/ 3 times, and a 2: 3 sample number conversion process is performed.

The digital filter DFa provided in the sample number conversion circuit 60 in accordance with the sample number conversion processing.
DFd is switched to the triple magnify mode. The other operations are the same as those described above.

In the above-described first invention, the number of lines is converted according to the selected conversion display mode, and then the number of samples corresponding to the selected conversion display mode is converted.

The second invention is the reverse of the signal processing of the first invention. That is, as shown in FIG. 6, each of the divided signals output simultaneously is first subjected to horizontal sample number conversion in accordance with the selected conversion display mode in the sample number conversion circuit 60. After that, the line number conversion circuit 31 passes through the horizontal position control circuit 50.
And the number of lines is converted with a conversion ratio corresponding to the conversion display mode to be downconverted. In this case, although the sample number conversion circuit 60 performs a 4-part parallel input process, the output can be divided into two, and the line number conversion circuit 31 at the next stage is divided into two, and the circuit can be simplified (N = 4, M = 2). Subsequent processes are the same as those in FIG. 1, and other descriptions are omitted.

Even if such signal processing is reversed from that of FIG. 1, a new down-converted television signal having the number of lines and the number of samples according to the conversion display mode can be generated.

In both the first invention and the second invention, the television system of the television signal to be down-converted is not particularly limited to the above example.

[0086]

As described above, in the down converter according to the first aspect of the invention, the input television signal is divided into N parts in the horizontal direction, each television signal is output simultaneously, and And a conversion process of the number of samples, and finally down-converts to a television signal having an intended line number and a sample number and having an aspect ratio conforming to the current television system.

According to this, since it is not necessary to use an analog low-pass filter for the input television signal according to the conversion display mode, the circuit size can be greatly reduced. In particular, when the input television signal is a digital component signal, conventionally, the input signal is once D / A-converted, and A / D conversion is performed again according to the conversion mode.
Although D conversion had to be performed, the present invention does not have such a case.

Further, since the converter has an all-digital configuration, it is possible to output a digital output corresponding to a digital standard such as 4: 2: 2.

Needless to say, during the conversion process of the number of samples, since the data is thinned out, it is necessary to control the coefficient of the corresponding digital filter. In this case, too, the digital filter has two luminance signals and color difference signals. Any number may be used, and an arbitrary low-pass filter characteristic can be provided by a coefficient given from the outside. Therefore, the configuration can be significantly simplified as compared with the conventional case.

The second invention also has the same features as described above, since the manner of signal processing is only the reverse of that of the first invention. Therefore, the present invention is particularly suitable for application to a down converter in which a plurality of modes can be selected as the conversion display mode.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of a down converter according to the present invention.

FIG. 2 is a system diagram of a main part showing a specific example of FIG. 1;

FIG. 3 is a diagram for explaining a magnify mode.

FIG. 4 is a waveform chart for explaining the operation.

FIG. 5 is a system diagram showing a specific example of a main part of a position control signal output circuit.

FIG. 6 is a system diagram showing an example of a down converter according to the second invention.

FIG. 7 is an explanatory diagram of a conversion display mode.

FIG. 8 is a system diagram of a conventional down converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Down converter 30 Phase division circuit 31 Line number conversion circuit 50 Horizontal position control circuit 60 Sample number conversion circuit 34 Phase conversion circuit 40 Frame number conversion circuit 42 Sample number conversion circuit 43 Horizontal position control circuit

Claims (6)

(57) [Claims] 1. A down-converter for down-converting a television signal having a large number of lines into a television signal having a small number of lines, wherein an input television signal is divided into N parts in the horizontal direction and N-divided television signals are simultaneously output. A phase division circuit that converts the number of lines of the N-divided television signal output from the phase division circuit with a conversion ratio corresponding to the conversion display mode to be down-converted; Controlling the write operation to the memory to write the N-divided television signal output from the line number conversion circuit as the M-divided television signal and to control the read operation from the memory. Simultaneously output the divided television signals of M division written in the line memory. A horizontal position control circuit that converts the number of samples of the M-divided television signal output from the horizontal position control circuit with a conversion ratio corresponding to the conversion display mode to be downconverted; A down-converter for converting the M-divided television signal output from the sample number converter into a one-phase television signal. 2. The conversion display mode includes a letterbox mode for compressing the entire image to display the image at an aspect ratio of 4: 3, an edge crap mode for cutting and displaying a part of the right and left portions, and a predetermined area. Magnify mode in which the image is enlarged and displayed by magnification can be selected. In the line number conversion circuit, the conversion ratio is switched according to the selected conversion display mode. In the sample number conversion circuit, the letter box is used. 2. The down converter according to claim 1, wherein when the mode or the edge clap mode is selected, a thinning process is performed to convert the number of samples. 3. The horizontal position control circuit controls writing of a signal to the memory when a magnify mode is selected as the conversion display mode, so that an image designated from the N-divided television signal is output. 2. The down converter according to claim 1, wherein only the area is extracted and written into the memory as the M-divided television signal. 4. A down-converter for down-converting a television signal having a large number of lines into a television signal having a small number of lines, wherein the input television signal is divided into N parts in the horizontal direction and N-divided television signals are simultaneously outputted. A phase division circuit that converts the number of samples of the N-divided television signal output from the phase division circuit with a conversion ratio corresponding to the conversion display mode to be down-converted; Controlling the write operation to the memory, writing the N-divided television signal output from the sample number conversion circuit as the M-divided television signal, and controlling the read operation from the memory. , The M-divided television signals written in the line memory are simultaneously A horizontal position control circuit that outputs the number of lines of the M-divided television signal output from the horizontal position control circuit with a conversion ratio corresponding to the conversion display mode to be down-converted; And a post-division number conversion circuit for converting the M-division divided television signal output from the line number conversion circuit into a one-phase television signal. 5. The conversion display mode includes a letterbox mode for compressing the entire image and displaying the image at an aspect ratio of 4: 3, an edge crap mode for cutting and displaying a part of the left and right portions, and a predetermined area. A magnify mode for enlarging and displaying at a magnification is selectable. In the sample number conversion circuit, when the letter box mode or the edge crap mode is selected, the number of samples is converted by performing a thinning process, and the line 5. The down converter according to claim 4, wherein the number conversion circuit switches the conversion ratio according to the selected conversion display mode. 6. The horizontal position control circuit, when a magnify mode is selected as the conversion display mode, controls writing of a signal to the memory so as to specify an image designated from the N-divided television signal. 5. The down converter according to claim 4, wherein only the area is extracted and written into the memory as the M-divided television signal.