JPH05308619A - Down converter - Google Patents

Abstract

PURPOSE:To simplify a filter processing system for an input television signal in spite of the number of conversion display modes. CONSTITUTION:A down-converted television signal provided with the number of lines and the number of samples in accordance with the conversion display modes can be formed by outputting N-divided division signals by the simultaneous N-division of the input television signal in the horizontal direction, converting the number of lines of each division signal outputted simultaneously by a conversion ratio in accordance with the conversion display mode to be down-converted at a line number conversion circuit 31. converting the number of samples of line number conversion output in the horizontal direction in accordance with the conversion display mode at a sample number conversion circuit 60 via a horizontal positon control circuit 50, and after that, converting the N-divided television signals to television signals of one phase at a division number conversion circuit 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a down converter suitable for application in the case where a high resolution television signal is converted into another television signal.

[0002]

2. Description of the Related Art When converting a high-resolution television signal having a large number of lines (horizontal scanning lines) such as a high-definition signal into a television signal of an NTSC system or a PAL system having a smaller number of lines, A conversion display mode as shown in 7 is considered.

High-definition signal (original television signal)
7A has a wide aspect ratio of 16: 9 and is converted to a 4: 3 normal aspect ratio television signal (new television signal). FIG. 7A shows a conversion display mode called letterbox. Is. In the letterbox mode, the entire wide surface image having an aspect ratio of 16: 9 is compressed to 3/4 and displayed at the center of the screen having an aspect ratio of 4: 3. The screen is displayed with blank areas at the top and bottom of the screen.

FIG. 1B shows a conversion display mode called edge cropping. This is one in which the left and right parts of the high-definition signal are cut and displayed.

FIGS. 1C and 1D show a conversion display mode called "magnify". This is a mode in which a predetermined area, for example, a half area (shown by diagonal lines) is extracted from the video area of the high-definition signal and is displayed at an arbitrary magnification, for example, 2 times.

A configuration as shown in FIG. 8 is known as a down converter for converting into a new television signal corresponding to such various conversion display modes. A high-definition signal is supplied to the terminal 11.

The pass band of the high-definition signal is limited by the filter 12. When the conversion display modes are the above-mentioned three types, the sampling rates at the time of A / D conversion are different from each other, so that the low-pass filter characteristics corresponding to the sampling rates are given. In this example, three types of filters, a letterbox filter 12a, an edge cropping filter 12b, and a magnifying filter 12c, are selected according to the conversion display mode. Reference numeral 13 indicates the selection switch.

The output of the selection switch 13 is the A / D converter 1
4 and is sampled at a predetermined sampling rate and digitized. The sampling rate differs depending on the selected conversion display mode. The digitized high-definition signal is supplied to the phase dividing circuit 15 and converted into a 1-phase to 4-phase signal.

In the example of FIG. 8, the sampling data is taken out once every three pieces and made into a 4-phase high-definition signal. Therefore, the sampling data of the first phase (a-phase data) is 1, 5, 9, ..., And the sampling data of the second phase (b-phase data) is 2, 6, 1.
It looks like 0 ...

The divided signals (divided high-definition signals) of these four phases (four channels), which are data compressed to 1/4 in the horizontal direction, are supplied to the phase conversion circuit 16 and converted from four phases to two phases. It In the letterbox mode or the edge crop mode, it is converted into a two-phase divided signal of an a-phase divided signal and a c-phase divided signal or a b-phase divided signal and a d-phase divided signal.

In the magnify mode, data of all four phases are used. In this example, however, the data is divided into two phases and output. Therefore, even in this case, the two-phase conversion processing is eventually performed. Becomes Therefore, as shown in the figure, the sampling data of the first phase is 1, 3, 5,
... and the sampling data for the second phase is 2, 4,
6, ...

The reason why the data is processed by dividing it into two phases in this way is that the processing speed in the signal processing system in the subsequent stage is suppressed to 1/2 so that a circuit system having a very high processing speed is not constructed. This is so that it can be done.

Each divided signal obtained by the two-phase conversion is supplied to the line number conversion circuit 17, and the number of lines is converted according to the conversion display mode. PA as a new television signal
In the case of the L system television signal, it is converted into 625 lines per frame, and in the case of the NTSC system, 525 lines are converted.
Converted into a book.

After the number of lines is converted, it is supplied to a color collector and enhancer 22 for color correction processing and the like, and then a new analog television signal is obtained at its output terminal 24 by a D / A converter 23. The parallel / serial conversion from two phases to one phase can be performed by the color collector and enhancer 22.

This new television signal is a component signal, and when the high-definition signal has a three-channel structure including a luminance signal and a pair of color difference signals, the converter shown in FIG. 7 also exists for three channels. However, the description is omitted.

In FIG. 8, a conversion ratio control circuit 20 controls the number of horizontal samples and the number of lines according to the conversion display mode. Reference numeral 21 denotes an extraction position control circuit, which also controls the cutout positions at both the horizontal position and the vertical position according to the conversion display mode.

[0017]

By the way, in the letterbox mode, the horizontal conversion ratio is controlled so that the number of effective samples of the high-definition signal is the same as the number of effective samples of the output, and the sampling frequency of the A / D converter 14 is controlled. However, in actuality, in consideration of the magnifying mode, for example, the magnifying mode of double, the sampling processing is performed at the double sampling frequency.

When converting from 4 phases to 2 phases, data is thinned out one by one, so the low pass filter 1
By 2, the band limitation corresponding to the thinning out of this data is performed.

In the edge cropping mode, the sampling frequency of the A / D converter 14 is selected so that 3/4 of the number of effective samples of the high-definition signal becomes the same as the number of effective samples at the output, and the horizontal and vertical cutout positions are selected. Is performed by controlling the read address of the memory.

In the double magnify mode, the phase conversion circuit 16 performs phase conversion using all of the input data. The movement of the horizontal position is performed by controlling the write address of the memory in the phase conversion circuit 16, and the movement of the vertical position is performed by controlling the write address of the line number conversion circuit 17.

In this way, the conventional down converter 10
The horizontal position adjustment can be easily performed by the memory address control regardless of the conversion display mode to be selected, but the horizontal direction sample conversion is performed by changing the A / D conversion sampling frequency of the input analog signal. Is going. Therefore, it is necessary to prepare as many types of low-pass filters 12 as there are conversion display modes. In particular, when the input signal is divided into several channels, low-pass filters are required for that number of channels.

Therefore, since the circuit scale becomes large, if a conversion display mode that uses a special conversion ratio such as zooming is installed, since there are more low-pass filters, such a conversion display mode is actually adopted. It is not possible. Further, the frequency characteristic becomes unstable due to the use of the low-pass filter.

The above-mentioned method of changing the sampling frequency in the horizontal direction is effective only for the analog input signal and cannot be applied to the digital input signal.

Further, it cannot be essentially applied to a digital output in which a sampling frequency such as a 4: 2: 2 digital standard is defined.

Therefore, the present invention solves such a conventional problem, and proposes a down converter which does not require an analog filter circuit and can perform digital output in accordance with a digital standard.

[0026]

In order to solve the above problems, in the first invention, a down converter for down converting from a television signal having a large number of lines to a television signal having a small number of lines is an input television. The signals are divided into N in the horizontal direction, N divided television signals are simultaneously output, and each of these simultaneously output divided television signals is converted corresponding to the conversion display mode to be down-converted in the line number conversion circuit. The number of lines is converted with the ratio,
The line number conversion output passes through the horizontal position control circuit, and in the sample number conversion circuit, the number of samples in the horizontal direction is converted in the horizontal direction according to the conversion display mode and the number of divisions of N → M is converted. The divided television signal is converted into a one-phase television signal, and a television signal having the number of lines and the number of samples according to the conversion display mode is formed.

A second aspect of the present invention has a configuration in which the line number converting circuit and the sample number converting circuit are reversed from those of the first aspect.

[0028]

1 is an example of the first invention. The digitized input television signal is supplied to the phase division circuit 30, and the divided television signals horizontally divided into N are simultaneously output. Each of these simultaneously output division television signals is converted into the line number conversion circuit 31. In, the number of lines is converted with a conversion ratio corresponding to the conversion display mode to be down-converted.

Next, the line number conversion output is passed through the horizontal position control circuit 50, the sample number conversion circuit 60 performs horizontal sample number conversion in accordance with the conversion display mode, and then the divided number conversion circuit 34 outputs N. A divided television signal (an example of M = N) is converted into a one-phase television signal. This is not a process of thinning out sampling data for forming a new television signal having a line number and a sample number according to the conversion display mode, but a process of horizontally dividing the sampling data into N phases. The frequency characteristic does not change even if it is horizontally divided into.

Since the sampling number thinning process according to the conversion display mode is digitally performed by the sample number conversion circuit, the circuit scale does not increase even if the number of conversion display modes is large.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case in which an example of the down converter according to the present invention is applied to the above-described down converter for high-definition signals will be described in detail with reference to the drawings.

Also in the present invention, a high-definition signal is exemplified as a television signal having many lines. A PAL system television signal is exemplified as the new television signal whose number of lines has been converted. As the conversion display mode, there are three types, as described above, that is, the letterbox mode, the edge crop mode, and the magnify mode (for example, the double magnify mode).

The HDTV signal has 11 horizontal lines.
25 lines, 60Hz, 2: 1 interlaced signal,
The number of effective samples in the horizontal direction is 1920. The PAL television signal has 625 horizontal lines and 5
It is an interlace signal of 0 Hz and 2: 1 and the number of effective samples in the horizontal direction is 720.

In the down converter 10 according to the present invention shown in FIG. 1, the high-definition signal supplied to the terminal 11 is first converted into a digital signal in the A / D converter 14. This digital conversion is constant regardless of the conversion display mode selected.

The digitized high-definition signal is supplied to the phase division circuit 30 and divided in the horizontal direction into N (N
Is any integer). In this example, it is equal to 4 in the horizontal direction
Divided into two. Each television signal A divided into four
D (hereinafter referred to as divided signal) is simultaneously output as a parallel signal.

The parallel divided signals A to D are respectively supplied to the line number conversion circuit 31 and subjected to the conversion processing of the number of lines according to the conversion display mode. In this example, a non-interlaced signal (625 lines / 60 Hz / 1). : 1).

In the letterbox mode, since the number of lines is converted from 1125 lines per frame to 625 lines per field, the line number conversion ratio is 6: 5.

Magnify mode For example, in the double magnify mode, 1/2 of the image per field
Since this is used as a new image after conversion by enlarging it twice, the number of lines of divided signals A to D is 1/2 of one field, that is, (1125/2) / 2. Become. Since the number of lines after conversion is 625, the conversion ratio of the number of lines is 9:20.

Since the edge crop mode is the same as the normal mode of the double magnify mode, the line number conversion ratio is 9:10.

The conversion of the number of lines is performed using the frame memory. By controlling the write address and read address of the frame memory,
Since the horizontal and vertical cutout positions for the divided signals can be controlled, the display position in each conversion display mode can be arbitrarily selected by adding the address control function.

The divided signals A to D, the number of lines of which is converted in accordance with the conversion display mode, are next supplied to the horizontal position control circuit 5.
0 is supplied. The horizontal position control circuit 50 is a circuit used especially when the magnify mode is selected, and is normally fixed in other conversion display modes.

As shown in FIG. 3, when the original image area is SN and the image area when the double magnify mode is selected is SM, the original divided signals A to D are magnified. The new divided signals in the modes are as in a to d. Therefore, when the magnify mode is selected, it is necessary to perform a data conversion process for associating the divided signals A to D with the new divided signals a to d. If the horizontal and vertical positions of the designated image area SM are different, the divided signals A to D are changed to the new divided signal a.
It goes without saying that the data conversion process for associating with ~ d is different.

The processing system for executing the data conversion processing according to the image area SM is the horizontal position control circuit 50. In other conversion display modes, the relationship between the original divided signals A to D and the new divided signals a to d is
It is invariant so that A corresponds to a.

FIG. 2 shows a specific example of the horizontal position control circuit 50, which includes a changeover switch 50A and a memory section 50.
B, each of which includes the same number of changeover switches SWa to SWd as the number of divisions N and memories 51a to 51d.

Specific one or a plurality of signals among the divided signals A to D input by the changeover switches SWa to SWd are selected. Each of the memories 51a to 51d is composed of two line memories connected in parallel.

An example of the horizontal position control will be described below with reference to FIGS. Assuming that the horizontal cut-out position of the new image area SM is from the intermediate position of the divided area A as shown in FIG. 3, the memory 51a stores the signal regarding the new divided signal a as shown in FIG.
The changeover switches SWa to SWa are arranged so that the signal regarding the new divided signal b is stored in b, the signal regarding the new divided signal c is stored in the memory 51c, and the signal regarding the new divided signal d is stored in the memory 51d. SWd is controlled.

Since the divided signals A to D are simultaneous signals, the divided signal A will be described first. All the new divided signals a are divided signals A (the signal at this time is a for convenience).
Therefore, the changeover switch SWa is controlled by the corresponding control signal Sa so that the division signal A is written in the first memory MA1 by the write enable signal WA1 supplied to the first memory MA1. ..

The new divided signal b is stored in the second memory 51b. As for the new divided signal b, as shown in FIG. 3, the former half thereof is composed of the latter half signal A2 of the divided signal A, and the latter half thereof is composed of the former half signal B1 of the divided signal B. The divided signals A2 and B1 are temporally signals B.
1 precedes (because the divided signals A and B are simultaneous signals), and the divided signals B1 and A2 are separated by a predetermined time, so that the divided signal B1 is the second signal as shown in FIG.
Memory MB2, and the divided signal A2 is stored in the first memory MB1 after a lapse of a predetermined time after the end of the memory. In this way, the first changeover switch SWb is controlled by the control signal Sb.

Since the new signal c is composed of only the divided signal B (= B2) as shown in FIG. 3, in this case, the third changeover switch SWc is controlled to divide the divided signal B.
At the timing when 2 is supplied, the division signal B2 is stored in the first memory MC1 side forming the third memory 51c as shown in FIG.

Regarding the new signal d, the signal B3 in the latter half of the divided signal B and the signal C in the first half of the divided signal C as shown in FIG.
As shown in FIG. 4, in this case, as shown in FIG. 4, at the timing when the fourth changeover switch SWd is controlled and the division signal C1 is supplied, the first memory MD2 that constitutes the fourth memory 51d is formed. The divided signal C1 is stored on the side.
Then, at the timing when the divided signal B3 is input, the fourth changeover switch SWd is controlled again and the second memory MD is
The divided signal B3 is stored in the memory 1.

When such processing is performed, all the new divided signals a to d corresponding to one horizontal period have been stored in the memory, and therefore, the signals a to a are stored in the next one horizontal period.
The read operation is simultaneously performed on d (see FIG. 4).
In this case, when the signal is stored in each of the two memories connected in parallel, the first memory MA1,
Signals are read first from MB1, MC1 and MD1, and at the same time as the reading ends, the second memories MA2, MB2 and MC
2, MD2 signal is read. The total of the lead times is one horizontal period.

In FIG. 1, 35 is a conversion ratio signal output circuit, and 36 is a position control signal output circuit. In the conversion ratio signal output circuit 35, a signal (conversion ratio signal) representing a conversion ratio with respect to the number of lines and the number of samples according to the selected conversion display mode is supplied to the number of lines conversion circuit 31 and the number of samples conversion circuit 60.

Even in the position control signal output circuit 36, since it is necessary to control the vertical and horizontal cutout positions and the like according to the selected conversion display mode, the control signal is sent to the line number conversion circuit 31 and the horizontal position control circuit 50. Is supplied.

FIG. 5 shows a concrete example of the memory control signal forming circuit 70 provided in the position control signal output circuit 36 for horizontal position control. The forming circuit 70 is a circuit that is particularly active when the magnify mode is selected.

Description will be made with reference to FIG. In FIG.
When the absolute address from the origin (scanning start point) in the horizontal direction to the horizontal cutout position in the magnify mode is H, the absolute address from this cutout position to each boundary point between the divided signals a to d is Pa to Given by Pd.

In FIG. 5, reference numeral 71 denotes an absolute address Pa ...
This is a Pd generation circuit, and an address corresponding to the conversion display mode is generated from the terminal 72. This is because the boundary points of the divided signals a to d differ depending on the selected conversion display mode. These absolute addresses are absolute addresses H indicating the horizontal cutout position from the input terminal 74 in the adder 73.
Is added.

This addition processing operation is managed by the transfer timing controller 75 so as to be performed during the vertical blanking period. Therefore, the controller 75 is supplied with the vertical synchronizing signal VP from the terminal 76 and the horizontal address data output from the horizontal counter 77, and the absolute address Pa ~ is synchronized with the vertical synchronizing signal VP and the horizontal address data. Pd is output.

The output of the adder 73 is supplied to the ROM 78, and the absolute addresses Pa to Pd including the absolute address H are converted into relative addresses. The converted relative address (shown as Pa to Pd for convenience) is stored in the corresponding registers 80a to 80d within the vertical blanking period in synchronization with the latch pulses La to Ld output from the controller 75.

The relative addresses Pa to Pd read from the registers 80a to 80d are respectively compared with the comparators 81a to 81.
write enable signal W associated with the memories 51a to 51d for performing the processing shown in FIG.
A1 to WD2 are generated. Write enable signal WA
Detailed description of 1 to WD2 will be omitted because it overlaps with the description of FIG. Read enable signals RA1 to RD
The same applies to 2.

At the same time, it is also supplied to the switching signal forming circuits 82a to 82d to form the switching control signals Sa to Sd for the changeover switches SWa to SWd.

By the above switch control operation and memory operation, a new division signal a corresponding to the image area SM is obtained.
~ D is obtained.

The new divided signals a to d are supplied to the sample number conversion circuit 60 shown in FIG. 1, and the sample number conversion processing according to the conversion display mode is performed.

The sample number conversion circuit 60 includes digital filters DFa to DFd for each phase and line memories LMa to LMd and LM provided in the preceding and subsequent stages thereof.
a'to LMd '.

The digital filters DFa to DFd are for performing corresponding filter processing when data thinning processing in the conversion display mode is performed as described later. In this, the filter coefficient is controlled for each data to give a predetermined filter characteristic.

The line memories LMa to LMd in the preceding stage are 2
It is a line memory used when magnifying more than twice (for example, triple magnifying) (up-rate sampling mode).

Later line memories LMa 'to LMd'
Is used for data thinning processing according to the conversion display mode, and arbitrary data thinning can be realized by controlling the write address.

In the sample number conversion circuit 60, for example, conversion processing is performed so that the sample number becomes 960 regardless of which conversion display mode is selected. When the letterbox mode and the edge cropping mode are selected, the conversion processing of the number of samples is performed using all four phases of the four-divided signals a to d as in the conventional case, and in the magnify mode, the four-divided signals a to d are converted. The conversion processing of the number of samples is performed by using the two phases.

The number of effective samples of the high-definition signal is 19
Since it is 20, there are 480 samples per divided signal when the signal is divided into four in the horizontal direction. Number of samples converted 4
As shown in FIG. 1, the divided signals are then parallel-serial converted by the phase conversion circuit 34 and returned to a one-phase television signal. Therefore, when converting from 4 phases to 1 phase, 4
The number of samples of the divided signals a to d itself is 4 phases × 48
0 samples = 1920 samples and there is too much data.

Therefore, in the letter box mode or the edge cropping mode in which all the four-phase divided signals a to d are used, the sample number conversion circuit 60 performs the thinning process on the data for each phase to 1/2. By this thinning-out processing, the number of samples after parallel / serial conversion into one phase becomes the target of 960 samples.

In the magnify mode, half the effective samples 960 of the high-definition signal are cut out, so that there are 240 samples per divided signal of the four-phase divided signals a to d. In this case, the number of samples does not exceed the specified number, because 240 samples × 4 phases = 960 samples are obtained even by one-phase conversion. Therefore, the number of samples is not converted in the double magnify mode.

Such sample number conversion processing is appropriately selected by the signal FS related to the selection of the conversion display mode as shown in FIG. WCK is a line memory LMa to L
The write clock for Md 'and RCK are its read clocks.

As shown in FIG. 1, after the conversion processing of the number of lines, the phase conversion processing is performed as described above, the number of lines is 625, the field frequency is 60 Hz, and the non-interlace (1: 1). Then, a television signal having 960 horizontal effective samples is output. Since the aspect ratio of this television signal remains 16: 9, the television signal of this horizontally long screen is obtained at the output terminal 25.

This television signal is then supplied to the frame number conversion circuit 40, and 60 frames are converted into 50 frames so as to conform to the PAL system. Then, the post-processing circuit 41 is supplied to perform post-processing such as gamma correction and colorimetry conversion processing. When the post-processing is finished, different processing is performed this time depending on the selection of the conversion display mode.

When the letterbox mode is selected, 960 samples are PAL in the sample number conversion circuit 42.
It is converted into the effective sample number 720 conforming to the method, and then output to the changeover switch 44 side.

In the edge crop mode, the horizontal position control circuit 43 supplies the horizontal position control circuit 43 to control from which position in the horizontal direction 3/4 is cut by an external instruction.

In the magnify mode, the 960 samples themselves are used, so the changeover switch 4 is set in the through state.
It is output to the 4 side.

The changeover switch 44 selects the television signal for the instructed conversion display mode, which is D
It is supplied to the / A converter 23 to obtain an analog television signal. Therefore, this television signal is
The PAL system television signal has 625 lines, 50 Hz, 2: 1 (interlaced signal), and an aspect ratio of 4: 3.

Since the television signal obtained at the output terminal 24 is a component signal, the configuration shown in FIG. 1 actually has two channels of a luminance signal and a color difference signal. Although not shown, those component television signals are not shown. Are combined to obtain a final PAL system composite television signal.

In the above-described magnify mode, the magnify mode of 2 times has been described, but the display magnification is an example, and the same can be applied to other magnifications.

For example, when the triple magnify mode is selected, the write enable period for each memory provided in the line number conversion circuit 31, the horizontal position control circuit 50, and the sample number conversion circuit 60 is two.
It is changed to / 3 times, and a sample number conversion process of 2: 3 is performed.

A digital filter DFa provided in the sample number conversion circuit 60 in accordance with this sample number conversion processing
The filter coefficients of ˜DFd are switched to the triple magnifying mode. Others are the same as the above-mentioned operation.

The first invention described above is such that the number of lines is converted according to the selected conversion display mode, and then the number of samples corresponding to the selected conversion display mode is converted.

The second invention is the reverse of the signal processing of the first invention. That is, as shown in FIG. 6, each of these divided signals simultaneously output is first subjected to horizontal sample number conversion in the sample number conversion circuit 60 in accordance with the selected conversion display mode. After that, through the horizontal position control circuit 50, the line number conversion circuit 31
And the line number is converted with a conversion ratio corresponding to the conversion display mode to be down-converted. In this case, the sample number conversion circuit 60 performs 4-division parallel input processing, but the output can be divided into 2-division processing, and the line number conversion circuit 31 in the next stage is divided into 2 divisions, and the circuit can be simplified (N = 4, M = 2). Subsequent processing is the same as in the case of FIG.

Even if such signal processing is reversed from the case of FIG. 1, a new down-converted television signal having the number of lines and the number of samples according to the conversion display mode can be generated.

In both the first invention and the second invention, the television system of the television signal to be down-converted is not particularly limited to the above example.

[0086]

As described above, in the down converter according to the first aspect of the present invention, the input television signal is divided into N in the horizontal direction, the respective television signals are simultaneously output, and the number of lines is set for each of them. And the conversion processing of the number of samples, and finally down-converts into a television signal having an aspect ratio conforming to the current television system having the target number of lines and number of samples.

According to this, since it is not necessary to use an analog low-pass filter for the input television signal according to the conversion display mode, the circuit scale can be greatly reduced. In particular, when the input television signal is a digital component signal, in the past, the input signal was once D / A converted, and then again converted to A / A according to the conversion mode.
It was necessary to perform D conversion, but the present invention does not have such a case.

Since it is an all-digital converter, it is possible to output a digital output corresponding to a digital standard such as 4: 2: 2.

Of course, since data thinning processing is performed during the conversion processing of the number of samples, it is necessary to control the coefficient of the corresponding digital filter. In this case, however, the digital filter also has two components, the luminance signal and the color difference signal. Only a small number of them are required, and an arbitrary low-pass filter characteristic can be given by a coefficient given from the outside. Therefore, the configuration can be remarkably simplified as compared with the conventional one.

The second aspect of the invention is similar to the first aspect in that the method of signal processing is the opposite of that of the first aspect, and thus has the same characteristics as described above. Therefore, the present invention is particularly suitable for application to a down converter capable of selecting a plurality of conversion display modes.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of a down converter according to the present invention.

FIG. 2 is a system diagram of a main part showing a specific example of FIG.

FIG. 3 is a diagram for explaining a magnify mode.

FIG. 4 is a waveform diagram for explaining the operation.

FIG. 5 is a system diagram showing a specific example of a main part of a position control signal output circuit.

FIG. 6 is a system diagram showing an example of a down converter according to a second invention.

FIG. 7 is an explanatory diagram of a conversion display mode.

FIG. 8 is a system diagram of a conventional down converter.

[Explanation of symbols]

 10 Down Converter 30 Phase Division Circuit 31 Line Number Conversion Circuit 50 Horizontal Position Control Circuit 60 Sample Number Conversion Circuit 34 Phase Conversion Circuit 40 Frame Number Conversion Circuit 42 Sample Number Conversion Circuit 43 Horizontal Position Control Circuit

Claims (6)

[Claims] 1. A down converter for down-converting a television signal having a large number of lines into a television signal having a small number of lines, wherein an input television signal is horizontally divided into N and divided television signals are divided into N at the same time. Each of these divided television signals that have been output and are simultaneously output is converted in the line number conversion circuit with a conversion ratio that corresponds to the conversion display mode to be down-converted, and the line number conversion output is the horizontal position. In the sample number conversion circuit via the control circuit, the sample number conversion in the horizontal direction according to the conversion display mode and the conversion number of N → M are performed. It is converted to a television signal and the number of lines and Down converter, characterized in that it is adapted to a television signal is formed and a Le number. 2. The down converter according to claim 1, wherein the conversion display modes are a letter box mode, an edge clap mode and a magnify mode. 3. When the magnify mode is selected as the conversion display mode, only a designated image area of the divided television signal is extracted to form a corresponding new N divided television signal. The down converter according to claim 1, wherein 4. A down-converter for down-converting a television signal having a large number of lines into a television signal having a small number of lines, wherein an input television signal is horizontally divided into N and divided television signals are divided at the same time. Each of the divided television signals that are output and simultaneously output is subjected to horizontal sample number conversion and N → M division number conversion in the sample number conversion circuit according to the conversion display mode, and then to the horizontal position. It is supplied to the line number conversion circuit via the control circuit, the number of lines is converted at a conversion ratio corresponding to the conversion display mode to be down-converted, and the line number conversion output is converted into an M division television signal in the phase conversion circuit. It is converted into a one-phase television signal and the number of lines according to the conversion display mode Down converter, characterized in that it is adapted to a television signal is formed and a sample number. 5. The down converter according to claim 4, wherein the conversion display mode includes a letterbox mode, an edge clap mode and a magnify mode. 6. When the magnify mode is selected as the conversion display mode, only a designated image area of the divided television signal is extracted and a corresponding new N divided television signal is formed. The down converter according to claim 4, characterized in that