JP3237527B2 - High-speed camera system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed camera system for capturing a slow motion image in television broadcasting.

[0002]

2. Description of the Related Art In recent years, as slow motion reproduction is frequently used in sports broadcasting and the like, smoothness of movement of reproduced images is required, and scanning is performed at a higher speed than a standard television scanning speed. The use of high-speed camera systems that can capture more motion information of a subject is also increasing.

A conventional high-speed camera system will be described below. As a conventional high-speed camera system, one described in Japanese Patent Publication No. 5-54315 is known. FIG. 9 shows a block diagram of this conventional high-speed camera system. In FIG. 9, reference numeral 1 denotes a digital television camera (hereinafter, a triple speed camera) that performs scanning at three times the standard scanning speed, 2 denotes a speed conversion circuit, 3 denotes a divided standard output a, 4 denotes a divided standard output b, and 5 denotes a divided standard output b. This is the divided standard output c. FIG. 10 shows a block diagram of the speed conversion circuit 2. In FIG. 10, 16 is a triple speed signal, 17 is a write / read control circuit, and 18 is a field memory (F
M1 to FM16).

The operation of the conventional high-speed camera system configured as described above will be described below.

FIG. 11 is a timing chart showing the operation of the speed conversion circuit of the conventional triple speed camera system. First, 3
The double speed camera 1 performs a genlock operation in response to an external standard speed synchronization signal, and performs scanning at a speed three times the standard television scanning speed. Since the output signal of the triple speed camera 1 is the standard triple speed, as shown in FIG. 11, during the first odd field period of the standard speed, the triple speed odd field 1 signal 1o, the triple speed even field 1 signal 1e,
Three signals of the triple speed odd field 2 signal 2o are continuously output. Similarly, during the first even field period of the standard speed, the triple speed even field 2 signal 2e, the triple speed odd field 3 signal 3o, and the triple speed even field 3 signal 3e are continuously output. The output of the triple speed camera 1 is input to the speed conversion circuit 2 and is divided into three signals and time-expanded to a standard speed signal. 3x speed signal to 3
To divide and time-extend to the standard speed, 6
This can be realized by independently controlling the writing / reading of the two field memories 18. As shown in FIG. 11, during the period 1 of the standard speed odd field, the 1o signal is set to FM1.
The 1e signal is written to FM2 and the 2o signal is written to FM3 at triple speed. Next, during the standard speed even field 1 period, F
The three field memories M1, FM2, and FM3 perform a read operation at a standard speed. At the same time, the 2e signal is written to FM4, the 3o signal is written to FM5, and the 3e signal is written to FM6. Next, in the standard speed odd field 2 period, FM
4. FM5 and FM6 perform the reading operation at the standard speed.
At this time, since the field memories FM1, FM2, and FM3 have finished reading all data, a new write operation starts, and the 4o signal becomes FM1 and the 4e signal becomes FM2.
The 5o signal is written to the FM3 at triple speed. By the operation as described above, the divided standard signal a, the divided standard signal b, and the divided standard signal c shown in FIG.

As described above, the conventional high-speed camera system is designed to handle a high-speed signal as a plurality of standard speed signals. In order to obtain a slow motion output, the three divided standard signals a to c are rearranged in a field order at the time of photographing by a memory or the like, and are converted into one signal, so that a one-third of the normal slow motion output is obtained. obtain. Further, the rearranged signals are recorded on a VTR or the like, and a slow-motion reproduction of the VTR is performed, so that a further slow-motion signal can be obtained.

[0007]

However, in the above-mentioned conventional configuration, when each of the three divided standard signals is viewed as a standard signal on a monitor, the field of each individual signal is discontinuous, and particularly, there is a movement. In video, the movement is jumpy and unnatural. In addition, since the charge accumulation time of the CCD is reduced to one third at the time of 3 × speed photographing, when the three divided signals are viewed as standard signals, the original S / N ratio is obtained.
However, there is a problem that it is worse than at the time of standard speed photographing.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a high-speed camera system which reduces a sense of discomfort in motion and outputs a standard signal having a good S / N ratio.

[0009]

In order to achieve this object, a high-speed camera system according to the present invention comprises a speed conversion circuit comprising
M output means for delaying each output by one horizontal scanning time, and a plurality of M output means of the speed conversion circuit which are the same field in distinguishing a standard television synchronization signal from an odd field and an even field. A selection circuit for switching and outputting an input signal to the delay means and an output signal to the delay means for each of the signals, and a plurality of signals which are different fields in distinguishing between the odd field and the even field of the standard television synchronization signal. A first adder for adding the input signal to the delay means and the output signal to the delay means, a selection signal generation circuit for generating a selection signal for the plurality of selection circuits, a plurality of selection circuit outputs, and the plurality of first circuits. By providing the second adder for adding the adder output, the uncomfortable feeling of the motion can be obtained from the M field signals output within the same field period at the standard speed. No, it is possible to obtain a standard signal that has improving S / N.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, an M is locked by an external standard television synchronizing signal, and scans at a speed M times the standard television (M is an arbitrary positive integer). The output signals of the double-speed digital television camera and the M-times digital television camera are divided into field units at M times the scanning speed, each is time-expanded to the standard scanning speed, and the M divided standard signals are synchronized. A speed conversion circuit for outputting the divided signals, M delay means for delaying each of the M divided standard signals by one standard horizontal scanning time, and a standard television synchronizing signal and an odd field out of the M divided standard signals. Or a selection circuit that outputs a plurality of divided standard signals that are the same field in distinction of even fields by individually switching between an input signal to the delay means and an output signal of the delay means, Among the divided standard signals, a standard television synchronization signal and a plurality of divided standard signals that are different fields in distinguishing between the odd field or the even field are individually input signals to the delay means and output signals of the delay means. A first adder for adding, a selection signal generating circuit for generating a selection signal to the plurality of selection circuits, and a second addition for adding outputs of the plurality of selection circuits and outputs of the plurality of first adders By adding together the fields of the signal for M fields output within a standard one-field period, the unnatural feeling of movement is reduced, and
/ N is obtained.

An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration of a high-speed camera system according to Embodiment 1 of the present invention. In FIG. 1, 1 is a 3 × speed camera, 2 is a speed conversion circuit,
Reference numeral 5 denotes a divided standard signal which is divided and time-expanded and synchronized to a standard scanning speed (each of which is referred to as a divided standard signal a to c), and 6 denotes 1H delay means for input signals for one horizontal scanning period at the standard scanning speed. Delay. 7 is a selection circuit, 8 is a first adder, 9 is a second adder, 10 is a selection signal generation circuit, 11
Is a coefficient unit, and 12 is a standard output N.

FIG. 4 is a drawing showing the principle of operation based on the pixel configuration in the CCD portion of the 3 × speed camera 1. Inputs a, b, and c in FIG. 4 correspond to the divided standard signal a, the divided standard signal b, and the divided standard signal c, respectively. First, FIG.
(A) shows the case where the field at the standard scanning speed is an even field. As can be seen from FIG. 11, the output signal of the 3 × speed camera 1 is read out after being once written in the speed conversion circuit 2, and thus is output after being delayed by one field of the standard speed. Therefore, the signal of the triple speed camera 1 written in the standard speed odd field 1 is
Since the data is read in the standard speed even field 1, input a
Is a 3x odd field 1, input b is a 3x even field 1, and input c is a 3x odd field 2. Since both the input a and the input c are odd fields, they do not match the field of the standard scanning speed. Therefore, if they are added as they are, the interlace relationship is broken and the image is shifted in the vertical direction. For input b, there is no problem because it is an even field. Therefore, for the input a and the input c, two signals separated by one horizontal scanning period are added to make a signal that spatially matches the position of the even field, and then added to the input b.

In FIG. 4, if the signal indicated by 0H is the current input signal, the signal indicated by 1H is the signal one horizontal period earlier, and the signal indicated by 2H is the signal two horizontal periods earlier. In FIG. 4, the position of the photodiode is indicated by the symbol □, and the position of the actual signal by the photodiode mix is indicated by the symbol ○. As shown in FIG. 4A, considering the interlace phase relationship, the signal obtained by (0H + 1H) input a is a signal having an even field phase indicated by P1 in the figure. Similarly, with respect to the input c, the signal obtained by (0H + 1H) becomes the signal of the even field phase indicated by P2. The P1 and P2 signals correspond to the 0H signal at input b. Therefore, even if the 0H signal of the input b, the P1 signal, and the P2 signal are added, no vertical image shift occurs. After the addition of the three signals, the gain is adjusted to obtain a standard scanning speed signal (standard output N) obtained by adding the signals for three fields by ５ by the coefficient unit 11.

Similarly, FIG. 4B shows a case of an odd field at a standard scanning speed. Inputs a and c are even fields, while input b is an odd field. A signal obtained by changing the input a to (0H + 1H) becomes a signal having an odd-numbered field phase indicated by Q1 in the figure, and changing the input c to (0H + 1H).
The resulting signal becomes an odd field signal indicated by Q2 in the figure.
This corresponds to the 1H signal of the input b. Therefore, even if the Q1 signal, the 1H signal of the input b, and the Q2 signal are added, no vertical image shift occurs.

As described above, when M is an odd number in the M-times scanning, the fields of the signals inputted to the inputs a, b and c are inverted in the odd field and the even field of the standard scanning speed. Therefore, in order to perform the addition process accurately, it is necessary to switch the output of the selection circuit 7 input to the second adder 9 to 0H in an even field and 1H in an odd field. Selection signal generation circuit 1
Reference numeral 0 denotes a control circuit that performs this switching operation, and switches the output of the selection circuit 7 in units of a field of a standard speed. In this manner, by adding the three triple-speed field signals in accordance with the field at the standard scanning speed, a standard speed signal having a better S / N and less uncomfortable motion can be obtained.

Incidentally, when the scanning speed of the high-speed camera is an even multiple of the standard (M = even number), a standard scanning signal is obtained by the same concept. FIG. 7 shows the operation when M = 2 (even number). It is a drawing showing a principle. FIG. 7A shows an addition process at the time of an even field at the standard scanning speed. Since the input a is an odd field signal, the addition is performed as it is.
Is an even-numbered field signal, the odd-numbered field data indicated by R in the figure is obtained from (0H + 1H) and added, so that vertical displacement of the video does not occur. The same applies to the odd field shown in FIG.

As described above, according to this embodiment, by adding the M divided standard signals together with the field, the unnaturalness of the moving image portion is eliminated, and the S / N deterioration is reduced. A small standard scanning speed video signal can be obtained.

(Embodiment 2) FIG. 2 is a block diagram showing a configuration of a high speed camera system according to Embodiment 2 of the present invention. In FIG. 2, the configuration related to the arithmetic processing for obtaining the standard scanning speed signal from the divided standard signal is different from that of the first embodiment.

FIG. 5 is a timing chart showing the operation of the high-speed camera system according to the present embodiment. The operation will be described below.

In the case of the first embodiment, in order to obtain a standard signal, two of the three divided standard signals are (0H + 1H).
Must be performed. This calculation is equivalent to applying a low-pass filter in the vertical direction, and the frequency characteristics in the vertical direction deteriorate. In order to improve this, the field of the output signal of the 3 × speed camera 1 is inverted, so that the operation of (0H + 1H) is performed only on one of the three divided standard signals, and the field of the three divided standard signals is Can be combined.

As shown in FIG. 5, by starting the camera output output in the standard speed odd field from the even field, the three divided standard signal outputs of the speed conversion circuit 2 are tripled in the standard speed even field. An even field 1e, a triple speed odd field 1o, and a triple speed even field 2e are obtained. FIG. 6A shows the operation of the line addition circuit at this time. Since inputs a and c are even field signals, no processing is required. Since the input b is an odd field signal, (0H +
1H), an even field signal Q is obtained and added to the 0H signals of the input a and the input c. Similarly, as for the standard odd field, as shown in FIG. 6B, only the input b is (0H + 1H) to obtain an odd field signal P, which is added to the 1H signal of the input a and the input c. In this case, the selection signal generation circuit 10 operates so as to switch between 0H and 1H for the input a and the input c to output. Note that the coefficient machine 11 is assumed to be 1/8.

As described above, according to the present embodiment, the field of the triple speed camera 1 is inverted with respect to the field of a standard synchronization signal from the outside, thereby providing the first embodiment.
As compared with the above, the number of low-pass filter components can be reduced and the frequency characteristics in the vertical direction can be improved. As described above, in the speed conversion circuit shown in FIG. 10, the field of the divided standard signal is inverted with respect to the external standard television synchronization signal. Therefore, for synchronization, a field memory for delaying the three divided standard signals by one field was externally required.
Since the field of the double speed camera 1 output is inverted, synchronization can be performed without requiring an external field memory.

(Embodiment 3) FIG. 3 is a block diagram showing a configuration of a high-speed camera system according to Embodiment 3 of the present invention. In FIG. 3, 13 is a coefficient multiplier for multiplying an arbitrary coefficient α, 14 is a coefficient multiplier for multiplying an arbitrary coefficient β, and 15 is a coefficient multiplier for multiplying an arbitrary coefficient γ. FIG. 8 is a diagram illustrating frequency characteristics in the vertical direction in the case of the standard, the case of the second embodiment, and the case of the third embodiment. As shown in FIG. 8B, the normal frequency characteristic is represented by 1 + Z ^-1 from the two-pixel mixing operation of the CCD. FIG.
As shown in (c), the frequency characteristic according to the method described in Embodiment 2 is 1 + 3Z since each coefficient α = β = γ = 1.
^-1 + 3Z ^-2 + Z ^-3 . FIG. 8D shows that α
= Γ = 3, β = 1 are applied to improve the deterioration of the frequency characteristics in the vertical direction. In this case, the frequency characteristic is 1
+ 7Z ^-1 + 7Z ^-2 + Z ^-3 And FIG.
(A) shows the frequency characteristics in each case. By appropriately selecting the filter characteristics as shown in the present embodiment, the frequency characteristics in the vertical direction can be significantly improved as compared with the second embodiment.

In the above embodiment, M = 2
Or, the case of 3 has been described, but the present invention is not limited to this, and it is sufficient to provide the necessary number of delay means and selection circuits in accordance with M (arbitrary positive integer).

[0025]

As described above, according to the present invention, there are provided M delay means for delaying each of the M divided standard signals output from the speed conversion circuit by one horizontal scanning time, and the standardized one of the M divided standard signals. A selection circuit for switching and outputting an input signal to the delay means and an output signal to the delay means for each of a plurality of divided standard signals which are the same field in distinguishing between the television synchronization signal and the odd or even field, and a standard television. A first adder for adding an input signal to the delay unit and an output signal of the delay unit to each of a plurality of divided standard signals which are different fields in differentiating the synchronization signal from the odd or even field, and selecting a plurality of selection circuits By providing a selection signal generation circuit for generating a signal and a second adder for adding a plurality of selection circuit outputs and a plurality of first adder outputs, a sense of discomfort in motion is reduced. And it is possible to get a good standard scan speed video signals S / N.

Further, by inverting the field state of the output of the M × speed digital camera with the field of the external standard television synchronizing signal, the vertical frequency of the standard scanning speed video signal which is the second adder output is obtained. The characteristics can be improved and the image quality can be improved. Further, by providing a coefficient multiplier for multiplying the coefficient by an arbitrary coefficient at each stage before the input of the second adder, it is possible to obtain a standard speed video signal with further improved vertical frequency characteristics.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a high-speed camera system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a high-speed camera system according to Embodiment 2;

FIG. 3 is a block diagram showing a configuration of a high-speed camera system according to Embodiment 3;

FIG. 4 is a view showing the operation principle of the high-speed camera system according to the first embodiment;

FIG. 5 is a timing chart showing the operation of the high-speed camera system according to the second embodiment;

FIG. 6 is a view showing the operation principle of the high-speed camera system.

FIG. 7 is a principle diagram of line addition when M is an even number according to the second embodiment of the present invention;

FIG. 8 is a characteristic diagram showing frequency characteristics in the vertical direction according to the third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional high-speed camera system.

FIG. 10 is a timing chart showing the operation of the speed conversion circuit of the high-speed camera system.

FIG. 11 is a block diagram showing a speed conversion circuit in the high-speed camera system.

[Explanation of symbols]

 Reference Signs List 1 M-speed digital television camera 2 Speed conversion circuit 3-5 divided standard signal 6 Delay means 7 Selection circuit 8 First adder 9 Second adder 10 Selection signal generation circuit 11 Coefficient unit 12 Standard output 13 Arbitrary α Coefficient multiplier to multiply 14 Coefficient multiplier to multiply by any β 15 Coefficient multiplier to multiply by any gamma 16 M-speed signal 17 Write / read control circuit 18 Field memory

Continuation of the front page (56) References JP-A-59-221813 (JP, A) JP-A-8-102871 (JP, A) JP-A-7-288717 (JP, A) JP-A-62-135081 (JP) , A) Japanese Patent Publication No. 5-54315 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/225-5/247 H04N 5/14-5/217

Claims (3)

(57) [Claims] 1. Genlocked by an external standard television synchronization signal, the standard television M
An M-times digital television camera that performs scanning at double speed (M is an arbitrary positive integer); and an output signal of the M-times digital television camera,
A speed conversion circuit that divides each of the field units at a scanning speed of M times, time-expands each to a standard scanning speed, and synchronizes and outputs the M divided standard signals; M number of delay means for delaying one standard horizontal scanning time, and a plurality of divided standard signals which are the same field in distinguishing the standard television synchronization signal and the odd field or the even field from the M divided standard signals To
A selection circuit for individually switching and outputting an input signal to the delay means and an output signal of the delay means; and among the M divided standard signals, the standard television synchronization signal and an odd field or an even field. A first adder for individually adding a plurality of divided standard signals, which are fields different in distinction, to an input signal to the delay unit and an output signal of the delay unit; and a selection signal to the plurality of selection circuits. A high-speed camera system comprising: a selection signal generating circuit that generates a signal; and a second adder that adds outputs of the plurality of selection circuits and outputs of the plurality of first adders. 2. The high-speed digital television camera according to claim 1, wherein the state of the odd field and the even field of the output of the M × speed digital television camera is inverted with respect to the field of an external standard television synchronization signal. Speed camera system. 3. The high speed apparatus according to claim 1, further comprising M coefficient multipliers each multiplying an output of the plurality of first adders and an output of the plurality of selection circuits by an arbitrary coefficient. Camera system.