JPH02226972A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To realize wiping and fade when a magnified picture is synthesized onto other picture by providing a subtractor taking subtraction between an output of a magnification processing circuit and an input video signal, a coefficient device multiplying a coefficient to be controlled with an output of the subtractor and an adder adding output of the coefficient device to the above- mentioned video signal. CONSTITUTION:When a coefficient data DK to a multiplier 20 is switched at 0 and 1 level synchronously with a horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) from a timing controller 8, a synthesis video signal giving a moving picture according to an input video signal in one portion of a still picture storing part of the screen is obtained. Moreover, when the coefficient data DK is set to 1/2, for example, a synthesis video signal forming a multiple pattern comprising the stored still picture and the moving picture depending on the input video signal is obtained. Furthermore, when the switching timing of 0, 1 level of the coefficient data DK is switched timewise, the screen switching by wiping is attained and the screen switching by fade is attained by varying the coefficient data DK timewise from 0 to 1 or vice versa.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing circuit, and particularly to a video signal processing circuit having a function of enlarging an image.

[Prior Art] Conventionally, video signal enlargement processing has generally been achieved by using a random access memory (RAM) and controlling its read address according to a predetermined program. Furthermore, Ganto Motobatake previously filed an application for a method for realizing the above-mentioned enlargement process using a so-called first-in-first-out memory (hereinafter referred to as FIFO).
(Patent Application No. 17413/1983).

[Problems to be Solved by the Invention] By the way, it is conceivable that a screen subjected to such enlargement processing can be viewed alone, but a very interesting screen can be obtained by combining it with other screens.

Furthermore, by combining processing such as quizzes and fades on the enlarged screen, even more diverse image effects can be obtained.

However, the reality is that such processing is generally installed in business equipment but not in home consumer equipment. The reason for this is that in order to perform the above processing, a processing circuit for image enlargement, an image processing circuit for compositing this image, and a processing circuit for wiping or fading each of these are required, which requires a large circuit scale. This is because the amount becomes enormous.

Against this background, it is an object of the present invention to provide a video signal processing circuit that has a simple circuit configuration and is capable of wiping and fading an enlarged image when compositing it with another image. .

[Means for Solving the Problems] For the above purpose, the video signal processing circuit of the present invention includes an enlargement processing circuit capable of forming an enlarged image using a memory capable of storing a video signal for one screen; a subtracter that takes the difference between the output of the enlargement processing circuit and the input video signal; a coefficient multiplier that multiplies the output of the subtracter by a controllable coefficient; and an adder that adds the output of the coefficient multiplier to the video signal. The structure includes the following.

[Function] By configuring as described above, all the compositing, fading, and wiping of the image corresponding to the input video signal and the enlarged image can be realized simply by controlling the coefficients of the coefficient multiplier, and no complicated processing circuit is required. There's no need.

E example] Two embodiments of the present invention will be described below.

FIG. 1 is a block diagram showing the configuration of a video signal processing circuit as an embodiment of the present invention, and a digital video signal obtained by digitizing a playback signal etc. from a VTR is supplied to an input terminal indicated by 2 in the figure. has been done. It is assumed that all the components in the numbered part of the first figure handle multi-bit digital signals.

First, the normal operation of the processing circuit of FIG. 1, ie, the operation when acting as a noise reduction circuit, will be described.

In this case, the switch 4 is connected to the output terminal 26 side of this processing circuit by a control signal generated from the system controller 30 in response to the operation of the operation unit 32, and the video signal output to the output terminal 26 is switched. When data is input as write data (WD) to PIFO 6, which has a capacity for one field, through 4, PIFO 6 always writes and reads data, and immediately after the reset timing of the read address, the write address is reset. Reset timing is set.

This causes FIFO 6 to function simply as a one-field delay circuit.

Further, the switch 14 is always connected to one horizontal period delay line (IHDL) by a control pulse CP from the timing controller 8 controlled by the system controller 30.
The output of the FIFO 6 without passing through the subtracter 16 is inputted to the subtracter 16. The subtracter 16 takes the difference between the input video signal and the video signal one field before it, and supplies the resulting signal, which is the sum of the noise component and the motion component, to the subsequent circuit.

Furthermore, the switch 22 is controlled by the system controller 30.
It is connected to the nonlinear circuit 18 side, and this nonlinear circuit 1
8 is supplied to an adder 24. This nonlinear circuit 18
For example, when one input novel is less than a predetermined value, it is multiplied by a predetermined coefficient K (1>K>O), and when it is greater than the predetermined value, it is configured to output a value corresponding to the predetermined value. The coefficients of the nonlinear circuit 18 are set to values close to 1, and the configuration is such that noise components below a predetermined value are output, but components corresponding to image movement beyond that value are not output. Therefore, the video signal output from the adder 24 is a signal obtained by subtracting only the noise component from the video signal from the input terminal 2.

Next, the operation when the processing circuit shown in FIG. 1 is used for still image reproduction of a VTR will be described. At this time, the writing of the above-mentioned PIFO 6 is stopped at the timing when still image playback is commanded, and the same screen is repeatedly read out from the FIFO 6, and the switch 14 is
The output of PIFO 6 without passing through HDL 12 is supplied to subtracter 16 . Further, the switch 22 is connected to the multiplier 20 side. The coefficient of this multiplier 20 is determined by the system controller 3.
It is controlled by coefficient data (DK) from the coefficient control circuit 28 which is controlled by 0. During still image playback, this coefficient data DK is always set to 1, and this multiplier 20
The output of is the same as the output of the subtracter 16. Therefore, in the adder 24, the input signals are canceled out, and the still image signal output from the PIFO 6 is output from the output terminal 26.

In this state, if the coefficient data DK to the multiplier 20 is switched between O and 1 in synchronization with the horizontal synchronization signal (HD) and vertical synchronization signal (VD) from the timing controller 8, part of the screen It is possible to obtain a composite video signal in which the still image is stored and the other parts are moving images that follow the input video signal. Furthermore, by setting the coefficient data to a DKlk station, for example, it is possible to obtain a composite video signal that is a multiplexed screen of a stored still image and a moving image according to the input video signal. Furthermore, if the switching timing between O and 1 of the coefficient data DK is changed over time, it is possible to change the screen by wiping, and the value of the coefficient data DK can be changed from 0 to 1 or from 1 to 0 over time. For example, it becomes possible to switch screens by fade.

Next, an explanation will be given of image enlargement processing according to the present invention, as well as compositing, wiping, fading, etc. of an enlarged screen obtained by this enlargement processing with another screen.

Figure 2 shows the constituent countries used to explain this process.
3 and 4 are timing charts for explaining the processing timing of the PIFO 6 when enlarging an image, and FIG. 3 shows the vertical scanning timing. FIG. 4 shows the processing timing with respect to the horizontal scanning timing.

The synchronization separation circuit 10 separates a vertical synchronization signal (VD) and a horizontal synchronization signal (HD) from the input signal from the terminal 2.
These synchronization signals VD and HD determine the timing of each antibacterial signal output by the timing controller 8.

In Figure 3, VD is the vertical synchronization signal and WE is the PI
FO6 is a write enable signal, RE is a read enable signal, WR is a write reset signal, RR is a read reset signal, WD is write data, and RD is read data.

Now, assume that the area a on the screen shown in FIG. 2 is to be enlarged. As shown in FIG. 3, the write enable signal W E i is set to a high level (H) that enables writing during the period when the video signals corresponding to areas a and A in FIG. 2 are input. During the other periods, it is at a low level (L) which disables writing, and only the video signals corresponding to the areas A and S are written into the PIFO 6. To explain more precisely, the write enable signal WE changes to H at the timing when the point indicated by X in FIG. 2 is being scanned, and changes to L after the repair field. The timing at which this write enable signal WE changes to H is the timing shown by X in FIGS. 3 and 4. On the other hand, the write reset signal WR is a signal that has a pulse during a certain period (in the example of FIG. 3, in synchronization with the vertical synchronization signal) when the write enable signal is applied once every two fields, and
The write clock WC to PIFO6 is the same clock as when it acts as a noise reduction circuit.
has a capacity corresponding to one field's worth of video signals, then the video signal data corresponding to the areas A and A are written for two fields in a two-field period. It will continue to be lost. Note that the numerical values in the schematic diagram of the write data WD in FIG. 3 are field numbers, and the shaded area indicates a period in which there is no write data. Also, the fourth
a and b in the schematic diagram of write data WD in the figure.

C indicates video signal data corresponding to areas a, b, and c in FIG. 2, respectively.

On the other hand, the read clock RC at this time is the write clock W.
The frequency is set to the frequency of station C, and two fields are read out from the FIFO 6 with the time axis expanded twice in a two-field period. In this way, read clock R
Since the frequency of C is 4 times the frequency of the write clock WC, the read enable signal RE must be H for twice as long as the write enable signal WE, and is H for all periods except the vertical synchronization period. . The read reset signal RR is a signal that has a pulse once every two fields in synchronization with the vertical synchronization signal and at the timing of operating the upper left corner in Figure 2. Read data RD as shown is obtained. That is, F
In the read data from the IFO 6, only the upper left corner and the scanning line that scans the area in FIG.
In addition, a video signal corresponding to area A and a video signal corresponding to area A are alternately included every l horizontal scanning period.

CP in FIG. 4 indicates a control pulse supplied from the timing controller 8 to the switch 14; , becomes L during the horizontal scanning period when the video signal data corresponding to the area is output.
When it is H, it is connected to the I HDL L2 side, and when it is H, it is connected to the other side.

Therefore, from this switch 14, one horizontal scan of video signal data corresponding to area a is repeatedly output twice. Therefore, the video signal output from this switch 14 is a video signal showing an image obtained by enlarging the image in area a in FIG. 2 twice.

Next, various forms of outputting the enlarged image obtained as described above will be explained. First, if you want to output the enlarged image alone, connect switch 4 to the input side and switch 2.
2 is connected to the multiplier 20 side, and the coefficient data DK is always set to 1. As a result, the input signals are canceled out in the adder 24, and the enlarged image signal output from the switch 14 is output from the output terminal 26.

Further, if it is desired to output this enlarged image as a still image, writing to the FIFO 6 is stopped. Further, the read reset signals R and R of the PIFO 6 are made to be signals containing pulses for each field. As a result, the switch 14 repeatedly outputs an enlarged signal of the same screen. The other operations are the same as when viewing the enlarged image alone.

Next, a case will be described in which the enlarged image and the input image are wiped or faded. From switch 14,
While the enlarged image of the input image or the enlarged image of the still image is being output, the coefficient data DK to the multiplier 20 is synchronized with the horizontal synchronization signal (HD) and vertical synchronization signal (VD) from the timing controller 8. By switching between 0 and 1, it is possible to obtain a composite video signal in which part of the screen is an enlarged image and the other part is a moving image according to the input video signal. Also, for example, if the coefficient data DK is set to 坏,
It is possible to obtain a composite video signal that is a multiplexed image of an enlarged image and a moving image according to the input video signal. Furthermore, if the switching timing between 0 and 1 of the coefficient data DK is changed over time, it is possible to change the screen by wiping, and the value of the coefficient data DK can be changed over time from O to 1 or from 1 to O. For example, it becomes possible to switch screens by fade.

These image compositions can be performed in the same way whether the enlarged image is a still image or a video, and especially when the enlarged image is a video, it is possible to combine a normal screen and a video for the same screen. This makes extremely effective image synthesis possible. For example, it is also possible to obtain an image signal corresponding to a composite screen as shown in FIG. 5(B) from an input image signal corresponding to an image as shown in FIG. 5(A).

Also, while the switch 14 is outputting the enlarged image,
By connecting the switch 4 to the output terminal 26 for one field period and stopping writing to the FIFO 6 at the same time as the end of this period, it is possible to obtain a still image that is a further enlarged image.

According to the video signal processing device of the embodiment described above, with a simple circuit configuration, noise reduction processing, still image output processing, image composition processing, wipe, fade, image enlargement processing, still image output processing of enlarged image, and enlargement can be performed. It has become possible to realize a wide variety of processes such as image synthesis processing using images, wipe 5 using enlarged images, fading using enlarged images, and image re-enlargement processing with the same circuit configuration.

Note that for still image output processing, image composition processing, wipe, fade, image enlargement processing, image composition processing using enlarged images, wipe using enlarged images, and fade using enlarged images, data is sent from PIFO 6 to adder 24. The present invention includes all such configurations.

[Effects of the Invention] As described above, according to the video signal processing circuit of the present invention, the circuit configuration is simple, and wipe and fade can be realized when an enlarged image is combined with another image. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a video signal processing circuit as an embodiment of the present invention, FIG. 2 is a schematic diagram for explaining the enlargement process by the processing circuit of FIG. 1, and FIGS. FIG. 5 is a timing chart for explaining the operation of each part of the circuit of FIG. 1 during enlargement processing, and FIG. 5 is a diagram showing an example of a special screen obtained by the circuit of FIG. 1. In the figure, 2 is an input terminal, 4 is a switch, 6 is an IFO having a capacity for one field, 8 is a timing controller, 10 is a synchronous separation circuit, and 12 is an IHDL. 14 is a switch, 16 is a subtracter, 18 is a nonlinear circuit, 20 is a multiplier, 24 is an adder, 26 is an output terminal, 28 is a coefficient control circuit, 30 is a system controller, and 32 is an operating section. Figure 3

Claims (3)

[Claims] (1) An enlargement processing circuit capable of forming an enlarged image using a memory capable of storing a video signal for one screen, a subtracter that takes the difference between the output of the enlargement processing circuit and the input video signal, and A video signal processing circuit comprising: a coefficient multiplier for multiplying an output by a controllable coefficient; and an adder for adding the output of the coefficient multiplier to the video signal. (2) The video signal processing circuit according to claim (1), wherein the input video signal and the output of the adder can be selectively supplied as input signals to the memory. . (3) The coefficient multiplier selectively operates between a first coefficient multiplier that multiplies a variable coefficient determined regardless of the input level, and a second coefficient multiplier that multiplies a coefficient determined according to the input level. The video signal processing circuit according to claim (2), characterized in that it can be used for.