JP3271443B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging device compatible with a next-generation television system.

[0002]

2. Description of the Related Art In the next-generation television system, in order to pursue higher image quality in the vertical direction and a wider screen with an aspect ratio of 16: 9, HDTV (1125 scanning lines interlaced scanning) and second-generation EDTV ( Television systems such as 525 scanning lines (sequential scanning) are being promoted.

[0003] As described above, when the aspect ratio is changed from the conventional 4: 3 to 16: 9 and the imaging apparatus of the progressive scanning is used,
A signal having a wider band than that of a conventional image pickup apparatus must be handled, and not only the image pickup apparatus and display but also a signal processing circuit requires a dedicated circuit different from a video signal processing apparatus of a standard television system. In particular, video signal processing circuits have recently been digitized, and most of these circuits have been converted to LSL. When the screen is widened and sequentially scanned, the clock frequency of a circuit for performing digital processing of a video signal increases, so that an arithmetic circuit such as a multiplier, an adder, and a memory must be speeded up.

Therefore, in a video signal processing apparatus in which the screen is widened and further sequentially scanned, in order to digitally process the video signal, a dedicated digital processing circuit or LSI must be developed in consideration of the speed of the arithmetic circuit. However, there is a problem that the development cost increases.

For this reason, when constructing a video signal processing device compatible with a television system in which the screen is widened and further scanned sequentially, development costs are reduced by sharing the circuit and LSI of the conventional video signal processing device for a standard television. Recently, there has been proposed a method of providing an inexpensive wide-screen video signal processing device capable of reducing the image quality and outputting a conventional interlace signal.

Hereinafter, a conventional wide-screen progressive scanning imaging apparatus will be described with reference to FIGS.

In FIG. 3, a signal photoelectrically converted by an image sensor 23 is converted into a black level by a black balance or the like, a white level by a white balance or the like, and a penny processing by an analog signal processing circuit group (analog process circuit) 24. Is applied. This analog signal is converted into a digital signal by the AD converter 25 at the subsequent stage. The output signal of the AD converter 25 is input to a line division / time extension circuit group 26, and the sequentially scanned image pickup signal is converted into a signal sequence of odd lines (1, 3, 5,... The signal is divided into signal lines of even-numbered lines (second, fourth, sixth,...) Scanning lines, and each signal sequence is time-expanded from one horizontal scanning time of the sequential scanning system to one horizontal scanning time of the interlace scanning system, and interlaced scanning is performed. It is output at the same timing in synchronization with the horizontal scanning of the system.

The operation of the line division / time extension circuit group 26 will be described with reference to FIGS.

The line dividing / time extending circuit group 26 is shown in FIG.
As shown in (a) of FIG. As shown in the timing chart of FIG. 11B, the 1H memory A37 writes the odd-numbered lines (1, 3, 5,...) Of the input signal of the sequential scanning system and delays one horizontal scanning period of the sequential scanning system. The data is read out at two-half horizontal scanning period of the sequential scanning system, that is, one horizontal scanning period of the interlaced scanning system at half the frequency of writing, thereby performing time expansion. The 1H memory B 38 writes the even-numbered lines (2, 4, 6,...), And simultaneously starts writing at the half frequency of the writing, for two horizontal scanning periods of the sequential scanning system, that is, one horizontal scanning of the interlaced scanning system. The time is extended by reading over a period. Thus, the line division / time extension circuit group 26
The input signal is divided into an odd-line signal sequence and an even-line signal sequence, and time expansion is performed in synchronization with the interlaced scanning system, so that the digital signal processing circuit groups 27 and 28 at the subsequent stage correspond to the conventional television system. The video signal processing circuit described above can be used.

The time-expanded two signal sequences are input to digital signal processing circuit groups 27 and 28, respectively.
Various digital processes such as a gamma correction, a blanking process, a matrix process, a vertical / horizontal contour correction process, and the like are performed, and output as a luminance signal and a color difference signal.

The digital signal processing circuit groups 27 and 28
FIG. 5 shows an example of the configuration of the vertical contour correction processing of FIG.

The R, G, and B image signals input from a pre-stage signal processing circuit (not shown) are supplied to 1H delay lines 39, 40, and 4 that delay the input signals by one horizontal scanning period.
1 and is delayed by one horizontal scanning period of the interlaced scanning system. The R and G image signals delayed by one horizontal scanning period by the 1H delay line are further input to the next 1H delay lines 42 and 43, respectively, and are delayed from the input by a total of two horizontal scanning periods. The R and G image signals that have not been delayed (0H delay) are added by the adder 44 to become a 0H delay high-frequency luminance signal.

Delayed by one horizontal scanning period (1H delay)
The R and G image signals are added by an adder 45 to become a 1H delayed high-range luminance signal. Then, the R and G image signals delayed by two horizontal scanning periods (2H delay) are added by the adder 46 to become a 2H delayed high-frequency luminance signal.

The 0H and 2H high-frequency luminance signals are added by an adder 47 for forming a 1H- (0H + 2H) / 2 band-pass filter (BPF) for a vertical contour correction signal, and the (0H + 2H) / 2 vertical signals are added. It is output as a BPF creation signal. In order to configure a low-pass filter (LPF) for a horizontal contour correction signal, the selector 48 sets (0H +
2H) / 2, 0H, 1H, 2H, one system signal is selected by the vertical LPF selection signal from the high-frequency luminance signal, and the vertical LPF is selected.
It is output as a creation signal. The R, G, and B imaging signal outputs of the contour emphasizing signal creation processing unit are vertical BPF, LPF
R, G, and B image signals delayed by 1H are output in order to make the phase of the center signal coincide with that of the center signal in the vertical direction.

As described above, the digital signal processing circuit group 2
The two signal sequences digitally processed in 7 and 28 are as follows:
The time compression and line synthesizing circuit group 29 is time-compressed from one horizontal scanning time of the interlaced scanning system to one horizontal scanning time of the sequential scanning system so that each signal sequence has a phase relationship before time expansion, and is subjected to one-system signal. Line synthesis is performed as a signal. The output signal of the time compression / line synthesis circuit group 29 is D
The signal is converted into an analog signal by the A converter 30 and output as a sequential scanning signal.

On the other hand, the digital signal processing circuit groups 27, 2
The two signal sequences digitally processed in 8 are also input to the pixel synthesizing circuit group 31. The pixel synthesizing circuit group 31 adds the odd-numbered line signal series and the even-numbered line signal series and outputs a signal of one system. The aspect ratio conversion circuit group 32 converts the signal having the aspect ratio of 16: 9 to the aspect ratio of 4: 3. Is converted to a signal. Aspect ratio conversion circuit group 32
Is converted into an analog signal by the DA converter 33, and an interlaced scanning signal is obtained.

The digital signal processing circuit groups 27, 2
The two signal sequences digitally processed in 8 are input to the color difference signal VLPF circuit group 34. The color difference signals of the two signal sequences are the (n-1) th line signal delayed by one horizontal scanning time in the interlaced scanning system by the 1H delay line, and the nth and (n + 1) th line signals input simultaneously. The line is subjected to a 1: 2: 1 vertical low-pass filter process, and is output as one system signal. The luminance signals of the two signal sequences are output as they are after being delayed by one horizontal scanning period of the interlaced scanning system. Color difference signal VLP
The two-system luminance signal output and one-system color difference signal output of the F circuit group 34 are input to the mapping circuit group 35.

In the mapping circuit group 35, one system of the luminance signal and the chrominance signal are time-compressed in order to transmit the signal system of the total of three systems of the two systems of the luminance signal and one system of the color difference signal as the two systems of the optical fiber. The remaining one system of the luminance signal is an odd-numbered pixel (1, 3, 5,...
, And even-numbered pixels (second, fourth, sixth,...) Pixels, and time-compresses the two-system signal sequences obtained by the pixel separation, and inserts them into the non-signal portions of the time-compressed luminance signal and color difference signal. Mapping by using

The output signals of the two systems of the mapping circuit group 35 are parallel-to-serial converted in the optical transmission section, transmitted as optical signals as optical signals through an optical fiber, serial-to-parallel converted on the receiving side, and de-mapping circuit groups 36. Is input to The de-mapping circuit group 36 separates a luminance signal, a color difference signal, an augmented signal divided into odd-numbered pixels and even-numbered pixels from the signals of the two systems, and combines the signals of the odd-numbered pixels and the even-numbered pixels into one system. Are time-expanded and output as a luminance signal, a color difference signal, and a reinforcement signal for interlaced scanning.

[0020]

However, in the above-mentioned conventional wide-screen progressive scan imaging apparatus, since the conventional digital signal processing circuit group is used, an interlace scan signal, a progressive scan signal, an interlace scan signal + reinforcement is used. A dedicated special processing circuit group using a 1H delay line is required to obtain an output signal form suitable for various devices such as signals, and the circuit scale and the cost of the imaging device are reduced by using an expensive general-purpose memory. growing. Even if each process is developed as a dedicated LSI, development costs are required for each LSI,
There was a problem that the development cost increased.

The present invention solves such a conventional problem. In a progressive scanning image pickup apparatus compatible with a wide screen, a one horizontal scanning period delay circuit used for generating a vertical contour correction signal of a digital signal processing circuit group. Aiming to provide an image pickup device that realizes a line division and time extension circuit with only a small-scale circuit increase by using a peripheral circuit and does not require a dedicated development cost, and enables an inexpensive LSI. And

[0022]

In order to achieve the above object, an image pickup apparatus according to the present invention comprises first and second storage means for holding an image signal for one horizontal scanning period, and writing and reading of the storage means. A storage means control unit for arbitrarily controlling
A first signal switching circuit for receiving an input image signal and an output signal of the first storage means and outputting a selected signal to the second storage means; an output signal of the second storage means and an external signal; A second signal switching circuit for inputting an arbitrary signal to be output to the second storage device, outputting a selected signal, a first output device for outputting an output signal of the first storage device, and a second signal switching circuit. Second output means for outputting a signal selected by the circuit, wherein the first signal switching circuit outputs the output signal of the first storage means, and the second signal switching circuit outputs the output signal to the outside. An arbitrary signal to be output is output, and the input image pickup signal (0H delay signal) is delayed by one horizontal scanning period in the first storage unit under the control of the storage unit control unit, and is delayed by one horizontal scanning period (1H delay signal). Signal), and converts the 1H delayed signal to the second delayed signal. It said second memory means further one horizontal scanning period delay to two horizontal scanning periods delayed signals from the input by the control of the storage control unit (2H delay signal)
And a vertical contour emphasizing signal is created from the 0, 1, 2H delay signal and output from the second output means, and the 1H delay signal is output from the first first output means. An edge enhancement signal generating circuit, wherein the first signal switching circuit outputs an input image signal, the second signal switching circuit outputs an output signal of the second storage means, and the control means controls the storage means. The operation of the unit is switched so that the input image signal is written to the first storage means when the input image signal is an odd line, and the input image signal is written to the second storage means when the input image signal is an even line. Controlling the first and second storage means to perform a write operation alternately every one horizontal scanning period.
The signal written in the storage means is controlled so that the read operation is performed simultaneously over two horizontal scanning periods at half the frequency at the time of writing, and the output signal of the first storage means is changed to the first signal. An output signal from the output means, and an output signal from the second storage means from the second output means.
And a second output means for outputting a two-system signal sequence, thereby outputting an odd-line signal sequence and an even-line signal sequence which are time-expanded during two horizontal scanning periods. It is provided with.

The image pickup apparatus of the present invention further comprises a pixel division circuit for dividing an input image pickup signal for each pixel and outputting a two-system signal sequence, and a first system signal sequence output from the pixel division circuit. And 1 for each of the signal sequences of the second system
First and second storage means for holding an image signal during a horizontal scanning period, a storage means control unit for arbitrarily controlling writing and reading of the storage means, an output signal of the pixel division circuit and the first storage A first signal switching circuit for receiving an output signal of the means and outputting a selected signal to the second storage means; and a first signal switching circuit for each of the first and second signal sequences divided for each pixel. The output signal of the storage means is input,
A second signal switching circuit that outputs a selected signal, and an output signal of a second storage unit for each of the first and second signal sequences divided for each pixel are input, and the selected signal is output. A third signal switching circuit for outputting, a fourth signal switching circuit for receiving an output signal of the second signal switching circuit and an arbitrary signal to be output to the outside, and outputting a selected signal;
A first output unit that outputs an output signal of the second signal switching circuit; and a second output unit that outputs an output signal of the fourth signal switching circuit. The input image pickup signal is output as it is without performing the pixel division operation, the output signal of the first storage means is output by the first signal switching circuit, and the signal of the first system is output by the second signal switching circuit. The third signal switching circuit outputs a second signal sequence output signal, and the fourth signal switching circuit outputs an arbitrary signal to be output to the outside. The input image signal (0H delay signal) is delayed by one horizontal scanning period in the first storage unit under the control of the storage unit control unit to obtain a one horizontal scanning period delay signal (1H delay signal). Under the control of the storage means control unit in the second storage means Further, a signal (2H delay signal) delayed by one horizontal scanning period from the input and delayed by one horizontal scanning period is obtained, a vertical contour emphasis signal is created from the 0, 1, 2 delay signals, and the 1H delay signal is output. A vertical contour emphasizing signal generating circuit for dividing the input image signal into two signal sequences for each of odd-numbered pixels and even-numbered pixels by the pixel dividing circuit, thereby halving the frequency of the input image signal. The first signal switching circuit outputs an input imaging signal for each of the two signal sequences, and the fourth signal switching circuit outputs an output signal of the third signal switching circuit;
The operation of the storage means control unit is switched to write the input imaging signal to the first storage means when the input imaging signal is an odd line, and to input the input imaging signal to the second storage means when the input imaging signal is an even line. In order to write an image signal, the first
And the second storage means are controlled so as to perform the writing operation alternately every one horizontal scanning period, and the signals written in the first and second storage means are output at a frequency which is 1/2 the frequency at the time of writing. Control is performed so that the reading operation is performed simultaneously over the horizontal scanning period, and the two-system signal sequence of the odd-numbered line and the even-numbered line is time-extended. The odd lines thus obtained are combined so as to form a single-system signal sequence, and the even lines divided for each pixel into odd-numbered pixels and even-numbered pixels by the third signal switching circuit are similarly formed into a single-system signal sequence. By outputting the image signal, the number of effective pixels in one horizontal scanning period can correspond to a signal exceeding the number of pixels in the storage means. To Those having a line division and time expansion circuit and outputting the extended time split to two horizontal scanning periods.

[0024]

According to the present invention, the operation of the 1H memory and the peripheral circuit used for generating the vertical contour correction signal of the digital signal processing circuit is switched to perform the line division / time extension operation, and the 1H memory is shared, so that each function is provided. In addition, there is an effect that it is possible to configure three lines of line dividing / time extending circuits which can be implemented at low cost without requiring development costs.

Further, according to the present invention, the operation of the 1H memory and peripheral circuits used for generating the vertical contour correction signal of the digital signal processing circuit is switched to perform pixel division, line division / time extension, and pixel synthesis operation. Even in an image pickup apparatus in which the number of effective pixels in one horizontal scanning period exceeds the number of pixels in the 1H memory by sharing the 1H memory, the input signal is divided into n-system signals for each pixel, and divided after line division / time extension. By combining the pixels so that they are in the previous order, 1
This has the effect that it is possible to configure a line division / time extension circuit that can be implemented in an inexpensive manner without requiring a development cost for each function and corresponding to n times the number of pixels of the H memory.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the image pickup apparatus according to the first embodiment of the present invention. In FIG.
1, 2, 3, 4, 5, and 6 delay an image signal by one horizontal scanning period (1H), and 1H memory capable of controlling writing and reading separately, and 7 generate control signals for the 1H memories 1 to 6. 1H memory control circuit, 8, 9, 10, 11
Is an adder, 12 is a selector for outputting an arbitrary signal among the four signal inputs from the adders 8 to 11, 13, 14, 1
Reference numerals 5, 16, 17, and 18 denote selectors that output any one of the two signal inputs.

The operation of the first embodiment of the present invention as a vertical contour emphasizing signal generating circuit will be described below.

In FIG. 1, the R, G, and B imaging signals input to the input terminals a, b, and c from the preceding signal processing unit (not shown) are input to the 1H memories 1, 2, and 3, respectively. 1
The H memories 1, 2, and 3 are controlled by a 1H memory control circuit 7 to delay the input signal by 1H.

1H 1H output from memories 1, 2, and 3
The delayed R, G, B image signals are supplied to selectors 13, 14,
15 is input. R, G, and B image signals that are not delayed (0H delay) and R, G, and B image signals that are delayed by 1H are input to the selectors 13, 14, and 15, respectively.
Only the 1H delay signal is output.

The output signals of the selectors 13, 14, and 15 are input to the 1H memories 4, 5, and 6, respectively. The 1H memories 4, 5, and 6, like the 1H memories 1, 2, and 3, are controlled by the 1H memory control circuit 7 to delay the input signal by 1H. R delayed by 2H from 1H memories 4, 5, 6;
G and B imaging signals are output. The R, G, and B image signals delayed by 1H are input to the selectors 16, 17, and 18. R, G, and B imaging signals delayed by 2H, vertical BPF and LPF creation signals, and a shading correction signal created by a shading correction circuit (not shown) are input to the selectors 16, 17, and 18, respectively. Only the vertical BPF, LPF creation signal and shading correction signal are output.

The operation of the adders 8, 9, 10, 11 and the selector 12 is exactly the same as that of the conventional vertical contour emphasizing signal generating process, and therefore their operations are also the same, and the description of the operations is omitted.

In this manner, the same operation as that of the conventional vertical contour emphasizing signal generating circuit can be obtained.

Next, the operation of the line dividing / time extending circuit will be described. The R, G, B image signals of the sequential scanning system inputted from the input terminals a, b, c are inputted to the 1H memories 1, 2, 3 and the selectors 13, 14, 15. Selector 1
Reference numerals 3, 14, and 15 output R, G, and B imaging signals from input terminals a, b, and c. The R, G, B imaging signals output from the selectors 13, 14, 15 are input to the 1H memories 4, 5, 6. 1H memories 1, 2, 3 and 1H memories 4, 5,
6 is controlled by a 1H memory control circuit 7 to alternately write an input signal every 1H and to simultaneously read out the input signal at half the writing frequency.

The 1H memories 1, 2, and 3 write the odd lines (1, 3, 5,...) Of the input signal, delay 1H of the sequential scanning system, and operate at the frequency of 1/2 of the writing with the sequential scanning system. Horizontal scanning period, that is, 1 of interlaced scanning system
Reading is performed at the same timing over the horizontal scanning period and in synchronization with the horizontal scanning of the interlaced scanning system. The 1H memories 4, 5, and 6 store even lines (2, 4, 6,...) Of input signals.
The second line) is written, and at the same time as the start of writing, over two horizontal scanning periods of the sequential scanning system, that is, one horizontal scanning period of the interlaced scanning system at half the frequency of the writing, and in synchronization with the horizontal scanning of the interlaced scanning system. Reading is performed at the same timing.

The selectors 16, 17, and 18 are controlled so as to output the output signals of the 1H memories 4, 5, and 6. The adders 8, 9, 10 and the selector 12 are irrelevant to the operation as the line dividing / time extending circuit.

In this manner, an operation similar to that of the conventional line dividing / time extending circuit can be obtained.

As described above, according to the first embodiment of the present invention, in an image pickup apparatus adapted for progressive scanning, a 1H memory and a peripheral circuit of a vertical contour emphasizing signal generating circuit of a digital signal processing circuit are used. Switch the operation of
In addition to the conventional vertical contour enhancement signal creation circuit,
It is possible to realize three systems of the time extension circuit, and to obtain a signal processing configuration which can be implemented at low cost without requiring a special development cost.

Further, in the first embodiment, the image signal of progressive scanning is used as an input signal. However, the input signal is used as a Hi-Vision signal, and a line division / time extension process not synchronized with the horizontal scanning period of the interlaced scanning system is performed. To convert the input Hi-Vision signal to a frequency that is 1/2 times, so that a video signal processing circuit compatible with a conventional television system can be used in a Hi-Vision imaging device.

Next, an image pickup apparatus according to a second embodiment of the present invention will be described. FIG. 2 is a block diagram illustrating a configuration of an imaging device according to a second embodiment of the present invention.

In FIG. 2, reference numerals 1, 2, 3, 4, 5, and 6 denote an 1H memory for delaying an image signal by 1H, and write and read can be separately controlled, and 7 generates control signals for 1H memories 1 to 6. 1H memory control circuit, 8, 9, 10, 1
1 is an adder, 12 is a selector that outputs an arbitrary signal among the four signal inputs from the adders 8 to 11, 13, 14, 1
Reference numerals 5, 16, 17, and 18 denote selectors for outputting any one of two signal inputs, and reference numeral 19 denotes a first pixel thinning circuit for outputting only odd-numbered pixels (1, 3, 5,...) Of input signals. , 20 are the even pixels (2, 4, 6, 6) of the input signal.
.., A second pixel thinning circuit that outputs
A selector 22 switches the signal sequence of the odd-numbered pixels and the signal sequence of the even-numbered pixels to one signal sequence.

The second embodiment differs from the first embodiment in that a first pixel thinning circuit 19, a second pixel thinning circuit 20, and selectors 21 and 22 are added. The other circuits are the same as those of the first embodiment, and therefore have the same operation and operation. Therefore, the description of the operation is omitted, and the operation of the different parts will be mainly described.

Hereinafter, the operation of the added circuit will be described. In an image pickup apparatus in which the number of effective pixels in one horizontal scanning period exceeds the number of pixels in the 1H memories 1, 2, 3, 4, 5, and 6, the same signal is input to the input terminals a and b.
The signal input from the input terminal a is input to the pixel thinning circuit 19, and outputs only the odd-numbered pixels (1, 3, 5,...). The signal input from the input terminal b is a pixel thinning circuit 2
0, and outputs only even-numbered pixels (2, 4, 6,..., Pixel).

The 1H memory 1 is used when the output signal of the pixel thinning circuit 19 is an odd line, and the 1H memory 4 when the output signal is an even line.
Are written alternately every 1H. Further, the reading is performed simultaneously on the odd-numbered lines and the even-numbered lines. When the output signal of the pixel thinning circuit 20 is an odd-numbered line, the data is written into the 1H memory 2 for each odd-numbered line, and when the output signal is an even-numbered line, the data is written into the 1H memory 5 every 1H.

The 1H memory 1 outputs a signal sequence of odd-numbered pixels on an odd line, and the 1H memory 2 outputs a signal sequence of even-numbered pixels on an odd line. In the selector 21, the signal divided into the two signal sequences of the odd-numbered pixel and the even-numbered pixel is switched so as to be the original one signal sequence (1, 2, 3, 4, 5, 6,... Output. The output signal of the selector 21 is output to the output terminal A as it is. Similarly, 1H memory 4
A signal sequence of odd-numbered pixels on an even-numbered line is output, and 1H
A signal sequence of even-numbered pixels on an even-numbered line is output from the memory 5 and input to the selector 22. Selector 22
Then, the signal divided into two signal sequences of odd-numbered pixels and even-numbered pixels is switched so as to become the original one signal sequence and output. The output of the selector 22 is input to the selector 17 and output to the output terminal E as it is.

As described above, even in an image pickup apparatus in which the number of effective pixels in one horizontal scanning period exceeds the number of pixels in the 1H memory,
One line corresponding to an image pickup apparatus having twice the number of pixels of a 1H memory by dividing and processing an image signal into a two-system signal sequence of odd-numbered pixels and even-numbered pixels and synthesizing the same into the original one-system signal sequence. A division / time extension circuit can be obtained.

Further, the image pickup signal is divided into n signal sequences for each pixel and processed, and the n signal sequences divided for each pixel are switched and combined so as to be one original signal sequence. It is needless to say that this makes it possible to cope with an imaging device having n times the number of horizontal effective pixels of the 1H memory.

Next, the number of effective pixels in one horizontal scanning period is 1H.
The operation as an ordinary vertical contour emphasizing signal generation circuit in an image pickup apparatus having the number of pixels within the memories 1, 2, 3, 4, 5, and 6 will be described.

In FIG. 2, R input from the input terminal a
The imaging signal is input to the pixel thinning circuit 19. The pixel thinning circuit 19 is controlled so as to output an input signal as it is, and the output signal is input to the 1H memory 1. Similarly, since the pixel thinning circuit 20 is also controlled so as to output the input signal as it is, the G imaging signal input from the input terminal b passes through the pixel thinning circuit B20 as it is, and the 1H memory 2
Is input to

The selector 21 receives the outputs of the 1H memory 1 and the 1H memory 2, but outputs the output signal of the 1H memory 1 as it is. The selector 22 receives the output signals of the 1H memory 4 and the 1H memory 5, but outputs the output signal of the 1H memory 5 as it is.

In this manner, the pixel thinning circuits 19 and 20
Can be obtained with the same operation as the conventional vertical contour emphasizing signal generating circuit. In addition, line division and time extension are also performed by the pixel thinning circuits 19 and 20 and the selector 21,
22 is controlled in the same way as the vertical contour emphasizing signal generating circuit, so that the same operation as the three-line dividing / time extending circuit of the first embodiment can be obtained.

As described above, according to the second embodiment of the present invention, a 1H memory and a peripheral circuit of a vertical contour emphasizing signal generating circuit of a digital signal processing circuit are used in a progressive scanning type imaging apparatus. Switch the operation of
By adding a pixel thinning circuit and a selector circuit to the signal path to enable switching, the conventional vertical contour emphasizing signal generation circuit and an imaging device in which the number of effective pixels in one horizontal scanning period exceeds the number of pixels in the 1H memory can be used. It is possible to realize a line division / time extension circuit that can respond, and it is possible to obtain a signal processing configuration capable of inexpensively forming an LSI without requiring a dedicated development cost.

[0053]

As is apparent from the above embodiment, the present invention conventionally realizes a line dividing / time extending circuit using an expensive memory or the like circuit separately from a circuit group necessary for digital signal processing. On the other hand, by adding a selector circuit to the vertical contour emphasizing signal generation circuit of the digital signal processing circuit group and sharing a 1H memory, the control of one LSI is switched to generate the vertical contour emphasizing signal generation circuit. Since both a circuit and a line dividing / time extending circuit can be obtained, an imaging device which is inexpensive and does not require dedicated development costs can be provided.

Further, according to the present invention, one L is added by adding a circuit for dividing a pixel into an odd-numbered pixel and an even-numbered pixel by a pixel thinning circuit and synthesizing a pixel by a pixel synthesizing selector.
Switching the control of SI to create a vertical contour enhancement signal
Since a line division / time expansion circuit can be provided that is compatible with an imaging device in which the number of effective pixels in the horizontal operation period exceeds the number of pixels in the 1H memory, an inexpensive imaging device that does not require dedicated development costs can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an imaging apparatus according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a conventional imaging device.

FIG. 4A is a block diagram showing a configuration of a line division / time extension circuit group of a conventional imaging apparatus; FIG. 4B is a timing chart thereof;

FIG. 5 is a block diagram illustrating a configuration of a vertical contour emphasizing signal generation circuit of a conventional imaging apparatus.

[Explanation of symbols]

 1, 2, 3, 4, 6 1H memory 7 1H control circuit 8, 9, 10, 11 Adder 12 Selector 13, 14, 15, 16, 17, 18 Selector 19 First pixel thinning circuit 20 Second pixel Thinning circuit 21, 22 Selector

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-266672 (JP, A) JP-A-4-299671 (JP, A) JP-A-63-30076 (JP, A) JP-A-3-3 145290 (JP, A) JP-A-4-336885 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/14-5/217 H04N 7/01

Claims (2)

(57) [Claims] A first storage unit for storing an image signal for one horizontal scanning period; a storage unit control unit for arbitrarily controlling writing and reading of the storage unit; an input image signal and the first image signal; The output signal of the storage means is input,
A first signal switching circuit for outputting a selected signal to the second storage means, an output signal of the second storage means and an arbitrary signal to be output to the outside are input, and the selected signal is output A second signal switching circuit; first output means for outputting an output signal of the first storage means; and second output means for outputting a signal selected by the second signal switching circuit. An image pickup apparatus, wherein the first signal switching circuit outputs an output signal of the first storage means, and the second signal switching circuit outputs an arbitrary signal to be output to the outside, and The signal (0H delay signal) is delayed by one horizontal scanning period by the first storage unit under the control of the storage unit control unit to obtain a one horizontal scanning period delay signal (1H delay signal). The storage means is controlled by the storage means control unit. Further, a signal (2H delay signal) delayed by one horizontal scanning period from the input and delayed by one horizontal scanning period is obtained, and a vertical contour emphasizing signal is created and output from the 0, 1, 2H delay signals, and the first signal is output. A vertical contour emphasizing signal generating circuit for outputting the 1H delay signal from the output means, and an input image signal output by the first signal switching circuit;
The second signal switching circuit outputs the output signal of the second storage means, and switches the operation of the storage means control section so that when the input image signal is an odd number line, the input image is stored in the first storage means. A signal is written, and when the input image signal is an even-numbered line, the first and second storage means perform a write operation alternately every one horizontal scanning period so that the input image signal is written to the second storage means. And the signals written in the first and second storage means are controlled so as to simultaneously perform a read operation at half the frequency at the time of writing over two horizontal scanning periods. Outputting an output signal of the storage means from the first output means, outputting an output signal of the second storage means from the second output means,
By outputting two signal sequences from the first and second output means, a line splitting / outputting device outputs two signal sequences of an odd line signal sequence and an even line signal sequence which are time-expanded during two horizontal scanning periods. An imaging device comprising a time expansion circuit. 2. A pixel division circuit that divides an input image signal for each pixel and outputs a two-system signal sequence, a first system signal sequence and a second system signal output from the pixel division circuit. First and second storage means for holding an image signal of one horizontal scanning period for each series, a storage means control unit for arbitrarily controlling writing and reading of the storage means, an output signal of the pixel dividing circuit, A first signal switching circuit which receives an output signal of the first storage means and outputs the selected signal to the second storage means; a first and a second signal sequence divided for each pixel A second signal switching circuit to which an output signal of each of the first storage means is input and which outputs a selected signal; and a second signal switching circuit for each of the first and second signal sequences divided for each pixel. The output signal of the storage means is A third signal switching circuit that outputs a selected signal, a fourth signal switching circuit that receives an output signal of the third signal switching circuit and an arbitrary signal to be output to the outside, and outputs a selected signal An image pickup apparatus comprising: a first output unit that outputs an output signal of the second signal switching circuit; and a second output unit that outputs an output signal of the fourth signal switching circuit. The pixel dividing circuit does not perform the pixel dividing operation, outputs the input imaging signal as it is, outputs the output signal of the first storage means by the first signal switching circuit, and outputs the first signal by the second signal switching circuit. An output signal of a system signal sequence, an output signal of a second system signal sequence in the third signal switching circuit, and a signal to be output to the outside in the fourth signal switching circuit. , The input image signal (0H delay signal) to the first
The one-horizontal-scanning-period delay signal (1H-delay signal) is delayed by one horizontal-scanning-period under the control of the storage-unit control unit in the storage unit, and the 1H-delay signal is controlled by the second storage unit in the control of the storage-unit control unit To obtain a signal (2H delay signal) which is further delayed by one horizontal scanning period from the input and produces a vertical contour emphasis signal from the 0, 1, 2H delay signals and outputs the 1H delay signal. And an input image signal is divided by the pixel division circuit into two signal sequences for each of odd-numbered pixels and even-numbered pixels, and the frequency of the input image signal is reduced by half. The first signal switching circuit outputs an input imaging signal for each of the two signal sequences, the fourth signal switching circuit outputs an output signal of the third signal switching circuit, and Memory The operation of the means control unit is switched so that the input image signal is written into the first storage means when the input image signal is an odd line, and the input image signal is written into the second storage means when the input image signal is an even line. The first and second storage means are controlled so as to perform a write operation alternately every one horizontal scanning period so as to write, and the signal written in the first and second storage means is reduced by 1/100 of the write time. Control is performed so as to simultaneously perform the read operation at twice the frequency and over two horizontal scanning periods to extend the time of the two-system signal sequence of the odd line and the even line. The odd lines divided into pixels are combined so as to form a single signal sequence, and the even lines divided into odd pixels and even pixels by the third signal switching circuit for each pixel are similarly combined with one signal sequence. Become By generating and outputting the image signals, the number of effective pixels in one horizontal scanning period can correspond to a signal exceeding the number of pixels in the storage means. Divided by each 2
An image pickup apparatus, comprising: a line dividing / time expanding circuit for performing time expansion and outputting in a horizontal scanning period.