JPH08289311A - Image pickup device - Google Patents

Abstract

PURPOSE: To provide a color difference VLPF circuit just with addition of a small scale circuit by making use of a single-horizontal scanning period delay circuit used for production of contour emphasizing signals and a peripheral circuit. CONSTITUTION: A contour emphasizing signal production circuit delays the input signals 1, 2 and 3 by 1H through the 1H memories 1, 2 and 3 and then delays again the input signals by 1H through the 1H memories 4, 5 and 6. These delayed signals are used as the output signals, and the contour emphasizing signals are produced from the 0H, 1H and 2H delay signals. The control of operations of a signal path selector and the 1H memories are changed and added to the input signals 1 and 2 and then to the input signals 4 and 5. Thus the vertical LPF signals of 1:2:1 are obtained. Furthermore, the LPF signals are delayed by 1H and the signal phase can be controlled through the memories 4 and 5. The phase of the luminance signal is controlled through the memories 3 and 6 and in accordance with a color difference signal. In such a constitution, a color difference signal VLPF circuit is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device compatible with a next-generation television system.

[0002]

2. Description of the Related Art In the next-generation television system, in order to achieve higher image quality in the vertical direction and wider screen with an aspect ratio of 16: 9, HDTV (1125 scanning lines interlaced scanning) and 2nd generation EDTV (scanning) Television systems such as 525 lines are sequentially scanned). As described above, when the aspect ratio is changed from 4: 3 to 16: 9 in the related art and becomes a progressive scanning imaging device, it is necessary to handle a wider band signal than the conventional imaging device, and not only the imaging device and the display but also the signal processing. The circuit also requires a dedicated circuit different from the standard television system video signal processing device.

Particularly, recently, video signal processing circuits have been digitized, and most of these circuits have been integrated into LSI. If the screen is widened and further scanned, the clock frequency of the circuit that performs digital processing of the video signal rises, so the arithmetic circuits such as multipliers, adders, and memories must be speeded up. Therefore, in a video signal processing device in which the screen is widened and further sequentially scanned, in order to digitally process the video signal, a dedicated digital processing circuit or LSI for considering the speed of the arithmetic circuit is taken into consideration.
However, there is a problem that the development cost becomes large.

Therefore, in constructing a video signal processing device corresponding to the television system in which the screen is widened and further progressively scanned, the development cost is increased by sharing the circuit and the LSI of the video signal processing device for the conventional standard television. In recent years, there has been proposed a method for providing an inexpensive video signal processing device for wide screen, which can output interlaced signals.

A conventional wide-screen compatible progressive scan image pickup apparatus will be described below with reference to FIGS. FIG. 4 is a block diagram showing a configuration of a conventional image pickup apparatus by progressive scanning.

The operation of FIG. 4 will be briefly described.
The optical signal photoelectrically converted by 78 is subjected to black level adjustment by black balance or the like, white level adjustment by the white balance or the like, and prinny processing or the like in the analog signal processing circuit group 79. This analog signal is the AD converter of the latter stage.
Converted to digital signal by 80.

The output signal of the AD converter 80 is input to the line division / time expansion circuit group 81, and the sequential scanning image pickup signal is an odd line (1st, 3rd, 5th ... Scanning line) every horizontal scanning line. Signal sequence and even lines (2, 4, 6 ...
(Th scanning line), each signal sequence is extended from one horizontal scanning time of the sequential scanning system to one horizontal scanning time of the interlaced scanning system, and in synchronization with the horizontal scanning of the interlaced scanning system. It is output at the same timing.

The two time-extended signal sequences are input to digital signal processing circuit groups 82 and 83, respectively, and gamma correction, blanking processing, matrix processing, vertical
Various digital processing such as horizontal contour correction processing is performed,
It is output as a luminance signal and two types of color difference signals (Pb and Pr signals).

FIG. 5 shows a block diagram of an example of the configuration of a vertical contour emphasis signal generation circuit for performing the vertical contour correction processing of the digital signal processing circuit groups 82 and 83. The R, G, and B image pickup signals input from the pre-stage signal processing circuit (not shown) are input to input terminals 5001, 5002, and 5003, respectively.
The G and B image pickup signals are written in the 1H delay lines 93, 94 and 95 for delaying one horizontal scanning period and delayed by one horizontal scanning period of the interlaced scanning system. 1H delay line 93,
The R and G imaging signals delayed by one horizontal scanning period by 94 and 95 are further input to the next 1H delay lines 96 and 97, respectively, and as a result, a total of two horizontal scanning periods are delayed from the input.

Further, R, G which are not delayed (delay by 0H)
The image pickup signals are added by the adder 98 to become a 0H delayed high frequency luminance signal. R delayed by 1 horizontal scanning period (1H delay),
The G image pickup signal is added by the adder 99 to be a 1H delayed high frequency luminance signal. Then, the R and G image pickup signals delayed by 2 horizontal scanning periods (2H delay) are added by the adder 100 to become a 2H delayed high frequency luminance signal.

OH, 1H and 2H thus obtained
Each delayed high band luminance signal is input to selectors 101 and 102 so that a vertical band pass filter (BPF) for a vertical contour correction signal can be configured in an arbitrary combination, and the selected signals are added by an adder 105. It is output from the output terminal 5104 as a vertical BPF creation signal.

Further, the vertical low-pass filter (LPF) for the horizontal contour correction signal is input to the selectors 103 and 104 so that the vertical low-pass filter (LPF) for the horizontal contour correction signal can be constructed in an arbitrary combination, and the selected signal is added to the adder 10
Output terminal 510 as a signal for vertical LPF creation after addition in 6
Output from 5.

Further, R, G, B of the contour emphasis signal generating circuit
The image pickup signal output has a phase in the vertical direction that matches the center signal of the vertical BPF and LPF, so R, G, and B delayed by 1H.
Imaging signals are output from output terminals 5101, 5102, 5103.

Next, returning to FIG. 4, the two systems of luminance signals and Pb and Pr signals digitally processed by the digital signal processing circuit groups 82 and 83 are respectively processed by the time compression / line synthesizing circuit group 84. The signal sequence is time-compressed from one horizontal scanning time of the interlaced scanning system to one horizontal scanning time of the sequential scanning system so that the signal sequence has a phase relationship before time expansion, and line combination is performed as one system of signals. The output signal of the time compression / line synthesizing circuit group 84 is converted into an analog signal by the DA converter 85 and output as a sequential scanning signal.

On the other hand, the two signal sequences digitally processed by the digital signal processing circuit groups 82 and 83 are also input to the pixel synthesizing circuit group 86. In this pixel synthesizing circuit group 86, the signal series of the odd line and the signal series of the even line are added and output as a single system signal.
At 87, a signal with an aspect ratio of 16: 9 is converted into a signal with an aspect ratio of 4: 3. The signal whose aspect ratio has been converted by this aspect ratio conversion circuit group 87 is converted into an analog signal by the DA converter 88 and output as an interlaced scanning signal.

The two signal sequences digitally processed by the digital signal processing circuit groups 82 and 83 are color difference signals V
It is input to the LPF circuit group 89. Of these two signal sequences
The Pb and Pr signals are 1: H in the 3rd line, which is the (n-1) th line signal delayed by one horizontal scanning time of the interlaced scanning system by the 1H delay line and the simultaneously input nth line and (n + 1) th line signal. A 2: 1 vertical low-pass filter process is performed and the signal is output as one system signal. The luminance signals of the two signal sequences are output as they are after being delayed so as to be output in the same phase as the Pb and Pr signals.

FIG. 6 is a block diagram (a) showing the structure of the color difference signal VLPF circuit group 89 and its timing chart (b). The operation will be described below with reference to FIGS. 6 (a) and 6 (b). Figure 6
As shown in (a), the color difference signal VLPF circuit group 89 is composed of a 1H memory 107 and adders 108 and 109, and processes Pb and Pr signals. That is, as shown in the timing chart of FIG. 6B, the input signal 1 input to the input terminal 6001
The (n + 1) th line is delayed by the 1H memory 107 in the 1H horizontal scanning period of the interlaced scanning system. 1H memory 10
7 outputs the (n-1) line input before the 1H horizontal scanning period of the interlaced scanning system, and outputs (n-1) line to the adder 108.
The line and the (n + 1) line are input, and the signals of the two lines are added and output. On the other hand, n lines are input from the input signal 2 input to the input terminal 6002, and are added to the output of the adder 108 by the adder 109 to form 3 lines 1: 2: 1.
The vertical low-pass filter processing is performed, and the output signal shown in FIG. 6B is output from the output terminal 6101.

Next, returning to FIG. 4, the luminance signal outputs of two systems and the Pb and Pr signal outputs of one system of the color difference signal VLPF circuit group 89 are input to the color difference signal HLPF circuit group 90. In the color difference signal HLPF circuit group 90, HLPF processing is performed on the Pb and Pr signals to halve the signal band and also halve the sampling frequency. The Pb and Pr signals of which the sampling frequency is halved are switched for each pixel, and the signals are combined in a time division manner so that the Pb signal and the Pr signal are alternately output, and the color difference signal is set to 1 Output as a system signal. The luminance signals of the two signal series are delayed as they are so as to be output in the same phase as the color difference signals and are output as they are. The two-system luminance signal output and the one-system color difference signal output of the color difference signal HLPF circuit group 90 are input to the mapping circuit group 91. The mapping circuit group 91 time-compresses one luminance signal system and color difference signals in order to transmit a total of three signal sequences of two systems of luminance signals and one system of color difference signals through the optical fiber 93 as two signal sequences. , The rest of the luminance signal 1
The system is time-compressed as a reinforcement signal and the odd pixels (1,
3rd, 5th ... Pixel) and even pixels (2, 4, 6th ... Pixel) are divided pixel by pixel, and the two-divided signal sequences are the time-compressed luminance signal and color difference signal. The mapping process is performed by inserting it into the non-signal portion of.

FIG. 7 is a block diagram (a) showing the configuration of the mapping circuit group 91 and its timing chart (b). The operation will be described below with reference to FIGS. 7 (a) and 7 (b). Figure 7
As shown in (a), the mapping circuit group 91 includes a 1H memory 110,
111, 112, 113, 114, 115 and selectors 116, 117, 118, 12
0, 121 and a pixel division circuit 119.

Two 1H memories and one selector are used for the signal of one system and the input signal is an odd line (1, 3, 5 ...
(Th line), the data is written in the 1H memories 110, 111 and 112, and is read out with a delay of one horizontal scanning period of the interlaced scanning system. Similarly, the input signals are even lines (2, 4, 6 ...
(Th line), the data is written in the 1H memories 113, 114 and 115, and is read out with a delay of one horizontal scanning period of the interlaced scanning system. In this way, each 1H memory performs writing and reading for each 1H. The selectors 116, 117, 118 are controlled by the 1H memory switching signal S1 so as to output the signal of the 1H memory performing the read operation.

1H when reading a signal from a 1H memory
The memories 110, 112, 113, 115 are read at a frequency higher than that at the time of writing to perform time compression, and the 1H memories 111, 114 are read at a frequency twice as high. Moreover, 1H memory 11
Readings 1 and 114 start at the timing when the signals of 1 horizontal scanning period of the 1H memories 110, 112, 113, and 115 end.

The output signals of the 1H memories 111 and 114 are divided by the pixel division circuit 119 into odd-numbered pixels (1, 3, 5 ... th pixel) and even-numbered pixels (2, 4, 6 ... The output signal 1 is output from the output terminal 7101 by switching the signal series of the odd-numbered pixels to the signal of the input signal 1 by the selector 120, and the signal series of the even-numbered pixels is changed to the signal of the input signal 3 by the selector 121. Switch to output signal 2 from output terminal 7102
Is output.

Here, the selectors 120 and 121 are switched by the 1H memories 110 and 112 or 1H according to the sub switching signal S2.
1H memory 110, 1 when the memories 113, 115 are reading
The output signals of the 12 or 1H memories 113 and 115 are controlled so as to output the output signals of the 1H memory 111 or 114 when the 1H memory 111 or 1H memory 114 is reading.

As shown in the timing chart of FIG. 7 (b), the output signal 1 is delayed by one horizontal scanning period with respect to the input signals 1, 2, 3 input from the input terminals 7001, 7002, 7003. It becomes a signal obtained by combining the compressed input signal 1 and the input signal 2 divided into odd pixels. Also, output signal 2
Is an input signal 3 which is delayed by one horizontal scanning period and time-compressed.
And a signal obtained by combining the input signal 2 divided into even pixels.

Next, returning to FIG. 4, the output signals of the two systems of the mapping circuit group 91 are parallel / serial converted by the optical transmission section and transmitted as optical signals by the optical fiber 93, and serial / parallel converted by the receiving side. .Mapping circuit group
Entered in 92. The demapping circuit group 92 separates the luminance signal, the color difference signal, and the reinforcement signal divided into the odd pixel and the even pixel from the signals of the two systems, and the reinforcement signal combines the signals of the odd pixel and the even pixel into one system. As a result, they are time-expanded and output as a luminance signal, a color difference signal, and a reinforcement signal for interlaced scanning.

FIG. 8 is a block diagram (a) showing the configuration of the demapping circuit group 92 and a timing chart diagram (b) thereof. The operation will be described below with reference to FIGS. As shown in FIG. 8A, the demapping circuit group 92 includes 1H memories 122, 123, 124, 125, 126 and 127 and selectors 128, 129 and 1.
30 and a pixel composition circuit 131.

Input signals 1 and 2 of two systems are input terminals 8001 and
The signal input from the 8002 to the pixel synthesizing circuit 131 and divided into odd-numbered pixels and even-numbered pixels for each pixel is used as one system (1, 2, 3,
(4th, 5th, 6th ... th pixel) are combined and combined into a three-system signal. Two 1H memories and one selector are used for the signal of one system, and the input signal is an odd line (1, 3, 5
.. line), the data is written in the 1H memories 122, 123, and 124, and is read out with a delay of one horizontal scanning period of the interlaced scanning system. Similarly, if the input signal is an even line (2, 4, 6
.. line), the data is written in the 1H memories 125, 126 and 127, and is read out with a delay of one horizontal scanning period of the interlaced scanning system. In this way, each 1H memory performs writing and reading for each 1H.

Only the effective portions of the luminance signal and the color difference signal are written in the 1H memories 122, 123, 125 and 126, and the 1H memory 12
Control is performed so that only the reinforcement signals obtained by pixel combination are written to 4 and 127. When writing to the 1H memories 124 and 127, since a pixel-combined signal is written, it is necessary to write at a frequency twice that of other 1H memories. Selector 128, 12
9 and 130 are controlled by the 1H memory switching signal S3 so as to output the signal of the 1H memory which is performing the read operation. When a signal is read from the 1H memory, the process reverse to the time compression process in the mapping circuit group 91 is performed. Therefore, the signal is read at a frequency lower than that at the time of writing and time extension is performed to restore the signal before the mapping process to 3 Output signals 1, 2, and 3 shown in FIG. 8B are output from the output terminals 8101, 8102, and 8103 as system signals.

[0029]

However, in the above-mentioned conventional wide-screen compatible progressive scanning image pickup apparatus, since the conventional digital signal processing circuit group is used, an interlaced scanning signal, a progressive scanning signal, an interlaced scanning signal + reinforcement is applied. A special special processing circuit group using a 1H delay line is required in order to obtain an output signal form suitable for various devices such as signals, and by using an expensive general-purpose memory, the circuit scale and the cost of the imaging device are reduced. growing. Moreover, even if each process is developed as a dedicated LSI, a development cost is required for each LSI,
There was a problem that the development cost increased.

The present invention solves such a conventional problem, and in a wide-screen compatible progressive scanning image pickup device, a 1H horizontal scanning period delay circuit used for creating a vertical contour correction signal of a digital signal processing circuit group. And the peripheral circuit, the color difference signal VLPF can be obtained only by adding a small circuit.
An object of the present invention is to provide a signal processing configuration that realizes a circuit group and can be inexpensively integrated into an LSI without requiring a dedicated development cost.

Further, according to the present invention, in a wide-screen compatible engaged scanning image pickup apparatus, a one horizontal scanning period delay circuit and a peripheral circuit used for producing a vertical contour correction signal of a digital signal processing circuit group are utilized to make a small scale. It is an object of the present invention to provide a signal processing configuration that realizes a mapping circuit group only by increasing the number of circuits and that does not require a dedicated development cost and can be inexpensively integrated into an LSI.

Further, according to the present invention, in a progressive scanning image pickup device corresponding to a wide screen, one horizontal scanning period delay circuit and a peripheral circuit used for producing a vertical contour correction signal of a digital signal processing circuit group are used to make a small scale. Only by increasing the number of circuits
An object of the present invention is to provide a signal processing configuration that realizes a mapping circuit group and that can be inexpensively integrated into an LSI without requiring a dedicated development cost.

[0033]

In order to achieve the above-mentioned object, the first means of the present invention is to input the input image pickup signals of the six systems to the first, second, third, fourth, fifth and sixth. Input means, first, second, third, fourth, fifth and sixth storage means for holding the image pickup signals input from each of the input means for one horizontal scanning period, and the first input. The output signal of the first storage means, which is input by the means and delayed by one horizontal scanning period, the image pickup signal input by the fourth input means, and the image pickup signal input by the second input means are input. A first signal switching means for outputting the selected signal; a first adding means for adding the image pickup signal input from the first input means and the output signal of the first signal switching means; Output signal of the first storage means and image pickup signal input from the second input means Second signal switching means for outputting an input selected signal; an output signal of the second storage means input from the second input means and delayed by one horizontal scanning period; and the fifth input Third signal switching means for receiving the image pickup signal inputted by the means and outputting the selected signal, the output signal of the second signal switching means, and the third signal switching means.
Second addition means for adding the output signals of the signal switching means, and the output signal of the fifth storage means and the signal input from the third input means are input, and the selected signal is output. A fourth signal switching means, a fifth signal switching means for receiving the output signal of the fourth storage means and the signal input from the sixth input means and outputting a selected signal, and the fourth signal switching means. Third addition means for adding the output signal of the signal switching means and the output signal of the fifth signal switching means, the output signal of each of the first, second and third addition means and the fourth input. A sixth signal switching means for receiving the input signal of the means and outputting the selected signal, and the output signals of the first, second and third adding means, respectively, and outputting the selected signal. Seventh signal switching means,
Fourth adding means for adding the output signal of the sixth signal switching means and the output signal of the seventh signal switching means;
Eighth signal switching means for receiving the respective output signals of the second and third adding means and the input signal of the fifth input means and outputting a selected signal, and the first, second and third Output signals of the respective addition means of No. 9 and the output signal of the ninth signal switching means for outputting the selected signal, the output signal of the eighth signal switching means and the output signal of the ninth signal switching means are added. A fifth addition means, a tenth output terminal of the output signal of the first storage means, an output signal of the first addition means, and an output signal of the fourth addition means are input and a selected signal is output. A signal selected by the signal switching means, the output signal of the fourth storage means obtained by delaying the output signal of the tenth signal switching means by one horizontal scanning period, and the output signal of the tenth signal switching means. And an eleventh signal switching means for outputting The first output means for outputting the output signal of the switching means, the output signal of the second storage means, the output signal of the second adding means, and the output signal of the fifth adding means are input and selected. And a twelfth signal switching means for outputting the output signal of the twelfth signal switching means, an output signal of the fifth storage means obtained by delaying the output signal of the twelfth signal switching means for one horizontal scanning period, and the twelfth signal switching means. , A thirteenth signal switching means for outputting the selected signal, a second output means for outputting the output signal of the thirteenth signal switching means, and one horizontal scanning period input from the third input means. A fourteenth signal which receives the delayed output signal of the third storage means, the output signal of the third adding means, and the image pickup signal input from the sixth input means, and outputs a selected signal The output signal of the switching means and the fourteenth signal switching means is 1 water. A fifteenth signal switching means which receives the output signal of the sixth storage means and the output signal of the fourteenth signal switching means delayed by the scanning period and outputs a selected signal, and the fifteenth signal switching means. 3rd output means for outputting the output signal of, the 4th output means for outputting the output signal of the 4th addition means, the output signal of the 5th addition means and the 3rd input means for inputting A signal that has been selected and an output signal of the third storage means, and outputs a selected signal; and a fifth signal that outputs the output signal of the sixteenth signal switching means.
And output control means and storage control means for arbitrarily controlling writing and reading of the first, second, third, fourth, fifth and sixth storage means.

The second means inputs first, second and third input means for inputting three systems of input image pickup signals, and signals from the first, second and third input means respectively. And the first, second and third storage means capable of holding the input signal for one horizontal scanning period, and the image pickup signal and the imaging signal input from the first, second and third input means, respectively. Output signals of the first, second and third storage means are input and first, second and third signal switching means for outputting a selected signal, and the first, second and third signal switching means, respectively. Fourth, fifth and sixth signals capable of holding the signal output from the signal switching means for one horizontal scanning period
Storage means, and output signals of the first, second and third storage means and output signals of the fourth, fifth and sixth storage means, respectively, and a fourth signal for outputting a selected signal. , 5th and 6th signal switching means and output signals of the 5th signal switching means are odd pixel (1,3,5 ... th pixel) and even pixel (2,4,6 ... th pixel) A pixel dividing means for dividing each pixel to output two signal sequences, an output signal of the fourth signal switching means and a first output of the pixel dividing means, and outputs a selected signal. The seventh signal switching means, the eighth signal switching means for receiving the output signal of the sixth signal switching means and the second output of the pixel dividing means, and outputting the selected signal, respectively. First, second outputs the output signals of the seventh, fifth and eighth signal switching means And a third output means and a storage control means for arbitrarily controlling writing and reading of the respective storage means.

The third means includes first, second and third input means for inputting three systems of input image pickup signals and a first holding means for holding the input image pickup signals as image pickup signals for one horizontal scanning period. , Second and third storage means, and odd-numbered pixels (1, 3, 5 ... th pixel) and even-numbered pixels (2, 4, 6 ... th pixel input from the first and second input means) ), A pixel synthesizing means for synthesizing two systems of signals divided for each pixel for each pixel to synthesize one system of signals, an image pickup signal inputted from the third input means, and an output signal of the pixel synthesizing means. Is input to output a selected signal, and the output signal of the first storage unit input from the first input unit and delayed by one horizontal scanning period and the first signal switching unit. The image pickup signal inputted from the input means is inputted and the selected signal is outputted. Second signal switching means, and the second
The input signal of the second storage means delayed by one horizontal scanning period and the image pickup signal input from the second input means are input, and the selected signal is output. A signal selected by the signal switching means, the output signal of the third storage means obtained by delaying the output signal of the first signal switching means by one horizontal scanning period, and the output signal of the first signal switching means are input. And fourth, fifth and sixth storage means capable of holding the output signals of the second, third and fourth signal switching means respectively for one horizontal scanning period. , The first, respectively
The output signals of the second and third storage means and the fourth and the fourth
Fifth, sixth and seventh signal switching means for receiving the output signals of the fifth and sixth storage means and outputting the selected signals, and the fifth, sixth and seventh signal switching means, respectively. The first, second and third output means for outputting the output signal and the storage control means for arbitrarily controlling writing and reading of the respective storage means are provided.

[0036]

According to the first means of the present invention, the operations of the 1H memory and the peripheral circuits used for creating the vertical contour correction signal of the digital signal processing circuit are switched to perform the color difference signal VLPF processing operation, and the 1H memory is shared. By doing so, it is possible to configure two systems of the color difference signal VLPF circuit and two systems of the luminance signal delay circuit which can be inexpensively integrated into an LSI without requiring a development cost for each function.

That is, as the first operation of the first means, the first signal switching means outputs the input signal of the second input means, and the tenth signal switching means outputs the first storage. Means outputs the output signal of the first storage means, the eleventh signal switching means outputs the output signal of the tenth signal switching means, and the second signal switching means outputs the output signal of the output means of the first storage means. Is output, and the output signal of the second storage means is output by the third signal switching means.

The twelfth signal switching means outputs the output signal of the second storage means, the thirteenth signal switching means outputs the output signal of the twelfth signal switching means, and the fourth signal switching means outputs the output signal. The signal switching means outputs the output signal of the fourth storage means, the fifth signal switching means outputs the output signal of the fifth storage means, and the fourteenth signal switching means outputs the third signal. The output signal of the storage means is output.

The fifteenth signal switching means outputs the output signal of the fourteenth signal switching means, and the sixth, seventh, eighth, and ninth signal switching means output the first, second, and ninth signals. An arbitrary signal is output from the adding means of No. 3, and an output signal of the fifth adding means is output from the sixteenth signal switching means to input the input image pickup signal (0H delay signal) to the first, second and third. The storage means delays one horizontal scanning period under the control of the storage control means to obtain a one horizontal scanning period delay signal (1H delay signal).

Further, the 1H delay signal is further delayed by one horizontal scanning period by the control of the storage control means in the fourth, fifth and sixth storage means and delayed by two horizontal scanning periods from the input (2H delay signal). ) Is obtained, a vertical contour emphasis signal is created from the 0, 1, 2H delay signal and
The vertical contour emphasizing signal generating circuit for outputting the H delay signal is operated.

As a second operation, the first signal switching means outputs the input signal of the fourth input means, and the tenth signal is output.
Signal switching means outputs the output signal of the first adding means, the second signal switching means outputs the output signal of the second input means, and the third signal switching means outputs the fifth signal. The input signal of the second input means is output, the output signal of the second addition means is output by the twelfth signal switching means, and the output signal of the third input means is output by the fourth signal switching means. Then, the fifth signal switching unit outputs the input signal of the sixth input unit.

Further, by switching the operation of the storage control means, the input image pickup signal is divided into an odd line (1, 3, 5 ... Line) and an even line (2, 4, 6 ... Line) line by line. Further, two image pickup signal sequences which are time-expanded in two horizontal scanning periods and inputted at the same timing are inputted from the first, second, third and fourth, fifth and sixth input means, respectively. , The input signals of the first and fourth input means are added by the first adding means to be combined into a signal of one system and output from the tenth signal switching means.

The signal which is added by the eleventh signal switching means and combined into one system is output, or the combined signal is delayed by one horizontal scanning period by using the fourth storage means to change the phase. It is controlled and outputted, or arbitrarily selected and outputted from the first output means, and similarly, the input signals of the second, fifth and third and sixth input means are respectively outputted in the second, third The twelfth,
The signal is output from the 14th signal switching means,
The signal synthesized by one of 15 signal switching means is output, or the signal synthesized by using the fifth and sixth storage means is delayed by one horizontal scanning period and the phase is controlled and outputted. Then, the pixel synthesizing circuit for synthesizing the input signals of the two systems by outputting from the second and third output means is operated.

As a third operation, the first signal switching means outputs the output signal of the first storage means, and the sixth signal is output.
Signal switching means outputs the input signal of the fourth input means, the seventh signal switching means outputs the output signal of the first adding means, and the tenth signal switching means outputs the fourth signal. The output signal of the adding means is output, and the output signal of the twelfth input means is output by the second signal switching means.

The third signal switching means outputs the output signal of the second storage means, the eighth signal switching means outputs the input signal of the fifth input means, and the ninth signal. The switching means outputs the output signal of the second adding means, the twelfth signal switching means outputs the output signal of the fifth adding means, and the fourteenth signal switching means outputs the sixth input. Output the input signal of the means.

Further, the operation of the storage control means is switched to input the luminance signal (Y signal) and the two kinds of color difference signals (P signal).
b, Pr signals) are divided line by line into odd lines (1,3,5 ... th line) and even lines (2,4,6 ... th line), respectively, and time-expanded in two horizontal scanning periods. The two-system Y signals input at the same timing are input to the third and sixth input means, and the second-system Pb and Pr signals are input to the first and fourth input means or the second and fifth input means. The color difference signal is input to the input unit, and the color difference signal is the signal (0H delay signal) input from the first and second input units.
1 horizontal scanning period delay (1H delay signal) by the storage means, and the 0H delay signal by the first and second adding means, and the signal input from the fourth and fifth input means. The addition is performed by the fourth and fifth adding means.

The signals added by the eleventh and thirteenth signal switching means and combined into one system are output, or the combined signals are utilized for one horizontal scanning by utilizing the fourth and fifth storage means. It is delayed for a period to output the phase controlled or outputted, or arbitrarily selected and outputted from the first and second output means, and the luminance signal is switched to the third and fourth signals in order to match the phase with the color difference signal. Means to output the input signal as it is, or to use the third and sixth storage means to delay the signal by one horizontal scanning period to control the phase and output the signal.
A color-difference signal VLPF circuit that performs vertical filtering on the color-difference signals output from the fifth output means is obtained.

Further, according to the second means of the present invention, it is used for producing the vertical contour correction signal of the digital signal processing circuit.
By mapping the operation of the H memory and the peripheral circuit to perform the mapping processing operation and sharing the 1H memory, it is possible to configure one system of the mapping circuit that can be inexpensively integrated into an LSI without the development cost for each function. it can.

That is, as the first operation of the second means, the output signals of the first, second and third storage means are output by the first, second and third signal switching means, respectively.
The output signals of the first, second and third storage means are output by the fourth, fifth and sixth signal switching means, respectively, and are input from the first, second and third input means, respectively. The input image pickup signal (0H delay signal) is set to 1 by the first, second and third storage means under the control of the storage control means.
A horizontal scanning period delay is performed to obtain a horizontal scanning period delay signal (1H delay signal).

Then, each of the 1H delay signals is further delayed by one horizontal scanning period by the control of the storage control means in the fourth, fifth and sixth storage means, and is delayed by 2 from the input.
A signal delayed by a horizontal scanning period (2H delay signal) is obtained, vertical contour emphasis signals are created from the 0, 1, 2H delay signals, and 1H delays are made by the first, second and third output means, respectively. The vertical contour emphasizing signal generating circuit that outputs a signal is operated.

As a second operation, the image pickup signals input by the first, second and third input means are output by the first, second and third signal switching means, respectively, and the storage means of the storage means is operated. The operation is switched and the input imaging signal is an odd line
(1,3,5 ... th line) are written in the first, second and third storage means respectively, and when the input image pickup signal is an even line (2,4,6 ... th line). The first, second, third, fourth, fifth and sixth storage means are alternately written in every horizontal scanning period so as to be written in the fourth, fifth and sixth storage means, respectively. Control to do.

During the write operation of the first, second and third storage means, the signals written in the fourth, fifth and sixth storage means are read out, and the fourth, fifth and sixth storage means are read out.
During the write operation of the storage means, the signals written in the first, second and third storage means are read out and the first, second, third and fourth, fifth and sixth storage means are The written signal is delayed by one horizontal scanning period and the reading operation is alternately performed every one horizontal scanning period.

Then, the fourth, fifth and sixth signal switching means are being read out of the first, second, third storage means and fourth, fifth, sixth storage means, respectively. The output signal of the storage means is switched every horizontal scanning period, and the signals written in the first, third, fourth, and sixth storage means are output at a frequency n times as high as that at the time of writing. Read and perform time compression.

The reading of the signals written in the second and fifth storage means is performed at the timing when the reading of the first, third, fourth, and sixth signals ends, and the read frequency is 2n times as high as the writing frequency. In the period in which the signals are output from the fourth and sixth signal switching means by the seventh and eighth signal switching means, the output signals of the fourth and sixth signal switching means are selected, During a period in which no signal is output, the output signal of the pixel dividing means is selected, and the signals divided for each odd pixel and even pixel are switched and combined.

By outputting the output signals of the seventh and eighth signal switching means from the first and third output means, respectively, the three signal sequences are time-compressed, respectively, and are generated by the time compression. In the non-signal period, the signal of one system is divided into an odd pixel and an even pixel for each pixel, is switched and combined, and is output as a signal of two systems.

According to the third means of the present invention, it is used in the vertical contour correction signal generation of the digital signal processing circuit.
One de-mapping circuit that can be integrated into an LSI at low cost without requiring development cost for each function by switching the operation of H memory and peripheral circuits to perform de-mapping processing operation and sharing 1H memory Can be configured.

That is, as the first operation of the third means, the first signal switching means outputs the input signal of the third input means to switch the second, third and fourth signals, respectively. Means output the output signals of the first, second and third storage means, and the fifth, sixth and seventh signal switching means output the output signals of the first, second and third storage means, respectively. A signal is output, and the input image pickup signal (0H delay signal) input from the first, second and third input means, respectively, is controlled by the storage control means by the first, second and third storage means. Thus, the signal is delayed by 1 horizontal scanning period to obtain a 1 horizontal scanning period delay signal (1H delay signal).

Then, each of the 1H delay signals is further delayed by one horizontal scanning period in the fourth, fifth and sixth storage means under the control of the storage control means, and then input from the input 2
A signal delayed by a horizontal scanning period (2H delay signal) is obtained, vertical contour emphasis signals are created from the 0, 1, 2H delay signals, and 1H delays are made by the first, second and third output means, respectively. The vertical contour emphasizing signal generating circuit that outputs a signal is operated.

As a second operation, the first signal switching means outputs the output signal of the pixel synthesizing means, and the second, third and fourth signal switching means respectively output the first and second inputs. Means and the signal from the first signal switching means are output, and the operation of the storage control means is switched to time-compress three-system signals as input signals to convert one-system signal into an odd pixel and an even pixel. When the signals of the two systems that are divided by pixel and switched to the remaining two systems of time-compressed non-signal portions are input, the input imaging signal is an odd line
(1,3,5 ... th line) are written in the first, second and third storage means respectively, and when the input image pickup signal is an even line (2,4,6 ... th line). The first, second, third and fourth, fifth and sixth storage means are respectively written in the fourth, fifth and sixth storage means.
The storage means is controlled so that the writing operation is alternately performed every horizontal scanning period.

Further, the first, second and fourth and fifth storage means write only the original two-system signal portion, and the third and sixth storage means are switched to the non-signal portion to be synthesized. The signals of the two systems divided into the odd number pixel and the even number pixel for each pixel are switched to one system by the pixel synthesizing means, and the synthesized signal is twice as large as that of the first, second and fourth and fifth storage means. Write at a frequency, read the signals written in the fourth, fifth and sixth storage means during the write operation of the first, second and third storage means, and read the fourth, fifth and sixth storage means. During the write operation of the storage means, the signals written in the first, second and third storage means are read out and the first, second, third and fourth, fifth and sixth storage means are Delay the written signal by 1 horizontal scanning period and then 1 horizontal scanning period Controls to perform the read operation alternately in each.

The first, second, third, fourth and fifth
And the sixth and fifth storage means are set to the read frequency of the signal to be 1 / n times as high as the first, second and fourth and fifth write frequencies to perform time extension, and the fourth and fifth signals respectively. And a sixth signal switching means is the first,
Second and third storage means and fourth, fifth and sixth
Of the storage means, the output signal of the storage means during the read operation is switched every horizontal scanning period,
The original signal portion of the two signal sequences is time-expanded, the odd-numbered pixel and the even-numbered pixel are switched to the non-signal part, and the combined signal is combined into the original one system to perform time expansion. It operates the demapping circuit that restores and outputs the signals of three systems.

[0062]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of an image pickup apparatus according to the first embodiment of the present invention. In FIG. 1, 10
01 to 1006 are input terminals as input means for inputting inputs 1 to 6, and 1 to 6 are image pickup signals for one horizontal scanning period (1H).
1H memory as a first to sixth storage means, which is delayed and is capable of controlling writing and reading separately, 7 is the above 1
1 as storage control means for generating control signals for H memory
H memory control circuit, 8 to 12 adders as first to fifth adding means, 13 to 28 selectors as first to sixteenth signal switching means for outputting any one signal of signal inputs, 11
01 to 1105 are output terminals as outputs 1 to 3 and first to fifth output means for outputting signals for producing vertical BPF and LPF.

The first operation of the vertical contour emphasizing signal generating circuit according to the first embodiment of the present invention will be described below.
Inputs 1, 2, 3 (R, G,
B image pickup signal input) is input to the 1H memories 1, 2, and 3, respectively. The 1H memories 1, 2 and 3 are controlled by the 1H memory control circuit 7 so as to delay each input signal by 1H. The 1H-delayed R, G, B image pickup signals output from the 1H memories 1, 2, and 3 are input to selectors 18, 19, and 20.

The other inputs of the selectors 18, 19 and 20 are not used in the vertical contour emphasizing signal generating circuit, and therefore only the 1H delay signal is output. The output signals of the selectors 18, 19, 20 are input to the 1H memories 4, 5, 6 respectively. The 1H memories 4, 5 and 6 are controlled by the 1H memory control circuit 7 so as to delay each input signal by 1H, similarly to the 1H memories 1, 2 and 3.

The 1H memories 4, 5 and 6 output 2H delayed R, G and B image pickup signals. Also selectors 18, 1
The 1H-delayed R, G, B image pickup signals output from 9, 20 are input to selectors 25, 26, 27. Selector 25, 2
The R, G, B image pickup signals delayed by 1H and the R, G, B image pickup signals delayed by 2H are input to 6 and 27, respectively, but only the 1H delayed signal is output. Selector 25, 26, 27
The output signal of is directly output as output terminals 1, 2 and 3 11
Output from 01, 1102, 1103.

The G image pickup signal delayed by 0H passes through the selector 13 and is added by the adder 8 to the R image pickup signal delayed by 0H.
The R image signal delayed by 1H passes through the selector 14, and the G image signal delayed by 1H passes through the selector 15 and is added by the adder 9. The 2H-delayed R image pickup signal passes through the selector 17, and the 2H-delayed G image pickup signal passes through the selector 16 and is added by the adder 10.

0H, 1 added by adders 8, 9, 10
H, 2H delay high frequency luminance signals are selectors 21, 22, 23, 24
The signal input to the selector and selected by the selectors 21 and 22 is the adder
Added at 11 and output terminal as vertical BPF creation signal 11
It is output from 04. The signals selected by the selectors 23 and 24 are added by the adder 12 and output from the output terminal 1105 as a vertical LPF creation signal. In this way, the same operation as that of the conventional vertical contour emphasis signal generation circuit can be obtained.

Further, the second operation similar to that of the pixel synthesizing circuit group 86 shown in FIG. 4 can be performed by utilizing the configuration of the present invention. The signal from the input 1 from the input terminal 1001 and the signal from the input 4 from the input terminal 1004 that passed through the selector 13 are added by the adder 8 to synthesize the two input signals, and the output signal from the adder 8 passes through the selector 18. Is input to the 1H memory 4 and the selector 25. The output signal of the 1H memory 4 is input to the selector 25, and the selector 18 outputs the signal added by the adder 8 for 1H.
It is output as the output 1 from the output terminal 1101 by selecting whether to delay or not.

The signal of the input 2 from the input terminal 1002 passing through the selector 14 and the signal of the input 5 from the input terminal 1005 passing through the selector 15 are added by the adder 9 to synthesize the input signals of the two systems, and the addition is performed. The output signal of the container 9 is input to the 1H memory 5 and the selector 26 through the selector 19. The output signal of the 1H memory 5 is input to the selector 26, and the selector 19 selects whether the signal added by the adder 9 is delayed by 1H or not, and outputs it as the output 2 from the output terminal 1102. The signal of the input 3 from the input terminal 1003 passing through the selector 16 and the signal of the input 6 from the input terminal 1006 passing through the selector 17 are added by the adder 10 to synthesize the input signals of the two systems, and the adder 10 Output signal goes through selector 20 and 1H memory 6 and selector
Entered in 27. The output signal of the 1H memory 6 is the selector 27
Input to the selector 20, and the selector 20 selects whether the signal added by the adder 10 is delayed by 1H or not, and an output terminal
By outputting the output 3 from 1103, the pixel synthesizing circuit can be configured in three systems. The adders 11 and 12 and the selectors 21, 22, 23, 24, and 28 have nothing to do with the operation of the pixel synthesizing circuit.

Next, the third operation of the color difference signal VLPF circuit will be described. Odd lines (1,3,5 ... th line) from the image signal of the progressive scanning meter to the interlaced scanning system
And the luminance signal which is line-divided and time-expanded into two signal series of even lines (2, 4, 6, ..., Line) are input as input 3 and input 6 from input terminals 1003 and 1006. P
b, Pr signal is input 1 from input terminal 1001 and input terminal 1004
Input 4 and input terminal 1002 Input 2 and input terminal 10
It is done by input 5 from 05.

The signal of input 1 is also input to the adder 8 and the signal of input 2 is input to the adder 9 through the selector 14. The signals delayed by 1H in the 1H memories 1 and 2 are input to adders 8 and 9 through selectors 13 and 15, respectively. The output signals of the adders 8 and 9 are selectors 22 and 24, respectively.
And is input to the adders 11 and 12.

The input signals of the inputs 4 and 5 are selectors, respectively.
Input to adders 11 and 12 through 21 and 23, and adders 11 and 12
Output signal is a signal obtained by subjecting the input color difference signal to LPF processing of 1: 2: 1. The signals subjected to the vertical LPF processing pass through the selectors 18 and 19, respectively, and the signals are directly output to the output terminals 1101 and 1102 as the output 1 and the output 2 by the selectors 25 and 26, respectively, or further delayed by 1H to adjust the horizontal phase. Or output the selected output.
The luminance signal of the input 3 input from the input terminal 1003 is delayed by 1H in the 1H memory 3, and the selector 28 selects whether to output the input signal as it is to match the phase with the color difference signal or to output the signal delayed by 1H. Then, it is output from the output terminal 1105 as a vertical LPF creation signal.

The luminance signal of the input 6 input from the input terminal 1006 passes through the selector 20 and is delayed by 1H in the 1H memory 6,
Similarly to the input 3, the selector 27 selects whether to output the input signal as it is from the output terminal 1103 as the output 3 to match the phase with the color difference signal or to output the signal delayed by 1H, and output as the output terminal 1003. . In this way, an operation similar to that of the conventional color difference signal VLPF circuit can be obtained.

Needless to say, the vertical BPF circuit can be constructed by switching the operations of the adders 11 and 12 to operate the subtractor.

As described above, according to the first embodiment of the present invention, the 1H memory and the peripheral circuit of the vertical contour enhancement signal generating circuit of the digital signal processing circuit are utilized in the image pickup apparatus capable of progressive scanning, and the 1H memory is used. Switch the operation of
By adding a selector circuit so that the operation can be switched, a color difference signal VLPF circuit or a pixel synthesizing circuit can be realized in addition to the conventional vertical contour emphasizing signal generating circuit, and the development cost is not required exclusively. LS at low cost
A signal processing configuration that enables I conversion is obtained.

Next, an image pickup apparatus according to the second embodiment of the present invention will be described. FIG. 2 is a block diagram showing the arrangement of an image pickup apparatus according to the second embodiment of the present invention.

In FIG. 2, 2001 to 2003 are first to third.
Input terminal as an input means of the
1H memory as first to sixth storage means which can be separately controlled for writing and reading with delay, 35 is a 1H memory control circuit as storage control means for generating a control signal for the 1H memory, 41 to 43, Reference numerals 48 to 52 designate selectors as first to eighth signal switching means for outputting any one of the input signals,
Reference numeral 53 is a pixel division circuit as a pixel division means for dividing the input signal into odd-numbered pixels (1, 3, 5 ... th pixel) and even-numbered pixels (2, 4, 6 ... 36 to 40 are adders, 44 to 47 are selectors, 2101 to 2105 are outputs 1 to 3, and output terminals as first to fifth output means for outputting signals for producing vertical BPF and LPF.

The first operation of the vertical contour emphasizing signal generating circuit according to the second embodiment of the present invention will be described below.
In FIG. 2, inputs 1, 2, 3 (R,
G, B imaging signal input) are 1H memories 29, 30, 3 respectively.
Entered in 1. The 1H memories 29, 30, 31 are controlled by the 1H memory control circuit 35 so as to delay the input signal by 1H. The 1H delayed R, G, B image pickup signals output from the 1H memories 29, 30, 31 are input to the 1H memories 32, 33, 34 through the selectors 41, 42, 43, respectively.

The 1H memories 32, 33, 34 are the 1H memories 29, 3
As with 0 and 31, the 1H memory control circuit 35 controls the input signal to delay it by 1H. 1H memory 32, 33, 34
The R, G, B image pickup signals delayed by 2H are output.
In addition, the 1H delayed R, G, B image signals are selected by the selector 4
The output signal of the selector 48 passes through 8, 49 and 50 and the selector 51 outputs
Is output from the output terminal 2101 as output 1. The output signal of the selector 49 is output as it is from the output terminal 2102 as the output 2, and the output signal of the selector 50 passes through the selector 52 and is output as the output 3 from the output terminal 2103.

Selectors 44, 45, 46, 47 and adder 39,
The circuit of 40 is exactly the same as the vertical contour emphasis signal generation process of the conventional example, and therefore its operation is also the same, and the explanation of the operation is omitted. In this way, the same operation as that of the conventional vertical contour emphasis signal generation circuit can be obtained.

Next, the second operation of the mapping circuit will be described. Inputs 1, 2, 3 (R, G, B image signal input) input from input terminals 2001, 2002, 2003 are 1H memory 2
Input to 9, 30, 31 and selectors 41, 42, 43. The selectors 41, 42, 43 output the signals of the inputs 1, 2, 3 and are input to the 1H memories 32, 33, 34. The 1H memories 29, 30, 31 and the 1H memories 32, 33, 34 are set to 1 by the 1H memory control circuit 35.
The input signal is alternately written for each H, and the signal delayed by 1H is read. The 1H memories 29, 30, 31 write the odd-numbered lines (1, 3, 5 ... Lines) of the input signal and read them with a delay of 1H. Similarly, 1H memory 32,
33 and 34 write even lines (2, 4, 6 ... Lines) and read them with a delay of 1H.

The selectors 48, 49 and 50 are controlled to output the signal of the 1H memory which is performing the read operation.
When the signal is read from the 1H memory, the 1H memory control circuit 35 reads the signal at a higher frequency than that at the time of writing, similarly to the mapping circuit of the conventional example, thereby performing time compression
1H memories 30, 33 can be read from 1H memories 29, 31, 32,
It starts when the 34 signal ends.

The output signal of the selector 49 is input to the pixel division circuit 53, and there are two systems for each pixel, odd numbered pixels (1, 3, 5 ... th pixel) and even numbered pixels (2, 4, 6 ... Of the 1H memories 29 and 31 or the 1H memories 32 and 34 by the selectors 51 and 52, and outputs the outputs 1 and 3 as two-system signals from the output terminals 2101 and 2103. In this way, an operation similar to that of the conventional mapping circuit can be obtained. The adders 39 and 40 and the selector 44,
45, 46 and 47 have nothing to do with the operation as a mapping circuit.

As described above, according to the second embodiment of the present invention, the 1H memory of the vertical contour enhancement signal generating circuit of the digital signal processing circuit and the peripheral circuit are used in the 1H memory in the progressive scan compatible image pickup apparatus. Switch the operation of
By adding a pixel division circuit and a selector circuit so that the operation can be switched, it is possible to realize a mapping circuit in addition to the conventional vertical contour enhancement signal generation circuit, which requires no special development cost and is inexpensive. It is possible to obtain a signal processing configuration that enables LSI implementation.

Next, an image pickup apparatus according to the third embodiment of the present invention will be described. FIG. 3 is a block diagram showing the arrangement of an image pickup apparatus according to the third embodiment of the present invention.

In FIG. 3, reference numerals 3001 to 3003 denote input terminals as input means to which inputs 1 to 3 are input, and reference numerals 54 to 59, which delay the image pickup signal by 1H, so that writing and reading can be controlled separately. 1H memory as a sixth storage means,
Reference numeral 60 is a 1H memory control circuit as a storage control means for generating a control signal for the 1H memory, and 66 to 68, 73 to 75 and 77 are selectors as arbitrary second to sixth and first signal switching means among inputs. , 76 is an odd numbered pixel (1, 3, 5 ... th pixel) and an even numbered pixel (2, 4, 6 ... Three
(4th, 5th, 6th ... Pixel combination) and a pixel combination circuit as a pixel combination means, 61-65 adders, 69-72 selectors, 3101-3105 outputs 1-3, vertical BPF ，
It is the 1st-5th output terminals which output the signal for LPF creation.

The first operation of the vertical contour enhancement signal generation circuit of the third embodiment of the present invention will be described below.
In FIG. 3, R, G, and B imaging signal inputs in which inputs 1, 2, and 3 are input to input terminals 3001, 3002, and 3003 from a pre-stage signal processing unit (not shown) are 1H memories 54 and 5, respectively.
Input to 5,56. The 1H memories 54, 55 and 56 are controlled by the 1H memory control circuit 60 to delay the input signal by 1H. The 1H-delayed R, G and B image pickup signals output from the 1H memories 54, 55 and 56 are input to the 1H memories 57, 58 and 59 through selectors 66, 67 and 68, respectively.

The 1H memories 57, 58, 59 are the 1H memories 54, 5
Similar to 5 and 56, the 1H memory control circuit 60 controls to delay the input signal by 1H. 1H memory 57, 58, 59
The R, G, and B imaging signals delayed by 2H from the selector 73,
It is output from the output terminals 3101, 3102, 3103 through 74, 75. Further, the R, G, B image signals delayed by 1H pass through the selectors 73, 74, 75 and are directly output terminals 3101, 3102, 31.
It is output as outputs 1, 2, and 3 from 03.

Selectors 69, 70, 71, 72 and adders 64,
The circuit of 65 is exactly the same as the vertical contour emphasis signal generation process of the conventional example, and therefore its operation is also the same, and the explanation of the operation is omitted. In this way, the same operation as that of the conventional vertical contour emphasis signal generation circuit can be obtained.

Next, the second operation of the demapping circuit will be described. The signals whose inputs 1 and 2 are input to the input terminals 3001 and 3002 are input to the pixel synthesizing circuit 76, and the signals divided into the odd pixel and the even pixel are switched to one system to input 1,
Signals of 3 systems are combined with 2. The input signals of the inputs 1 and 2 and the output signal of the pixel composition circuit 76 are the 1H memories 54 and 5
1H memory 57, 5 through 5, 56 and selectors 66, 67, 68
Input to 8 and 59. The 1H memories 54, 55, 56 and the 1H memories 57, 58, 59 are controlled by the 1H memory control circuit 60 to write an input signal for each 1H and read out a signal delayed by 1H. The 1H memories 57, 58 and 59 write the odd lines (1, 3, 5 ... Lines) of the input signal and read them with a delay of 1H. Similarly, the 1H memories 57, 58 and 59 write even-numbered lines (2, 4, 6 ... Lines) and read them with a delay of 1H.

The selectors 73, 74 and 75 are controlled to output the signal of the 1H memory which is performing the read operation.
The 1H memories 54, 55, 57, 58 are controlled so that only the effective portions of the luminance signal and the color difference signal are written, and the 1H memories 56, 59 are controlled so that only the pixel-combined reinforcement signals are written. When a signal is read from the 1H memory, the 1H memory control circuit 60 controls the signal to be read at a lower frequency than that at the time of writing to extend the time, and the restored three-system signals are output from the output terminals 3101, 3102, and 3103. , 3 are output. In this way, an operation similar to that of the conventional demapping circuit can be obtained. The adders 64 and 65 and the selector
69, 70, 71, 72 have nothing to do with the operation as the demapping circuit.

As described above, according to the third embodiment of the present invention, the 1H memory and the peripheral circuit of the vertical contour enhancement signal generating circuit of the digital signal processing circuit are used in the image pickup apparatus corresponding to the progressive scanning, Switching the operation of 1H memory,
By adding a pixel synthesizing circuit and a selector circuit so that the operation can be switched, a demapping circuit can be realized in addition to the conventional vertical contour emphasizing signal creating circuit, without requiring a dedicated development cost. It is possible to obtain a signal processing configuration that can be integrated into an LSI at low cost.

[0094]

As described above, the image pickup apparatus of the present invention has the following effects.

1. In the past, a color difference signal VLPF circuit was realized by using an expensive memory circuit or the like in addition to the circuit group required for digital signal processing, whereas it is used by the vertical contour emphasis signal generation circuit of the digital signal processing circuit group. By providing a circuit configuration in which a selector circuit is added and a 1H memory is shared, the control of one LSI can be switched to obtain both the vertical contour enhancement signal generation circuit and the color difference signal VLPF circuit. It is possible to provide an imaging device that does not require the.

2. Further, in the past, a mapping circuit was realized by using a circuit such as an expensive memory in addition to the circuit group necessary for digital signal processing, whereas the vertical contour emphasizing signal generating circuit of the digital signal processing circuit group was realized. By adding a pixel dividing circuit and a selector circuit to form a circuit configuration sharing a 1H memory, control of one LSI can be switched to obtain both a vertical contour emphasis signal generating circuit and a mapping circuit. An imaging device that does not require development costs can be provided.

3. Also, in the past, a demapping circuit was realized by using an expensive circuit such as a memory in addition to the circuit group required for digital signal processing, whereas the vertical contour enhancement signal generation of the digital signal processing circuit group was realized. By adding a pixel synthesizing circuit and a selector circuit to the circuit so as to have a circuit configuration in which a 1H memory is shared, control of one LSI is switched to obtain both the vertical contour emphasis signal generating circuit and the demapping circuit. It is possible to provide an imaging device that is inexpensive and does not require a dedicated development cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image pickup apparatus in a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an image pickup apparatus in a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an image pickup apparatus in a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional imaging device.

5 is a block diagram showing a configuration of a vertical contour enhancement signal generation circuit of FIG.

6 is a block diagram (a) and a timing chart diagram (b) showing a configuration of a color difference signal VLPF circuit group of FIG. 5.

7 is a block diagram (a) and a timing chart diagram (b) showing the configuration of the mapping circuit group of FIG. 4;

8 is a block diagram (a) and a timing chart diagram (b) thereof showing the configuration of the de-mapping circuit group of FIG.

[Explanation of symbols]

1-6, 29-34, 54-59 ... 1H memory, 7, 35, 60 ...
1H memory control circuit, 8 to 12, 36 to 40, 61 to 65 ... Adder, 13 to 28, 41 to 52, 66 to 75, 77 ... Selector, 53 ... Pixel division circuit, 76 ... Pixel composition circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shoji Nishikawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A first and a sixth input image pickup signals are inputted.
Second, third, fourth, fifth and sixth input means, and first, second, third, fourth and fourth input means for holding an image pickup signal for one horizontal scanning period input from each of the input means. 5 and 6
Storage means, an output signal of the first storage means input from the first input means and delayed by one horizontal scanning period, an image pickup signal input from the fourth input means, and the second input First signal switching means for receiving the image pickup signal inputted by the means and outputting the selected signal, and the image pickup signal inputted by the first input means and the first signal switching means
First addition means for adding the output signals of the signal switching means, and the output signal of the first storage means and the image pickup signal input from the second input means are input, and the selected signal is output. The second signal switching means, the output signal of the second storage means input from the second input means and delayed by one horizontal scanning period, and the imaging signal input from the fifth input means are input. A third signal switching means for outputting the selected signal, a second adding means for adding the output signal of the second signal switching means and the output signal of the third signal switching means, and the fifth Output signal of the storage means and the signal input from the third input means, and outputs a selected signal, a fourth signal switching means, an output signal of the fourth storage means and the sixth signal The signal input from the input means of Fifth signal switching means for outputting the output signal, third adding means for adding the output signal of the fourth signal switching means and the output signal of the fifth signal switching means, and the first and the first Sixth signal switching means for receiving the output signals of the second and third adding means and the input signal of the fourth input means and outputting the selected signal; and the first, second and third signal switching means. A seventh signal switching means which receives the output signals of the respective adding means and outputs the selected signal, and a fourth signal which adds the output signals of the sixth signal switching means and the seventh signal switching means. And an eighth signal switching means for receiving the output signals of the first, second and third adding means and the input signal of the fifth input means and outputting the selected signal, Output of each of the first, second and third adding means A ninth signal switching means for receiving a force signal and outputting a selected signal; and a fifth adding means for adding the output signal of the eighth signal switching means and the output signal of the ninth signal switching means. And an output signal of the first storage means, an output signal of the first addition means, and an output signal of the fourth addition means are input,
A tenth signal switching means for outputting the selected signal; an output signal of the fourth storage means obtained by delaying the output signal of the tenth signal switching means for one horizontal scanning period; and a tenth signal switching means of the tenth signal switching means. Eleventh signal switching means that receives the output signal and outputs the selected signal, first output means that outputs the output signal of the eleventh signal switching means, and output signal of the second storage means And the output signal of the second adding means and the output signal of the fifth adding means are input,
A twelfth signal switching means for outputting the selected signal; an output signal for the fifth storage means for delaying the output signal for the twelfth signal switching means by one horizontal scanning period; and a twelfth signal switching means. Thirteenth signal switching means for outputting the input and selected signal, second output means for outputting the output signal of the thirteenth signal switching means, and one horizontal input by the third input means The output signal of the third storage means delayed by the scanning period, the output signal of the third addition means, and the image pickup signal input from the sixth input means are input, and a selected signal is output. Signal switching means, and the output signal of the sixth storage means obtained by delaying the output signal of the fourteenth signal switching means by one horizontal scanning period and the output signal of the fourteenth signal switching means are input and selected. A fifteenth signal switching means for outputting a signal; Third output means for outputting the output signal of the signal switching means, fourth output means for outputting the output signal of the fourth adding means, output signal of the fifth adding means, and the third A sixteenth signal switching means for receiving the signal input by the inputting means and the output signal of the third storage means and outputting the selected signal; and a sixteenth signal switching means for outputting the output signal of the sixteenth signal switching means 5. An image pickup apparatus comprising: 5 output means; and storage control means for arbitrarily controlling writing and reading of the first, second, third, fourth, fifth and sixth storage means. . 2. A first input for inputting three input image pickup signals
The second and third input means and the signals from the first, second and third input means, respectively, are input and the input signals can be held for one horizontal scanning period. A signal selected by the third storage means, and the image pickup signals input from the first, second and third input means and the output signals of the first, second and third storage means, respectively. For outputting the first, second and third signal switching means, and the fourth, fourth signal switching means capable of holding the signals respectively output from the first, second and third signal switching means for one horizontal scanning period. The fifth and sixth storage means, the output signals of the first, second and third storage means and the output signals of the fourth, fifth and sixth storage means, respectively, are input and selected signals are input. Outputs the 4th, 5th and 6th signal off Switching means and the output signal of the fifth signal switching means from odd pixel (1,
Pixel dividing means for dividing each pixel into 3rd, 5th ... (third pixel) and even-numbered pixels (2, 4, 6, ... th pixel) and outputting a signal sequence of two systems, and the fourth signal switching means. An output signal and a first output of the pixel dividing unit are input, a seventh signal switching unit that outputs a selected signal, an output signal of the sixth signal switching unit, and a second output of the pixel dividing unit. Eighth signal switching means that receives the output and outputs the selected signal, and first, second and third outputs that output the output signals of the seventh, fifth and eighth signal switching means, respectively. An image pickup apparatus comprising: a storage unit; and a storage control unit that arbitrarily controls writing and reading of each of the storage units. 3. A first system for inputting three systems of input imaging signals
Second and third input means, first, second and third storage means for holding the input image pickup signal as an image pickup signal for one horizontal scanning period, and input from the first and second input means Odd pixels
(1,3,5 ... th pixel) and even pixels (2,4,6 ...
Pixel combining means for switching two systems of signals divided for each pixel into (1st pixel) and combining them into one system of signals; an image pickup signal input from the third input means, and the pixel combining means. First signal switching means for receiving an output signal and outputting a selected signal; and an output signal for the first storage means, which is input from the first input means and delayed by one horizontal scanning period, and the first signal switching means. A second signal switching means for receiving the image pickup signal inputted from the first input means and outputting a selected signal; and the second signal switching means inputted from the second input means and delayed by one horizontal scanning period. The output signal of the storage unit and the image pickup signal input from the second input unit are input, and the third signal switching unit that outputs the selected signal, and the output signal of the first signal switching unit are one horizontal The third delayed scanning period A fourth signal switching means for receiving the output signal of the storage means and the output signal of the first signal switching means and outputting the selected signal; and the fourth, second and third signal switching means respectively. Fourth, fifth and sixth storage means capable of holding the output signal for one horizontal scanning period, and output signals of the first, second and third storage means and the fourth, fifth and sixth storage means, respectively. The fifth, sixth and seventh signal switching means for receiving the output signal of the sixth storage means and outputting the selected signal, and the output signals of the fifth, sixth and seventh signal switching means, respectively. An image pickup apparatus comprising: the first, second and third output means for outputting, and a storage control means for arbitrarily controlling writing and reading of the respective storage means.