JPH0817479B2 - Vertical filter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is a so-called NTSC interlace system having 525 scanning lines and 30 frames per second for a so-called MUSE band-compressed HDTV signal with 1125 scanning lines. The present invention relates to a vertical filter circuit for converting the number of scanning lines used in a MUSE / NTSC converter for converting into a signal for use in scanning.

[Conventional technology]

A so-called high-definition television signal proposed as a high-definition television has one frame consisting of two fields, the number of scanning lines in one frame is as many as 1125, and the aspect ratio of the screen is 9:16. The system is different from the conventional NTSC interlaced signal in which one frame is composed of two fields, the number of scanning lines in one frame is 525, and the aspect ratio of the screen is 3: 4.

Therefore, it is necessary to convert the number of scanning lines in order to receive the same high-definition broadcast signal with the conventional NTSC system device.

Fig. 6 shows a high-definition image with an aspect ratio of 9:16 of 3: 3.
It is a figure embedded in the screen for NTSC signal reproduction of 4, when the number of scanning lines is converted to 1/3 using a vertical filter, or it is converted to 2/5 and the screen of 9:16 high-definition When it is inserted into the screen for NTSC signal reproduction as an NTSC interlaced signal with the same aspect ratio, the horizontal direction should be 1/3 or 2/5 to prevent image distortion. It is necessary to perform time-axis compression.In the former case, the compression rate is high, blank areas with no image occur on the left and right sides of the screen for NTSC signal reproduction, and the screen for NTSC signal reproduction cannot be effectively used. If the compression rate is low,
There was a problem that the left and right sides of the high-definition screen protruded from the screen for NTSC signal reproduction, and part of the high-definition image was lost.

[Problems to be Solved by the Invention]

Therefore, in order to display the high-definition image as the NTSC interlaced signal by filling the horizontal direction of the screen for NTSC signal reproduction, the vertical direction of the high-definition image may be converted to 4: 1.5. Is the number of scan lines 112
It is an object of the present invention to provide a vertical filter circuit that compresses 516 luminance signal scanning lines in one field included in 5 high-definition MUSE signals to 1.5 / 4 and converts it into an NTSC interlaced signal.

[Means for solving the problem]

FIG. 5 is an explanatory view showing the positional relationship of scanning line conversion of a vertical filter used in the MUSE / NTSC converter showing one embodiment of the present invention. As shown in FIG.
A luminance signal having 516 scanning lines in one field, which is extracted by converting the SE signal into a digital signal, is input to a vertical filter, and the same vertical filter is used to form four adjacent solid lines of the 516 luminance signal scanning lines. 7/8 to 1st of scan lines, 2nd
Is added with 1/8 weighted to extract the first scanning line indicated by the dotted line, and the second and third weights are added with 1/2 weighted and added to the second scanning line indicated by the dotted line. Extract the line,
The third scanning line is weighted by 1/8 and the fourth is 7/8 and added to extract the third scanning line indicated by the dotted line. By repeating the same procedure, the number of scanning lines is compressed to 3/4. So NTSC
Converted to non-interlaced signal.

Alternatively, instead of using the weighting values of 1/8 and 7/8, the numerical values of 1/6 and 5/6, which are approximations of the same values, are used and the weighting shown in parentheses in FIG. The number of scanning lines of the luminance signal is compressed to 3/4 by extracting the scanning lines.

Further, one out of every two scanning lines compressed to 3/4 is extracted and converted into an NTSC interlaced signal.

[Action]

According to the present invention, as shown in FIG. 5, of the 1125 scanning lines of one frame of the MUSE signal, each of the 516 luminance signal scanning lines for one field of 60 Hz is converted from four to three scanning lines to convert the scanning lines. I changed it, I converted 516 lines to 387 scan lines,
Furthermore, by converting each of the 387 scanning lines from 2 to 1 and changing the number of scanning lines, 387 lines are converted into 193.5 scanning lines, and an NTSC interlace signal of 60 fields per second is obtained. I have to.

The number of effective scanning lines in one field of the signal for NTSC interlace is 241.5, and the difference from 193.5 is the blank part without the video signal, but processing such as superimposing the DC component on the blank part is performed. In the horizontal direction, the time axis compression is performed at a compression ratio of 3/4 to fill the horizontal direction of the screen for NTSC signal reproduction, and the high-definition image has an aspect ratio of 9:16.
It can be displayed as is.

〔Example〕

FIG. 1 is a block diagram of an electric circuit of a main part of a MUSE / NTSC converter showing an embodiment of the present invention.
Number of scanning lines extracted by converting SE signal to digital signal 11
516 luminance signals for 1 field out of 25 are input to the vertical filter via the input terminal 1. The video signal α input by the vertical filter is branched, and the same is branched to output the first signal. The signal β input to the 1H delay circuit 2 is output, the signal β delayed by 1H is output, the output of the signal β is branched and one is input to the adder 3, and the adder 3 adds from the second branch of the input signal. The added input video signal α is added to output the signal of α + β and input to the multiplier 6 for multiplying by 1/2, and the multiplier 6 outputs 1
Multiply by / 2 to output a 1/2 ・ (α + β) signal, and then 1/2 ・ (α
The signal output of + β) is branched, and one of the branched signals is input to the selector 10.

The other one of the branched 1/2. (Α / β) signal outputs is 1
It is input to the multiplier 7 that multiplies / 4, multiplied by 1/4 in the multiplier 7, and a signal of 1/8 · (α + β) is output and input to the adder 9.

The input video signal α from the third branch of the input signal is input to the selector 4, and the other branch of the output of the signal β is input to the selector 4, and the control signal applied to the selector 4 The signal α or the signal β is output by 1 and input to the multiplier 5 that multiplies 3/4, and the multiplier 5 outputs 3
Multiply by / 4 to output a 3/4 ・ α or 3/4 ・ β signal,
It is input to the adder 9.

The 3/4 · α or 3/4 · β signal is added to the 1/8 · (α + β) signal added by the adder 9 to obtain 1 /
The signal of 8 · (7α + β) or 1/8 · (α + 7β) is output to the selector 10.

In the selector 10, the 1/2. (Α + β) signal input by the control signal 2 being added and the 1/8. (7α +
Either the β) signal or the 1/8 · (α + 7β) signal is selected and output and input to the FIFO (abbreviation of Fast In Fast Out) type memory 11, and the writing that is input in the memory 11 Read by control signal Write and read the input signal by the control signal and output, branch the output and branch it to input 1H delay circuit 20 and 1H delay circuit 20 input signal 1H The delayed and output signal is added to the adder 21, and the other branched signal is directly input to the adder 21 to be added to the 1H-delayed signal by the adder 21 and output.
It is input to the memory 22, multiplied by 1/2 by the multiplier 22, and then output.
Are typing in.

A FIFO (abbreviation of Fast In Fast Out) type memory is used as the memory 23, and as shown in FIG. 5, it is extracted from each two luminance signal scanning lines of the NTSC non-interlaced signal. In order to convert the signal into an interlaced signal, the read speed is set to 1/2 of the write speed and the read operation is performed from the memory 23. If the odd lines of the NTSC interlaced signal are converted, the even lines will be converted in the next field.
High-definition MUSE input by output to
Compress the luminance signal of 516 lines per field of the signal to 1.5 / 4
Convert to NTSC interlaced signal.

In the above embodiment, the explanation is made using the multiplier. However, instead of using the multiplier, the bit shift and the adder are used, and the bits of the input signal are shifted and shifted. The signals may be added together. The use of multipliers complicates the circuit and increases the circuit scale, but there is an advantage that the circuit scale can be reduced by only bit shifting and addition. Alternatively, the coefficient ROM may be used instead of using the multiplier, and the coefficient inside the coefficient ROM and the input signal may be calculated and output.

Further, although multipliers 3/4 and 1/4 are used for the multipliers 5 and 7, respectively, multipliers 2/3 and 1/3 may be used, respectively. In this case, as shown in case II in FIG.
The memory 11 has a signal of 1/2 · (α + β) and 1/6 · (5α +)
The signal of β) and the signal of 1/6 · (α + 5β) will be input.

FIG. 2 is an electric circuit block diagram of the control circuit for supplying the control signal in FIG. 1. Reference numeral 30 is a line counter, and the number of scanning lines is 1125, which is a high-definition MUSE signal converted into a digital signal as an input signal and extracted. 516 luminance signal data for one field of the book are input, and the LSB digit of the line count 0 (LC0) and the line count 1 (LC
The digit before the LSB of 1) is output as a control signal, and the line counter 30 counts the lines to input the timing signal to the read control signal generation circuit 37. In the signal generating circuit 37, the 129th line from the beginning of the field is at the L level and the H level is set at the 130th line as shown in FIG. 3, and the read control signal for outputting the H level period up to 516 lines is output. I have to.

The output from the read control signal generation circuit 37 is input terminal 16
The data is input to the memory 11 shown in FIG. 1 via the read data, and the written data is read during the H level period of the read control signal.

The line count 0 signal from the line counter 30 is branched and input to the inverter 32 and the AND circuits 33 and 35. The inverter 32 inverts the polarity of the input signal and outputs it. The output is branched so that one is output as the control signal 2 and the other branched is input to the AND circuit 34. There is.

FIG. 4 is an explanatory diagram showing the polarity of the control signal and the write state of the memory in the electric circuit block diagram of FIG. 1, and when the value of the line count 0 is 1 as shown in FIG. Outputs L level signal and line count 0
When the value of 0 is 0, an H level signal is output as the control signal 2. The control signal 2 is input to the selector 10 shown in FIG.
Reference numeral 10 outputs the input signal A from the adder 9 when the control signal 2 is at the L level, and outputs the input signal B from the multiplier 6 when the control signal 2 is at the H level.

The signal of line count 1 from the line counter 30 is branched and input to the inverter 31 and AND circuits 33 and 34. The inverter 31 inverts the polarity of the input signal and outputs the inverted signal to the AND circuit 35. AND circuit
The signal from the line count 0 is also input to 35, and when the signal of line count 1 is 0 and the signal of line count 0 is 1 as shown in FIG. Is output, and an L level signal is output in other cases, and the output from the AND circuit 35 is branched and one of them is input as the control signal 1 to the selector 4 shown in FIG. And the other branched one is input to the OR circuit 36.

The selector 4 outputs the input signal A from the 1H delay circuit 2 when the control signal 1 is at the H level, and outputs the input signal B from the input terminal 1 when the control signal 1 is at the L level.

The OR circuit 36 is added with the outputs from the AND circuits 33, 34 and 35. When the signal of line count 1 is 0 and the signal of line count 0 is 0 as shown in FIG. A signal is output, and an H level signal is output in other cases, and the output is used as a write control signal in the input terminal 15
Input to the memory 11 shown in FIG. 1 via
11 is a selector only when the write control signal 1 is at H level
I am trying to write the output from 10.

Similarly to the read control signal, the write control signal 2 counts the lines by the line counter 30 and inputs the timing signal to the write control signal generation circuit, and the write control signal generation circuit writes the control signal to the memory 23. Is generated (not shown).

〔The invention's effect〕

As described above, according to the present invention, the number of scanning lines is 1125.
The number of scanning lines of the MUSE signal of the high-definition book can be compressed to 1.5 / 4 and converted to the signal for NTSC interlace,
By compressing the horizontal time axis by 3/4, a vertical filter circuit that makes it possible to display a high-definition image with the aspect ratio of 9:16 and fill the horizontal direction of the screen for NTSC signal reproduction is displayed. Can be provided.

[Brief description of drawings]

FIG. 1 is an electric circuit block diagram of an essential part of a MUSE / NTSC converter showing an embodiment of the present invention, and FIG. 2 is an electric circuit block diagram of a control circuit for supplying a control signal in the electric circuit block diagram of the same. FIG. 3 is a waveform diagram of control signals in the electric circuit block diagram of the above, FIG. 4 is an explanatory diagram showing polarities of control signals and a writing state of the memory in the electric circuit block diagram of the same,
FIG. 5 is an explanatory diagram showing the positional relationship of scanning line conversion of a vertical filter, and FIG. 6 is an explanatory diagram in which a high-definition image with a screen aspect ratio of 9:16 is fitted into a 3: 4 NTSC signal reproduction screen. Is. 1,13,14,15,16 …… Input terminal, 2,20 …… 1H delay circuit, 3,
9,21 …… Adder, 4,10 …… Selector, 5,6,7,22 …… Multiplier, 11,23 …… Memory, 24 …… Output terminal, 30 …… Line counter, 31,32… … Inverter, 33,34,35 …… AND circuit, 36 …… OR circuit, 37 …… Read control signal generation circuit.

Claims (5)

[Claims] 1. A brightness signal scanning line extracted by converting a high-definition signal into a digital signal is subjected to arithmetic processing as a group of four adjacent scanning lines of the same scanning line and converted into three scanning lines, and each scanning line is converted. The number of luminance signal scanning lines is compressed so that the vertical intervals of all the scanning lines converted from are equal to each other and are converted to standard television non-interlaced signals. A vertical filter circuit, characterized in that one out of each two of the luminance signal scanning lines converted into a signal for use in a signal is extracted and converted into a signal for interlace of a standard television. 2. The first scanning line is extracted by weighting first 5/6 and second 1/6 of four adjacent scanning lines of the luminance signal scanning line, and adding the weighted lines to extract the first scanning line. The second and third weights are each weighted by 1/2 and added to extract the second scan line, and the third weighted 1/6 and fourth are weighted by 5/6 and added to 3
The second scanning line is extracted, and the same procedure is repeated to compress the number of scanning lines to 3/4, and further, one out of every two scanning lines compressed to 3/4 is extracted. The vertical filter circuit according to claim 1. 3. A first adder in which the vertical filter branches an input signal and an output circuit of a signal obtained by delaying the input signal by 1H, and adds one of the branched signals to each other, and the first adder. Multiplier that multiplies the output from the multiplier by 1/2, and the output of the first multiplier is branched and one of the branched is input to the first selector and the other is input to the second multiplier. And a second selector for branching the circuit for inputting to the second adder after multiplying 1/3 by the second multiplier and the output circuit for the signal obtained by delaying the input signal by 1H. And a third multiplier that multiplies the output from the second selector by 2/3,
A circuit for inputting the output from the third multiplier to the second adder, adding the output from the second multiplier and inputting to the first selector, and the line from the output from the first selector A circuit that writes and reads to and outputs from the first memory according to the control signal from the counter, and branches the same output to 1H for one
A circuit for delaying and adding to the third adder and adding the other directly to the third adder and adding to the signal delayed by 1H and outputting the same, and multiplying the output by 1/2 and inputting to the second memory And a circuit for writing an input signal to the second memory and reading the written signal at half the speed at the time of writing and outputting the read signal. The vertical filter circuit described. 4. The first scanning line is extracted by weighting the first scanning line of 7/8 and the second scanning line of 1 of the four adjacent scanning lines of the luminance signal scanning line, and adding the weighted lines. 1/2 for the second and third
And then add to extract the second scan line,
The third weighting of 1/8 and the fourth weighting of 7/8 are performed and added to extract the third scanning line, and the same procedure is repeated to compress the number of scanning lines to 3/4. The vertical filter circuit according to claim 1, wherein one out of every two scanning lines compressed to 3/4 is extracted. 5. A first adder, wherein the vertical filter branches an input signal and an output circuit of a signal obtained by delaying the input signal by 1H, and adds the branched ones to each other, and the first adder. Multiplier that multiplies the output from the multiplier by 1/2, and the output of the first multiplier is branched and one of the branched is input to the first selector and the other is input to the second multiplier. And a circuit for inputting to the second adder after multiplying 1/4 by the second multiplier and an output circuit for outputting a signal obtained by delaying the input signal and the input signal by 1H are second selectors. And a third multiplier that multiplies the output from the second selector by 3/4,
A circuit for inputting the output from the third multiplier to the second adder, adding the output from the second multiplier and inputting to the first selector, and the line from the output from the first selector A circuit for writing and reading to and outputting from a memory by a control signal from a counter, and branching the output to delay one of them by 1H and add it to a third adder, and directly add the other to the third adder and delay it by 1H. And a circuit for adding the same to the output signal and multiplying the output by 1/2 and inputting to the second memory
5. A vertical filter circuit according to claim 1, further comprising a circuit for writing an input signal to a memory, reading the written signal at a half of a writing speed, and outputting the read signal. .