JP3113464B2 - Television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention displays an image having an aspect ratio of 4: 3 as in the NTSC broadcasting system and an image having an aspect ratio of 16: 9 as in the HDTV broadcasting system on a common screen. The present invention relates to a television receiver that can be used.

[0002]

2. Description of the Related Art A television receiver capable of receiving a high-definition broadcast system has a 16: 9 aspect ratio screen, and can display not only a high-definition broadcast but also a television signal of an NTSC broadcast system. ing.

Since this television receiver has a 16: 9 aspect ratio screen as described above, all television signals of high-definition broadcasting can be displayed on the screen. Since the John signal is a 4: 3 screen, when the screen is displayed on a 16: 9 television receiver, the following display method is used.

[0004] First, as a first method, a television signal of the NTSC broadcasting system is made to correspond to the horizontal direction of a 16: 9 screen, and the upper and lower sides of the television signal are truncated. As a method, there is a method in which a television signal is made to correspond to the vertical direction of a 16: 9 screen, and blanking (non-image portion) is formed on the left and right screens.

However, in the first method described above,
Since a part of the television signal is truncated, the screen becomes difficult to see. Further, in the second method, the left and right screens become non-image portions, １ ／ of the screen width is wasted, and the images themselves are poor images.

In order to solve these problems, conventionally,
A method for effectively using a screen without truncating any images having different aspect ratios is disclosed in
No. 72 (H04N7 / 01).

According to this conventional technique, for example, three screens of a 4: 3 image are displayed in a small screen in the right corner, and 4: 3 in the left corner.
The effective use of the screen is achieved by displaying a large parent screen.

On the other hand, it has been proposed that a 16: 9 television receiver can simultaneously receive and display Hi-Vision broadcasts and NTSC broadcasts. In this case, a parent screen is transmitted by a Hi-Vision signal (or NTSC signal). Displaying the screen with an NTSC signal (high-definition signal) enables simultaneous viewing.

When a small-screen signal is generated, as is generally known, for example, Japanese Patent Publication No. 56-28
As disclosed in Japanese Patent Application Publication No. 21 (H04N5 / 44), a television signal is obtained as a compressed image signal obtained by thinning out the scanning lines of the image signal of the sub-screen and storing it in a memory, doubling the reading from the memory or the like. Displayed on the receiver.

In such a sub-screen creation method, if the main screen signal and the sub-screen signal are signals of the same system, the thinning-out of the image signal to be written into the memory of the sub-screen can be performed according to a conventional rule. However, if the parent screen signal and the child screen signal are different signals, the degree of thinning out to the child screen must be changed according to the broadcasting method of the parent screen.

That is, when the broadcasting system of the main screen is a signal of the high-vision broadcasting system and the broadcasting system of the sub-screen is a signal of the NTSC broadcasting system, the number of scanning lines of the main screen is 1125,
Since it is necessary to consider the thinning of the number of scanning lines of the child screen based on the number of scanning lines, the thinning is performed by 2/3 (350 lines).
Need to be

In this manner, a part (3
A range of (50 lines) scanning lines is displayed as a child screen.

On the other hand, when the parent screen and the child screen are both of the high-definition broadcasting system, the thinning of the child screen is reduced to 1/3.
(For 375 lines).

Therefore, it is necessary to change the thinning of the number of scanning lines according to each state. For this purpose, a vertical filter for thinning out the number of scanning lines according to each state has conventionally been constructed using a circuit as shown in FIG.

Here, the circuit configuration of FIG. 8 will be described. First, 20, 21 and 22 are delay memories for delaying one horizontal scanning period, 23 and 25 are 倍 multipliers, 24, 26 and 2
7, 28 are 1/4 multipliers, 29, 30, and 34 are selectors, 31, 32, and 33 are adders, and 35 is a gate circuit.

Next, the operation will be described. First, when an image signal of a small screen is input, each of the delay memories 20, 21, 22
Through respective multipliers 23, 24, 25, 26, 2
7 is input.

The vertical sampling (decimation of the number of scanning lines) is determined as shown in FIG. 2 according to the state of the television broadcasting system of the parent screen and the child screen. Here, the number of scanning lines is 1125 for the high-definition system and 5 for the NTSC system.
There are 25 lines, and vertical sampling is determined according to the number of scanning lines.

The vertical deflection enlargement of the NTSC system is a mode in which the number of scanning lines is 525 and the image is stretched in the vertical direction. The number of scanning lines of the molecular screen stretched in the vertical direction is the same as that of the normal NTSC system. Since the number of scanning lines increases and the screen becomes vertically long, sampling is performed to further reduce the number of scanning lines.

Then, by the vertical sampling, the coefficient of the multiplier is also selected as shown in FIG. 3, and the final output is also selected.

For example, when the vertical sampling is 2/3,
As for the image signal, the current signal is selected by the selector 29 through the 乗 算 multiplier 23, and 1H through the delay memory 20 is selected.
The selector 3 outputs the previous signal through the 乗 算 multiplier 25.
0 is selected and added by the adder 31. Then, the output is selected by the selector 34 and output from the gate circuit 35 composed of AND.

Incidentally, VSPL, for example, when extracting two lines from the number of three scanning lines, is performed only for the first two scanning lines, and is not performed for the subsequent one scanning line. This is a signal to stop the gate circuit so as not to perform.

The control signals S3, S4, S5 for controlling the selectors 29, 30, 34 are output in accordance with the above-described vertical sampling.

However, in such a conventional technique, FIG.
As shown in FIG.
(4, 1/4, 1/4) requires three delay memories, so that the circuit scale is disadvantageously increased.

Therefore, when the configuration is such that the delay memory is reduced by one, that is, in FIG.
And the adder 33 becomes unnecessary, but when the vertical sampling number is smaller than 1/3 (for example, 1/4, etc.), (1/4, 1 /
(2,1 / 4) was noticeable.
That is, when the number of scanning lines is reduced to 1/4, 3 out of 4 scanning lines are used.
One scanning line number is created from the number of scanning lines, and the remaining one is discarded, and information for one line is lost, so that image deterioration occurs.

Further, similar circuits exist for each of the luminance signal and the color difference signal, and the circuit scale has been increased.

[0026]

SUMMARY OF THE INVENTION According to the present invention, there is provided a simple circuit for displaying image signals of different broadcasting systems on the same screen without deteriorating the image quality of a small screen. It is an object of the present invention to provide a television receiver provided with a vertical filter circuit for creating a child screen which can be configured by using a television receiver.

[0027]

According to the present invention, there is provided a means for simultaneously receiving image signals of different broadcasting systems, and receiving an image signal of a main main screen displayed on a television screen. A television receiver comprising a display means for receiving an image signal of a child screen displayed on a television screen smaller than that of the television screen and simultaneously displaying the parent screen and the child screen on the television screen. Multiplication means for multiplying the weighting coefficient for each scanning line of the image signal, delay means for delaying the output from the multiplication means, addition means for adding the output from the delay means and the output from the multiplication means,
First selecting means for selecting a coefficient of the multiplying means, output from the multiplying means, second selecting means for selecting an output from the adding means and inputting it to the delay means, and an output from the adding means. Output means for outputting one scanning line from a plurality of scanning lines of the image signal of the child screen.

[0028]

According to the present invention, by switching the vertical sampling number and the vertical filter coefficient by the switch according to the above configuration, it is possible to obtain an image signal of a small picture without image quality deterioration.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. First, in FIG. 1, reference numeral 1 denotes a multiplex circuit, which is an A / D for a luminance signal.
It includes a converter, an A / D converter 5 for color difference signals, and a multiplexer circuit 6 for luminance / color difference signals.

Numeral 2 denotes a vertical filter circuit, a 1/2 multiplier 7 and a 1/4 multiplier 8, and changeover switches 9, 10, and 1
A delay memory for delaying the horizontal scanning period, an adder 12, and an overflow circuit 13 are incorporated.

3 is a multiplexer circuit, 14,
Reference numeral 15 denotes a gate circuit, and reference numeral 16 denotes a timing signal generation circuit.

Next, the operation will be described with reference to FIGS. First, description will be made with reference to FIGS. First, the input luminance / color difference signals of the child screen are time-division multiplexed by the multiplex circuit 1. Horizontal sampling clock AD
The A / D converter 4 for luminance signal converts the signal into a 6-bit digital signal A by the CK, and the digital signal B by the A / D converter 5 with built-in multiplex for chrominance signal. It becomes a division multiplex signal C.

Then, the data is input to the vertical filter circuit 2 and subjected to a filtering process. A 倍 -times multiplier 7, a 倍 -times multiplier 8 and a changeover switch 9 comprising a bit shift circuit,
If the switching signal S1 is "H", the filter coefficient is halved,
If "L", the filter coefficient is selected to 1/4 and the signal is multiplied.

Next, the adder circuit 12 adds the current input data to 1
After the previous data is added and the operation result is subjected to overflow processing, one horizontal period delay memory input stage switching circuit 1
0 is input to the demultiplexer 3 as the vertical filter output signal D using the upper 6 bits of the 8-bit signal.

Here, the input stage changeover switch 10 of the one horizontal period delay memory 11 selects the signal of the changeover switch 9 if the changeover signal S2 is "H", and selects the signal of the overflow processing circuit 13 if the changeover signal S2 is "L" and sends it to the memory. input.

Then, in the demultiplexing circuit 3, D
The luminance signal is latched at the rising edge of the MPX signal, and the color difference signal is latched at the falling edge.

With the above processing, the timing signal generator 17
Performs control based on the synchronization signals Hsync and Vsync of the sub-screen, the main screen display high-definition / NTSC switching signal, the sub-screen input high-vision / NTSC switching signal, and the main screen vertical deflection width switching signal. (That is, by designating the vertical sampling as shown in FIGS. 2 and 3, the control signals S1 and S2 are switched and controlled accordingly.) Next, using FIGS. The operation will be described. First, when the vertical sampling is 2/3,
As shown in FIG. 5A, the changeover switch 9 switches on the 側 multiplier 7 side, and the adder 12 always adds the signal passed through the delay memory 11.

The output is output to the gate circuits 14, 1
5 to VSPL signals are output only during the “H” period, so that 2/3 vertical sampling can be performed.

When the vertical sampling is 1/3,
As shown in FIG. 5B, the first and last scanning lines among the three scanning lines are 1/4 times, and the interval between them is 1/2 times. Then, the delay memory 11 first adds the previous scanning line, and then adds the delay output from the output,
The final output.

On the other hand, when the vertical sampling is 1/4,
As shown in FIG. 6 (c), the delay memory 11 also delays only the first scanning line while switching to the 1/4 side, and thereafter circulates through the delay output on the output side to obtain the final output. ing.

Further, when the vertical sampling is 1/6,
As shown in FIG. 6 (d), the delay memory 11 also delays only the first scanning line while switching to the 側 side, and thereafter circulates through the delay output on the output side to obtain the final output. ing. However, in this case, the output e,
f is not output, but is output at the previous timing (VSPL).

FIG. 4 is a diagram showing the relationship between the number of vertical samplings and the sampling points for each field. As can be seen from the figure, the vertical 2/3 sampling does not shift the sampling point of the second field with respect to the first field, but the vertical 1/3 and 1/4 sampling does not shift the second field sampling point.
Shift the sample point of the field by one line,
/ 6 sampling shifts by 2 lines, and vertical 1/8
By shifting by 3 lines in sampling,
Improves the interlace relationship after reducing the inset screen.

As described above, it is possible to realize a vertical filter circuit for creating a small screen that can perform a plurality of vertical samplings with a simple circuit configuration.

[0044]

According to the present invention, when a high-definition signal is displayed as a parent screen, NTSC signals are displayed by performing vertical deflection 60 HZ, horizontal deflection 33.75 KHZ, 1125 scanning lines, and 2: 1 interlace display. In the case, the vertical deflection is 120 HZ, the horizontal deflection is 31.47 KHZ,
In a television receiver capable of switching to 525 scanning lines and 2: 1 interlace display, the main screen
By optimally switching the vertical sampling number and the vertical filter coefficient according to the display state of the small screen, the image quality of the small screen can be improved. Further, since the vertical filter circuit can perform the one horizontal period delay memory for the luminance signal and the color difference signal, the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence between a main screen / child screen state and the number of vertical samplings.

FIG. 3 is a diagram showing the correspondence between the number of vertical samplings and vertical filter coefficients.

FIG. 4 is a diagram showing the relationship between the number of vertical samplings and sampling points for each field.

FIG. 5 is a diagram showing a relationship between 2/3 and 1/3 vertical sampling numbers and sample points for each field.

FIG. 6 is a diagram showing a relationship between 1/4 and 1/6 vertical sampling numbers and sampling points for each field.

FIG. 7 is a diagram showing timing of multiplex / demultiplex.

FIG. 8 is a diagram showing a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplex circuit 6 Multiplex circuit 2 Vertical filter circuit 3 Demultiplex circuit 4 A / D converter for luminance signal 5 A / D converter for color difference signal 7 1/2 multiplier 8 1/4 multiplier 9 Switch DESCRIPTION OF SYMBOLS 10 Changeover switch 11 1 Horizontal period delay memory 12 Adder circuit 13 Overflow processing circuit 14 Vertical gate circuit 15 Vertical gate circuit 16 Timing signal generator

Claims (2)

(57) [Claims] 1. A means for simultaneously receiving image signals of different broadcasting systems, an image signal of a main screen displayed on a television screen, and receiving an image signal of a main screen displayed on the television screen smaller than the main screen. A television receiver comprising a display means for receiving an image signal of a child screen displayed on a television screen and simultaneously displaying the parent screen and the child screen on a television screen, wherein for each scanning line of the image signal of the child screen, Multiplying means for multiplying the weighting coefficient; delay means for delaying the output from the multiplying means; adding means for adding the output from the delay means and the output from the multiplying means; and selecting the coefficient of the multiplying means. A first selection unit, an output from the multiplication unit, a second selection unit for selecting an output from the addition unit and inputting the output to the delay unit, a plurality of image signals of the child screen from the output of the addition unit Output means for outputting one scanning line from among the scanning lines. 2. A television receiver according to claim 1, wherein said multiplying means inputs a multiplexed luminance signal and color signal of a screen image signal. .