JP2687905B2 - Video signal converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to video signals, especially HD
TV video signal (1125 scanning lines, scanning method 2: 1 interlace, field frequency 60 Hz, aspect ratio 1
The present invention relates to a conversion device for converting an EDTV video signal (525 scanning lines, scanning non-interlace, field frequency 60 Hz, aspect ratio 16: 9) from a 6: 9).

[0002]

2. Description of the Related Art Generally, as a video signal conversion device, an HD
TV signal is NTSC signal (525 scanning lines, scanning method 2: 1 interlace, field frequency 60 or 5
A conversion device for converting to 9.94 Hz and an aspect ratio of 4: 3) is known. For example, as a conversion device of this type, there is a down converter device disclosed in Japanese Patent Laid-Open No. 01-126094. In this converter, after correcting the difference in scanning time due to the difference in aspect ratio with respect to 1125 scanning lines, the number of scanning lines (1050) is converted and the interlace of NTSC system with 525 scanning lines is converted. You are getting a signal.

On the other hand, as a conversion device for converting an HDTV signal into an EDTV signal, a television system converter described in Japanese Patent Laid-Open No. 2-261292 is known.
Further, as such a conversion device, Japanese Patent Laid-Open No. 4-2342
The television signal system conversion device described in Japanese Patent Publication No. 77 is known.

First, a signal processing circuit of a conventional television system converter will be outlined with reference to FIG.

The MUSE signal 201 input from the input terminal 20a is sampled by the A / D converter 21 at a sampling frequency of 16.2 MHz and becomes a sampled MUSE signal.
The sampled MUSE signal 202 is supplied to the scanning line number conversion circuit 22.
Is converted from a signal having 1125 scanning lines into a signal having 1050 scanning lines. The output of the scanning line conversion circuit 22 is 203
Is supplied to the non-interlace compatible luminance signal processing circuit 23 and the non-interlace compatible color signal processing circuit 24 and processed as described later. The output 204 of the non-interlace compatible luminance signal processing circuit 23 is passed through the D / A converter 25d and also the non-interlace compatible color signal processing circuit 24.
Outputs 205 and 206 of the D / A converter 25e
And 25f to the inverse matrix circuit 26b. The R, G, and B signals 210, 211, and 212 are output from the inverse matrix circuit 26b, and the output terminal 27
It is output from d, 27e, and 27f, respectively.

As described above, the sampling frequency is 16.2 MH.
The MUSE signal sampled by z is the scanning line number conversion circuit 22.
Is converted into a signal of 1050 scanning lines. This signal (1050 scanning lines) is an interlaced signal. The output of the scanning line number conversion circuit 22 is given to a non-interlaced luminance signal processing circuit 23 and a non-interlaced color signal processing circuit 24. Then, the non-interlaced luminance signal processing circuit 23 performs the following processing.

Since the MUSE signal is sub-sampled, interpolation processing is performed within the field.

In order to convert the number of scanning lines from 1050 to 525, band limitation is performed at 525/2 (cph) in the vertical direction.

From 1050 scanning lines interlace to 5
25 lines are converted to non-interlaced.

On the other hand, the non-interlaced color signal processing circuit 24 carries out the following processing.

Since the MUSE signal is sub-sampled, interpolation processing is performed within the field.

Band limitation is performed at 525/4 (cph) in the vertical direction.

1050 scanning lines, 525 scanning lines for interlaced color difference line sequential signal, non-interlaced R-
The Y signal is converted into a non-interlaced BY signal with 525 scanning lines.

Since the time axis of the color difference signal is compressed and transmitted, the time axis is expanded.

The luminance signal 204 which is the output of the non-interlace compatible luminance signal processing circuit 23 and the RY signal 205 and B- which is the output of the non-interlace compatible color signal processing circuit 24 obtained by the above processing. The Y signals 206 are respectively D / A converted, and further converted into RGB signals by the inverse matrix circuit 26b and output. Regarding the vertical misalignment between the luminance signal and the color signal, a memory is used for one of the non-interlaced luminance signal processing circuit 23 and the non-interlaced color signal processing circuit 24 to delay line by line. Can be solved by.
Further, the conversion of the aspect ratio is realized by reading the values of the required number of sample points in the scanning line number conversion circuit 22 described above.

In the above example, the case where the input signal is the MUSE signal has been described. However, the input signal is not limited to the MUSE signal, but may be a high-definition baseband signal (R, G, B signals). In the case of a baseband signal, the above-mentioned MUSE
Interpolation processing associated with the signal and time base processing of the color difference system are not necessary.

Another example of the signal processing circuit of the conventional television signal system converter will be described with reference to FIG.

A high-definition signal (for example, MUSE signal) is converted into a digital signal, and the luminance signal extracted from this digital signal is input to the first filter circuit 49. In the first filter circuit 49, with respect to the high-definition interlaced signal, in the odd field, one of the adjacent scan lines is weighted by 3/4 and the other is weighted by ¼ to convert the scan line, and in the even field. One of the adjacent scan lines is weighted by ¼ and the other is weighted by 3/4, and the scan lines are converted and output as standard television non-interlaced signals. Then, this non-interlaced signal is input to the second filter circuit 50. In the second filter circuit 50, one of the adjacent scanning lines is 1/2 and the other is 1 /.
2 is weighted and the scanning line is converted and output. Second
The output signal from the filter circuit 50 of FIG.
1, the odd-numbered scan lines and the even-numbered scan lines are alternately time-axis expanded to output an interlaced signal of a standard television signal. This standard television signal constitutes an odd field with odd-numbered time-axis expanded scan lines,
Even-numbered time-axis extended scan lines form an even-numbered field.

Referring also to FIG. 8, the first filter circuit 49 includes a delay circuit 31, adders 32 and 35, multipliers 34 and 36, and a selector 33, and a luminance signal delay circuit. 3, the adder 32, and the selector 33.

The delay circuit 31 delays the input signal (luminance signal) by one horizontal scanning period and outputs it. For example, when the input signal is the scanning line B of the odd field of the MUSE signal shown in FIG. 9, the output delayed by one horizontal scanning period by the delay circuit 31 corresponds to the scanning line A. The output from the delay circuit 31 is given to the adder 32 and the selector 33.
Therefore, the adder 32 adds and outputs the signal A delayed by the delay circuit 31 and the signal B before being delayed. The signal A + B is output from the adder 32, and the signal A + B is halved by the multiplier 34 to be supplied to the adder 35.

As shown in FIG. 8, a control signal detecting circuit 47 and a timing signal generating circuit 48 are provided as a control circuit of the selector 33. In the control signal detecting circuit 47, the MUSE applied via the input terminal 46 is provided. A frame pulse is detected from the signal and a frame pulse detection signal is given to the timing signal generation circuit 48. The timing signal generation circuit 48 generates an odd field identification signal and a signal which is inverted to an even field identification signal after a predetermined period of time, based on the input frame pulse detection signal.
That is, the timing signal generation circuit 48 generates an identification signal (field data) for identifying an odd field and an even field. Then, the identification signal is given to the selector 33 as a control signal. The selector 33 outputs the input from the delay circuit 31 in the odd field and outputs the input from the input terminal 30 in the even field according to the control signal. Therefore, in the case of the scanning line A and the scanning line B shown in FIG. 8, the signal of the scanning line A is output and given to the adder 35.

In the adder 35, the signal 1 / from the multiplier 34 is
The signal A is added to 2 (A + B) and given to the multiplier 36. In the multiplier 36, the output from the adder 35 is halved to 1/2 [A + 1/2 (A + B)] = 3 / 4A + 1. / 4
It is output as B and converted into the scanning line A1 of the non-interlaced signal of the standard television signal.

By the way, when the MUSE luminance signal in which the pixel data is interpolated is input as the MUSE luminance signal applied via the input terminal 30, the output from the multiplier 36 is the third filter. Given to the circuit. The third filter circuit includes a delay circuit 37 and an adder 3
8 and a multiplier 39. Then, the multiplier 36
The output from is supplied to the delay circuit 37 and the adder 38. The delay circuit 37 gives an output delayed by one pixel in the horizontal direction of the scanning line to the adder 38. The adder 38 adds the pixel sampling data and the horizontally adjacent interpolation data and outputs the result, and supplies this output to the multiplier 39.
The multiplier 39 takes an average value of the sampling data and the interpolated data. Then, the conversion process of the scanning line of the next stage is performed so as to maintain the continuity of the pixels in the horizontal direction by the data interpolation. If the pixel continuity in the horizontal direction due to data interpolation does not pose a problem, the processing by the third filter circuit is omitted and the output from the multiplier 36 is input to the second filter circuit 50 to scan lines. Is converted.

As shown in FIG. 8, the second filter circuit 5
0 includes a delay circuit 41, an adder 42, and a multiplier 43, and the above-mentioned non-interlaced signal is applied to the delay circuit 4
1 and the adder 42.

The delay circuit 41 delays the input signal (non-interlaced signal) by one horizontal scanning period and outputs it. For example, when the input signal is the scanning line B1 of the non-interlaced signal shown in FIG. 8, the output delayed by one horizontal scanning period by the delay circuit 41 corresponds to the scanning line A1. The output delayed by the delay circuit 41 is given to the adder 42, and the adder 42 adds and outputs the signal A1 delayed by the delay circuit 41 and the signal B1 before being delayed, and gives it to the multiplier 43. The multiplier 43 halves the input and outputs it.

In the same manner, the non-interlaced signal scanning lines of all standard television signals are converted by a combination such as B1 and C1 and C1 and D1 of the non-interlaced signal operation lines of the standard television signal and the time axis is converted. Input to the conversion circuit 51.

A FIFO (F
An IRST In FIRST Out) type memory 44 is used, and the memory 44 writes the non-interlaced signal scan lines A1 and B1 and the converted scan lines B1 and C1 output from the multiplier 43. And
Memory 4 at half the read speed compared to the write speed
4, the time axis is expanded and the odd-numbered scanning lines and the even-numbered scanning lines are alternately output. The odd-numbered time-axis-extended scan lines form an odd-numbered field,
Even-numbered scan lines extended in the time axis form even-numbered fields and output as interlaced signals of standard television signals.

In the above-mentioned conventional example, the multiplier is used for halving the data, but a bit shift and an adder are used instead of the multiplier to shift the bits of the pixel data, and the shifted pixel is shifted. The data may be added together. If a multiplier is used, the circuit becomes complicated and the circuit scale increases, but the circuit scale can be reduced by only bit shifting and addition. Alternatively, a coefficient ROM may be used instead of the multiplier, and the coefficient inside the coefficient ROM and the pixel data may be calculated and output.

[0029]

By the way, in the conventional example described with reference to FIG. 6, a high-definition signal is transmitted with an E ratio of 4: 3.
It is displayed on a display of DTV specification, and the 1125 scanning lines of the high-definition signal are converted into an interlaced signal of 1050 scanning lines, and the interlaced signal is made non-interlaced with 525 scanning lines. Therefore, the circuit becomes more complicated than directly converting a high-definition signal into a non-interlaced signal with 525 scanning lines, and 1125 scanning lines are converted from converting all 1050 scanning lines into 525 scanning lines. Direct conversion to 525 scanning lines is inferior in terms of image quality, considering that the image quality is not impaired.

On the other hand, in the conventional example described with reference to FIG. 7, a high-definition signal is converted into an NTSC system interlaced signal and an NTSC system non-interlaced signal. In this conventional example, the NTSC non-interlaced signal is incorporated as one of the processes for converting it into an interlaced signal. Therefore, an interlace conversion circuit unit is required for displaying on an EDTV display (525 scanning lines, scanning non-interlace, field frequency 60 Hz, aspect ratio 16: 9),
The circuit scale becomes large. Further, the time axis expansion processing synchronized with the EDTV video signal is not performed.

An object of the present invention is to provide a video signal conversion device for displaying an HDTV signal with high image quality on a display of EDTV specification with a simple structure.

[0032]

According to the present invention, there is provided a conversion device for converting an HDTV digital video signal in which one frame is composed of first and second fields into an EDTV digital video signal. Rate conversion means for speed-converting the video signal at the clock rate of the EDTV digital video signal to obtain a converted signal;
Delaying means for delaying the conversion signal by one scanning line to obtain a delay signal; and multiplying the conversion signal by a predetermined first coefficient in the first field to obtain a first multiplication signal, and the first multiplication signal. In the second field, the first signal is added to the delayed signal.
And a second generation means for obtaining a second multiplication signal by multiplying the coefficient by the second multiplication signal, and in the first field, the EDTV digital video signal is generated based on the first multiplication signal and the delay signal. In the field (1), there is obtained a video signal conversion device characterized by having a second generation means for generating the EDTV digital video signal according to the second multiplication signal and the conversion signal.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

First, referring to FIG. 1, a scanning line structure accompanied by signal conversion by the converter according to the present invention will be described. The solid line of HDTV shows the scanning line information of the first field, and the dotted line shows the scanning line information of the second field. The converted scanning line information E11 in the first field of the EDTV is HD
Between the scanning line information H11 and H12 of the first field of the TV, H11 and H12 are equally divided into four, and the ratio of the distance from H11 and the distance from H12 is 3: 1. . At this time, the scanning line information E11 is H11 and H.
It is inversely proportional to the spatial distance of 12 and is a value obtained by adding the value obtained by multiplying the information of H11 by 1/4 and the information of H12 by 3/4, respectively.

Hereafter, E12 and E13 are the values obtained by adding 1/4 of H12 and 3/4 of H13, respectively, as in E11.
It is a value obtained by adding 1/4 of H13 and 3/4 of H14.

In the second field, the spatial positions of the first and second fields of the EDTV are aligned,
Since the scanning is performed sequentially, the scanning line information E21 in the second field of the EDTV after conversion is converted to HD in the opposite manner to the first field.
Between the scanning line information H21 and H22 of the second field of the TV, the area between H21 and H22 is equally divided into four, and the information is the position where the ratio of the distance from H21 and the distance from H22 is 1: 3. . At this time, the scanning line information E21 is H21 and H.
It is inversely proportional to the spatial distance of 22, and is a value obtained by adding the value obtained by multiplying the information of H21 by 3/4 and the information of H22 by ¼, respectively.

Hereinafter, E22 is the same as E21 and is equal to 3 of H22.
It is a value obtained by adding / 4 and 1/4 of H23.

The addition of 1/4 and 3/4 as described above is a functional description, and in the actual circuit configuration,
If each scanning line is made 1/4 times and 3/4 times and the circuit is configured by the multiplier, the circuit scale becomes large, and each scanning line is made 1/4 by the bit shift.
If the calculation is performed as double, 3/4 times, the scanning line information is significantly reduced and the calculation error becomes large. Therefore, in an actual circuit, in order to reduce a calculation error, the information obtained by multiplying one by three and the information obtained by multiplying the other by one are added to obtain a quarter as follows.

E11 = (1/4) H11 + (3/4) H12 = [H11 + 3 (H12)] 1/4 E11: E11 of EDTV first field scanning line of FIG. 1 H11: EDTV first field scanning of FIG. Line H11 H12: EDTV first field of FIG. 1 H12 E21 of scanning line = (3/4) H21 + (1/4) H22 = [3 (H21) + H22] 1/4 E21: EDTV second field of FIG. Scanning line E21 H21: EDTV second field scanning line H21 H22 of FIG. 1: EDTV second field scanning line H22 of FIG. 1 Next, the video signal converting apparatus according to the present invention will be described with reference to FIG. .

HDTV Y, PB, and PR signals 101, 10 input to the input terminals 10a, 10b, 10c.
2, and 103 are matrix circuits 1 for HDTV G,
B and R signals 101, 105 and 106 are converted. These G, B, and R signals are sampled by the A / D converters 2a, 2b, and 2c, respectively, at the sampling frequency of HDTV. Sampled HDTV G, B, R
The signals 107, 108, and 109 are rate-converted by the rate conversion circuit 4 according to the timing signal from the timing generation circuit 9. That is, the rate conversion circuit 4 performs signal rate conversion. The G, B, and R signals 110, 111, and 112 whose rates have been converted by the rate conversion circuit 4
Are subjected to scan line conversion in the scan line conversion circuit 5 in order to create the above-mentioned scan line information. As a result, the scan line converted G, B, and R signals 113, 114, and 115 are respectively D / A converters 6a, 6b, and 6c.
ED with 525 scanning lines, scanning non-interlaced, field frequency 60Hz, aspect ratio 16: 9
The G, B, and R signals 116, 117, and 118 of the TV are output from the output terminals 60a, 60b, and 60c, respectively.

The HDTV Y signal 101 is also given to the sync separation circuit 7. The sync separation circuit 7 separates the horizontal sync signal HD and the vertical sync signal VD from the HD signal of the HDTV and synchronizes them. A signal FI having a field cycle for performing field identification is obtained from the signal. And
The PLL circuit 8 obtains an HDTV system clock signal HCK and an EDTV system clock signal ECK according to the horizontal synchronizing signal.

These HD, VD, FI, HCK, ECK
The signal 119 including the signals is given to the timing generation circuit 9, and the timing generation circuit 9 uses the signals such as the write clock of the field memory at the time of rate conversion, the read clock, the clocks at the time of scanning line conversion, and the like. Generating timing signals.

Here, the rate conversion circuit 4 and the scanning line conversion circuit 5 will be described with reference to FIG. In the illustrated example, only one field memory 3 and one scanning line conversion unit 5a are shown, but these field memories 3
There are three scanning line conversion units 5a and one scanning line conversion unit 5a, and one color process is performed by the pair of field memory 3 and scanning line conversion unit 5a. That is, the rate conversion circuit 4 is composed of three field memories 3, and the scanning line conversion circuit 5 is composed of three scanning line conversion units 5a.

The field memory 3 has the input terminals 3a through A
One of the outputs of the / D converters 2a to 2c is given (the processing is the same for the G, B, and R signals, so the G signal will be described here).

The rate conversion is performed by the field memory 3. The field memory 3 performs processing for converting the HDTV video signal into the clock rate of the EDTV video signal on the time axis. From the timing generation circuit 9, a write clock i for timing synchronized with the HDTV video signal is applied to the field memory 3. The sampling G signal is written as a write signal in the field memory 3 by the write clock i, and the write signal is read as a read signal from the field memory 3 by the read clock j at a timing synchronized with the EDTV video signal. Thereby, rate conversion is performed.

Further, in the line memory 10, in order to simultaneously retrieve the information of two scanning lines before and after in the same field of the signal when converting the scanning lines, one scanning line before
Delay the line. For example, when the signals c and d are the scanning line H12 of the first field of the HDTV signal shown in FIG. 1, the signal a delayed by one horizontal scanning period in the line memory 2 is used.
And b correspond to the scanning line H11.

The delayed output signal a from the line memory 10 is input to the selector 11, and the signal b is input to the selector 12. The signal c from the field memory 3 is supplied to the selector 11,
The signal d is input to the selector 12.

Here, the signals a and b are the HDT shown in FIG.
If the scanning line H11 of the V signal first field is used, the signal c
1 and d are the scanning lines H12 shown in FIG. 1. At this time, the selector 11 corresponds to the scanning line H12 as the first field by the field identification signal k in order to perform the processing to triple the scanning lines in the subsequent stage. The signal c is selected, and the selector 12 outputs the value of 3 obtained from the adder 13 in the subsequent stage.
In order to add the doubled scanning line data, the signal b corresponding to H11 is selected as the first field by the field identification signal k and output as signals e and f, respectively.

The signals a and b are HDTV shown in FIG.
If the scanning line H21 of the second field is the signal, the signals c and d are the scanning line H22 shown in FIG. 1. At this time, the selector 11 performs the processing for triple the scanning line in the subsequent stage, and therefore the field identification The signal a corresponding to the scanning line H21 is selected as the second field by the signal k, and the selector 12 adds the triple scanning line data obtained from the adder 13 in the subsequent stage. The signal d corresponding to the scanning line H22 is selected as two fields and output as signals e and f, respectively.

The field identification signal k is generated by the timing generation circuit 9 as a timing signal for identifying an odd field and an even field, whereby the selectors 11 and 12 are switched by the odd field signal and the even field signal. There is.

The output signal e of the selector 11 needs to triple the scanning line data as described above. this is,
Since 2e + 1e = 3e, the data doubled by the bit shift and the unchanged data that is 1x are input to the adder 13 to obtain the tripled output signal g. For example, selector 1
When the signal e obtained from 1 is 8-bit data, the doubled data becomes 9 bits, and the output signal g when adding the 8-bit data as it is with the adder 13 is 10 bits.
Bit.

The output signal g tripled by the adder 13 and the output signal f as it is obtained from the selector 12 are input to the adder 14, and the output is bit-shifted to 1
The signal h is obtained as / 4 data.

Here, when the signal g corresponds to a signal obtained by triple the scanning line H12 of the first field of the HDTV signal shown in FIG. 1, the signal f is the scanning line H11 shown in FIG. At this time, when the signal g and the signal f are added by the adder 14, the output signal h corresponds to the scanning line E11 of the first field of the EDTV signal shown in FIG.

Further, when the signal f corresponds to the scanning line H22 of the second field of the HDTV signal shown in FIG. 1, the signal g is a signal obtained by triple the scanning line H21 shown in FIG. At this time, when the signal g and the signal f are added by the adder 14, the output signal h corresponds to the scanning line E21 of the second field of the EDTV signal in FIG.

Next, another example of the scanning line conversion circuit 5 will be described with reference to FIG. Note that FIG. 4 also shows the circuit configuration corresponding to the processing of one color.

As described with reference to FIG. 3, the rate-converted signal in the field memory 3 is stored in the line memory 10.
In order to simultaneously retrieve the information of two scanning lines before and after in the same field of the signal when converting the scanning lines, the preceding one scanning line is delayed by one line.

The output signal of the line memory 10 is the signal a,
It is branched into the signal b, and the scanning line data of the signal a is tripled. That is, as described with reference to FIG. 3, the data doubled by the bit shift and the unchanged data that is 1 time are input to the adder 16 to obtain the tripled signal L.

Similarly, the signal from the field memory 3 is also branched into the signal c and the signal d, and the scanning line data of the signal c is tripled. That is, as described with reference to FIG. 3, the data doubled by the bit shift and the unchanged data that is 1 time are input to the adder 17 to obtain the tripled output signal m. For example, when the output signal a is 8-bit data, the doubled data becomes 9 bits, and when the same 8-bit data is added by the adder 16 or 17, the output signals L and m become 10 bits.

The tripled output signal L obtained by the adder 16 is input to the selector 15, and the tripled output signal m obtained by the adder 17 is input to the remaining one of the selectors 15.

The signal b branched from the output of the line memory 10 is input to the selector 12, and the signal d branched from the previous stage of the line memory 10 is input to the remaining one of the selector 12.

Here, the signals a and b are the HDTV shown in FIG.
Assuming that the scanning line H11 of the signal first field is the signal c,
d is the scanning line H12 in the figure. At this time, the selector 15
Selects the signal m which is three times the scanning line H12 as the first field by the field identification signal k, and the selector 12 selects the signal b corresponding to the scanning line H11 as the first field by the field identification signal k. Output as g and f.

Further, the signals a and b are HDTV shown in FIG.
If the signal is the scanning line H21 of the second field, the signals c and d are the scanning line H22 in the figure. At this time, selector 1
Reference numeral 5 selects a signal L obtained by multiplying the scanning line H21 as a second field by the field identification signal k, and selector 12 selects a signal d corresponding to the scanning line H22 as a second field by the field identification signal k. Output as g and f.

The field identification signal k is generated by the timing generation circuit 9 as a timing signal for identifying an odd field and an even field, whereby the selectors 12 and 15 are supplied with an odd field signal and an even field signal. Are switching.

The signal g output by the selector 15,
The signal f output from the selector 12 is input to the adder 14, and the output thereof is bit-shifted to obtain a signal h as 1/4 times data.

From the above, when the signal g corresponds to the signal obtained by multiplying the scanning line H12 in the first field of the HDTV signal shown in FIG. 3 by three, the signal f becomes the scanning line H11 shown in FIG.
It is. At this time, when the signal g and the signal f are added by the adder 14, the output signal h corresponds to the scanning line E11 of the first field of the EDTV signal shown in FIG.

When the signal f corresponds to the scanning line H22 of the second field of the HDTV signal shown in FIG. 1, the signal g corresponds to a signal obtained by multiplying the scanning line H21 shown in FIG. 1 by three. At this time, when the signal g and the signal f are added by the adder 14,
The output signal h corresponds to the scanning line E21 of the second field of the EDTV signal in FIG.

Still another example of the scanning line conversion circuit will be described with reference to FIG. The example shown in FIG. 5 also shows a circuit configuration corresponding to one-color processing.

In the above-described FIGS. 3 and 4, the coefficients by which the upper and lower two scanning lines of the first field and the second field are multiplied are fixed for each path, but in the scanning line conversion circuit shown in FIG. The upper and lower two scanning line paths of the second field are made common, and the coefficient is switched for each field.

As described with reference to FIG. 3, the rate-converted signal in the field memory 3 is stored in the line memory 10.
In order to simultaneously retrieve the information of two scanning lines before and after in the same field of the signal when converting the scanning lines, the preceding one scanning line is delayed by one line.

The output signal p of the line memory 10 is input to the coefficient unit 18, and the signal q from the field memory 3 is input to the coefficient unit 19.

Here, when the HDTV first field is input to the field memory 3, if the output signal p of the line memory 10 is the scanning line H11 of the HDTV signal first field shown in FIG. Signal q
Is the scanning line H12 shown in FIG. When the HDTV second field is input to the field memory 3, the signal p
Is the scanning line H21 of the second field of the HDTV signal in FIG. 1, the signal q is the scanning line H22 shown in FIG.

The scanning line H11 is applied to the coefficient unit 18 and the coefficient unit 19
When the scanning line H12 is input to the scanning line H12, the coefficient units 18 and 19 multiply the scanning line information by coefficients of 1 and 3 respectively as the first field by the field identification signal k and multiply the signals r and H12 by multiplying H11 by 3. Obtain the multiplied signal s.

When the scanning line H21 is input to the coefficient unit 18 and the scanning line H22 is input to the coefficient unit 19, the coefficient units 18 and 19 respectively output the coefficient of 3 times and 1 time as the second field by the field identification signal k. The scanning line information is multiplied to obtain a signal r obtained by multiplying H21 by 3 and a signal s obtained by multiplying H22 by 1.

The field identification signal k is generated by the timing generation circuit 9 as a timing signal for identifying an odd field and an even field, whereby the scanning line signals input to the coefficient multiplier 18 and the coefficient multiplier 19 are odd. Discriminate between field signal and even field signal,
The coefficients of the coefficient multipliers 18 and 19 by which the scanning line information is multiplied are switched.

The signals r and s output from the coefficient multipliers 18 and 19 are input to the adder 14, and the output thereof is bit-shifted to obtain a signal h as 1/4 times data.

From the above, when the signal r corresponds to a signal obtained by multiplying the scanning line H11 of the first field of the HDTV signal shown in FIG. 1 by a factor of 1, the signal s is the scanning line H12 shown in FIG.
Corresponds to the signal multiplied by 3. At this time, when the signal r and the signal s are added by the adder 14, the output signal h corresponds to the scanning line E11 of the first field of the EDTV signal shown in FIG.

When the signal r corresponds to a signal obtained by multiplying the scanning line H21 of the second field of the HDTV signal shown in FIG. 1 by 3, the signal s corresponds to a signal obtained by multiplying the scanning line H22 shown in FIG. 1 by 1. At this time, the signal r and the signal s are added by the adder 14.
, The output signal h corresponds to the scanning line E21 of the second field of the EDTV signal in FIG.

Referring again to FIG. 2, scanning line converted G, B and R output signals h (that is, outputs 113, 114,
And 115) are respectively D / A converted by D / A converters 6a, 6b and 6c and output as G, B and R signals of the EDTV.

As is apparent from the above description, the scanning line conversion circuit simultaneously takes out the information of two scanning lines before and after in the line memory and switches the signal path for each field, or the coefficient unit for switching the coefficient for each field. It can be seen that it is composed of an arithmetic circuit. Then, in the first field of the HDTV video signal, information of 1 times and 3 times of the adjacent upper and lower scanning line information is added, and scanning line information weighted by 1/4 is obtained as one scanning line information of the EDTV. In addition, in the next second field, the scanning line information obtained by adding the information of 3 times and 1 time to the adjacent upper and lower scanning line information, respectively, and conversely weighting it by 1/4 It can be obtained as one scan line information of EDTV. Hereinafter, the same processing as the first field and the second field is sequentially performed on each of the odd field and the even field.

Thus, according to this embodiment, the HDTV
Video signal (1125 scanning lines, scanning method 2: 1 interlace, field frequency 60 Hz, aspect ratio 16:
9) can be directly converted into EDTV video signals (525 scanning lines, scanning method non-interlaced, field frequency 60 Hz, aspect ratio 16: 9), so that HDTV signals can be converted to EDTV displays with an aspect ratio of 16: 9. Can be displayed.

In the above embodiment, the circuit processed by the three primary color signals of GBR was presented, but in order to reduce the circuit scale, it is processed by the luminance / color difference signal and converted into GBR at the final stage. Good.

In the examples shown in FIGS. 3 and 4, the bit shift and the adder are used in the calculation, but a multiplier may be used instead.

Further, in the configuration shown in FIG. 5, since the coefficient unit can be realized by using a general-purpose LSI, it is economical in terms of cost, and the LSI for image processing includes a line memory and an adder. There are things that can process up to the operation, so
Further, the circuit scale can be reduced.

[0084]

As described above, according to the present invention, it is possible to display an HDTV signal on an EDTV specification display with a relatively simple structure while suppressing deterioration of image quality due to conversion to a minimum. In addition to the display, if you use a device that uses this method, you will get an EDTV
It is possible to use HDTV signals as the signal source of
It also has the effect of significantly expanding the selection of program software for EDTV broadcasting.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a vertical phase relationship between a scanning line of an EDTV video signal after conversion and a scanning line of an HDTV signal before conversion according to the present invention.

FIG. 2 is a functional block diagram showing an embodiment of a video signal conversion device according to the present invention.

FIG. 3 is a functional block diagram for explaining an example of the scanning line conversion circuit shown in FIG.

FIG. 4 is a functional block diagram for explaining another example of the scanning line conversion circuit shown in FIG.

5 is a functional block diagram for explaining yet another example of the scanning line conversion circuit shown in FIG.

FIG. 6 is a block diagram showing an example of a conventional signal processing circuit.

FIG. 7 is a block diagram showing another example of a conventional signal processing circuit.

8 is a block diagram for explaining the signal processing circuit shown in FIG. 7. FIG.

FIG. 9 is an explanatory diagram showing a phase relationship in a vertical direction of scanning lines of luminance signals.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 matrix circuit 2a, 2b, 2c A / D conversion circuit 3 field memory 4 rate conversion circuit 5 scanning line conversion circuit 6a, 6b, 6c D / A converter 7 sync separation circuit 8 PLL circuit 9 timing generation circuit 10 line memory 11 , 12, 15 Selector 13, 14, 16, 17 Adder 18, 19 Coefficient unit

Claims (10)

(57) [Claims] 1. A conversion device for converting an HDTV digital video signal, one frame of which comprises a first field and a second field, into an EDTV digital video signal, wherein the HDTV digital video signal is a clock of the EDTV digital video signal. A rate conversion means for speed-converting a rate to obtain a converted signal, a delay means for delaying the converted signal by one scanning line to obtain a delayed signal, and a first predetermined predetermined converted signal in the first field. A first generating means for multiplying the delayed signal by the first coefficient in the second field to obtain a second multiplied signal, and the first field. Then, based on the first multiplied signal and the delayed signal, the EDT
V digital video signal is generated, and the E signal is generated in the second field according to the second multiplication signal and the conversion signal.
A video signal conversion device comprising: a second generation means for generating a DTV digital video signal. 2. The video signal conversion circuit according to claim 1, further comprising timing generation means for generating a field identification signal for identifying the first and second fields, and the first signal generation circuit. The video signal conversion device is characterized in that the generating means is configured to identify the first and second fields according to the field identification signal. 3. The video signal conversion circuit according to claim 2, wherein the first means uses the conversion signal as a first selection signal when the field identification signal represents the first field. First selector means for selecting and selecting the delayed signal as the first selection signal when the field identification signal represents the second field; and the field identification signal represents the first field. Second selector means for selecting the delayed signal as the second selection signal, and for selecting the conversion signal as the second selection signal when the field identification signal represents the second field. And a multiplication means for multiplying the first selection signal by the first constant to generate the first and second multiplication signals. 4. The video signal conversion circuit according to claim 3, wherein the second generation unit adds the second selection signal to each of the first and second multiplication signals and adds the result. And the addition result is multiplied by a second constant to obtain the above E
A video signal conversion circuit characterized in that a DTV digital video signal is generated. 5. The video signal conversion circuit according to claim 2, wherein the first means multiplies the converted signal and the delayed signal by the first constant, respectively, and the first and second signals are obtained. Multiplication means for obtaining a multiplication signal; and selecting the first multiplication signal when the field identification signal represents the first field, and selecting the first identification signal when the field identification signal represents the first field. First selector means for selecting a multiplication signal of 2, and the delayed signal is selected when the field identification signal represents the first field, and the field identification signal represents the second field. And a second selector means for selecting the converted signal. 6. The video signal conversion circuit according to claim 1, 2, or 5, wherein the second generation means adds the delay signal and the conversion signal to the first and second multiplication signals, respectively. Is added to obtain an addition result, and the addition result is multiplied by a second constant to generate the EDTV digital video signal. 7. The video signal conversion circuit according to claim 3 or 5, wherein the first constant is 3. 8. The video signal conversion circuit according to claim 4 or 6, wherein the second constant is 1/4. 9. The video signal conversion circuit according to claim 2, wherein the timing generating means has a write clock having a timing synchronized with the HDTV digital video signal and a read clock having a timing synchronized with the EDTV digital video signal. A clock is generated, and the rate conversion means is responsive to the write clock to the HDTV.
The digital video signal is written as the writing signal,
The write signal is sent to the E according to the read clock.
A video signal conversion circuit, which is a field memory for reading out as a DTV digital video signal. 10. The video signal conversion circuit according to claim 9, wherein the conversion means receives an HDTV video signal and converts the HDTV video signal into the HDTV digital video signal, and a horizontal synchronizing signal and a vertical sync signal from the HDTV video signal. A sync separation circuit for separating a sync signal to generate a field cycle signal representing a field cycle, and a clock signal of an HDTV video signal and an EDTV based on the horizontal sync signal.
A PLL circuit for obtaining a clock signal of a video signal, wherein the timing generation means is based on the horizontal synchronizing signal, the vertical synchronizing signal, the field period signal, and the both clock signals, the write clock, the read clock,
And a video signal conversion circuit, wherein the field identification signal is generated.