JPH0937175A - Picture display device and picture display method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously display the two kinds of pictures on the same screen and to select and view only one of the pictures by converting the two kinds of the picture signals of an interlace form to a non-interlace form and outputting them to a monitor with a shutter. SOLUTION: Class sorting adaptive processing circuits 14A and 14B take out only one of the fields of the picture signals S3 and S4 of the interlace form, interpolate picture elements in a vertical direction, convert them to the picture signals S5 and S6 of the non-interlace form and transmit them. Frame memories 16A and 16B for tentatively storing the signals S5 and S6 read the signals S5 and S6 to a selection circuit 17 based on synchronizing signals S8 from a control circuit 15, a required processing is executed in a monitor driving circuit 18 and they are outputted and displayed on a monitor 19. Also, the circuit 15 transmits LCD driving signals 510 and S11 synchronized with the signals S8 respectively to LCD driving circuits 20A and 20B. The circuits 20A and 20B open and close the respective shutters of liquid crystal spectacles 21A and 21B by the LCD driving signals S12 and S13 synchronized with the signals S10 and S11.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology (FIG. 6) Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (1) Overall Configuration (FIGS. 1 and 2) (2) Class Classification Adaptive Processing Circuit (FIGS. 3 to 5) (3) Other Embodiments Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device and an image display method, and is suitable for application to, for example, a television receiver.

[0003]

2. Description of the Related Art Conventionally, in television receivers,
It was common to see one type of image on one receiver. However, in recent years, there has been a demand from users who want to view a plurality of types of images on one receiver at the same time, and a television receiver that enables this has been devised.

For example, a television receiver 1 which uses a screen display with a parent-child screen as shown in FIG. 6 (A) displays a small child screen 3 by overlapping a part of the parent screen 2. The television receiver 1 can display both images at the same time by displaying the image mainly viewed by the user on the main screen 2 and displaying the image viewed secondarily on the child screen 3. When a scene that focuses on the image displayed on the child screen 3 is displayed, the image viewed on the child screen 3 is displayed on the parent screen 2 by replacing the image on the parent screen 2 with the image on the child screen 3. You can see.

Further, as shown in FIG. 6B, there is also a method of displaying the display screen of the television receiver 1 by equally dividing it into two. According to this method, the parent screen 2 and the child screen 3 have the same size, so that both the parent screen 2 and the child screen 3 can be viewed with good image quality and screen size. Further, as shown in FIG. 6C, the screen is divided into two equal parts,
It is also devised that the child screen 3 is further divided into a plurality of screens, and different types of images are displayed in the respective divided screens.

[0006]

By the way, in such a television receiver 1, in the case of a method of superimposing the small screen 3 on the main screen 2, the small screen 3 on the main screen 2 is superposed. There is a problem that the hidden part is hidden and you cannot see the part. Further, in the case of the method of dividing the screen into two equal parts, the parent screen 2 and the child screen 3 are sufficiently large, so that the legibility and good resolution can be obtained. There is a problem that one of the images becomes obtrusive to see the other image because of displaying the image. In the case of the method of further dividing one of the sub screens 3 which is further divided into two, there is a problem that the display image becomes difficult to see because the screen of the sub screen 3 becomes too small.

The present invention has been made in consideration of the above points, and an image display device and an image display capable of simultaneously displaying two types of images on the same screen and selecting only one of the images. It is intended to propose a method.

[0008]

In order to solve such a problem, according to the present invention, image conversion means for converting two types of input interlaced image signals into image signals in non-interlaced format, respectively. One of the two types of images displayed alternately on the same monitor and the time-division output means for alternately outputting the two types of image signals in the non-interlaced format on the same monitor at a predetermined cycle. Two types of shutters that are opened when is displayed and that transmit image light are provided.

An odd field or an even field is taken out from each of two types of image signals in the interlaced format, and vertical classification is performed by using a class classification adaptive process for generating and interpolating pixels not included in the image by a prediction coefficient prepared in advance. By interpolating the pixels in the direction, two types of image signals in the non-interlaced format are generated, and the two types of image signals in the non-interlaced format are alternately displayed on the same screen at a predetermined cycle. The two types of shutters are opened and closed in synchronization with the display cycle of one of the displayed images.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Overall Configuration The image display device 10 shown in FIG. 1 has an image signal S1 in an interlaced format via an antenna and two types of tuners.
And S2 are respectively received, and the odd field extracted from the image signal S1 and the even field extracted from the image signal S2 are subjected to class classification processing and non-interlaced conversion is performed by pixel interpolation in the vertical direction. After alternately displaying the images on the screen in a time-sharing manner, by viewing the screen using a liquid crystal shutter that opens and closes in synchronization with the display cycle of one of the images, only one of the images can be selected. It is something that you can see.

The image display device 10 displays the image signals S1 and S2, which are interlaced television broadcast signals,
Antenna 11 and two different tuners 12A and 12B
And analog / digital converter 13A via
And 13B, and converted into image signals S3 and S4 which are digital signals represented by 8 bits per pixel. Analog / digital converters 13A and 13B
Sends the image signals S3 and S4 to the class classification adaptive processing circuits 14A and 14B, respectively, and the control circuit 1
5

As shown in FIG. 2A, the class classification adaptive processing circuit 14A takes out an odd field of the image signal S3. In addition, the class classification adaptive processing circuit 14B uses the image signal S
Take out an even field of 4. The class classification adaptive processing circuits 14A and 14B take out only one of the fields and interpolate pixels in the vertical direction in this way, so that the image signals S3 and S4 in the interlaced format are obtained.
Is converted into non-interlaced image signals S5 and S6 and transmitted.

That is, as shown in FIG. 2 (B), one frame has two odd fields A _o and even fields A _e .
Non-interlace in which one frame consists of one field by extracting only odd field A _O from the interlaced image signal S3 consisting of field and interpolating pixels for one field in the vertical direction The image signal S5 (A _O ') of the format is converted. On the other hand, Yotsute that one frame to interpolate odd field B _O and the even field B pixels of one field from the image signal S4 in interlaced format consisting of 2 fields even fields B _e only in the vertical direction is taken out of the _e An odd field is generated and converted into a non-interlaced image signal S6 (B _e ') in which one frame has one field.

Class classification adaptive processing circuits 14A and 14B
The frame memories 16A and 16B for temporarily storing the image signals S5 and S6 sent from the control circuit 1 are
The image signals S5 and S6 which are synchronized by controlling the read timing based on the sync signal S8 sent from the signal No. 5 are read to the selection circuit 17. Selection circuit 1
Reference numeral 7 sends the image signals S5 and S6, which are alternately read by switching at a predetermined frame cycle by the synchronization signal S8, to the monitor drive circuit 18 as one non-interlaced image signal S7. Here, the synchronizing signal S8 synchronizes the image signals S5 and S6, and at the same time, the monitor driving circuit 18
Is output as a signal for setting the frame period of the image signal S7 transmitted to the.

The monitor driving circuit 18 sends to the monitor 19 an image signal S9 obtained by subjecting the image signal S7 to digital / analog conversion, amplification and detection. The monitor 19 displays an image based on the image signal S9 on the screen. As a result, the image signals S5 and S6 are displayed on the monitor 19.
Images are alternately displayed for each frame. That is, the image display device 10 is configured to alternately switch the received two types of images for each field unit and display them on the monitor 19.

Further, the control circuit 15 controls the LCD drive signal S1 which is switched in units of fields synchronized with the synchronization signal S8.
0 and S11 are LCD drive circuits 20A and 20 respectively.
Send to B. The LCD drive circuits 20A and 20B are L synchronized with the LCD drive signals S10 and S11, respectively.
By the CD drive signals S12 and S13, the liquid crystal glasses 2
The shutters of 1A and 21B are opened and closed.

That is, the liquid crystal glasses 21A are drive-controlled by the LCD drive signal S12 so as to open the shutter in synchronization with the field cycle of the image signal S5. At the same time, the liquid crystal glasses 21B are driven and controlled by the LCD drive signal S13 so as to open the shutters in synchronization with the field cycle of the image signal S6. Accordingly, each user wearing the liquid crystal glasses 21A or 21B can selectively see the images switched while the shutter cycle of the liquid crystal glasses 21A or 21B is opened, respectively. For example, when the field frequency of the displayed image is 60 [Hz], the switching operation of the image displayed on the monitor 19 and the shutter operation of the liquid crystal of the liquid crystal glasses 21A and 21B are switched at a frame cycle of 60 times per second. . As a result, the image can be viewed without being aware of the switching operation of the image and the liquid crystal due to human visual characteristics.

(2) Class Classification Adaptive Processing Circuit Next, the internal configuration of the class classification adaptive processing circuits 14A and 14B will be described. Class classification adaptive processing circuits 14A and 14
Since B has the same internal configuration, only the configuration of the class classification adaptive processing circuit 14A is shown here.

The class classification adaptive processing circuit 14A shown in FIG. 3 inputs the image signal S3 supplied from the analog / digital converter 13A to the block circuit 30 and the delay circuit 31. The block conversion circuit 30 extracts an odd field from the image signal S3 and then outputs it as a block signal S20 with 8 pixels × 8 lines as one unit in the ADR.
It is sent to the C (Adaptive Dynamic Range Coding) circuit 32.

The ADRC circuit 32 outputs the block signal S2.
0 is subjected to class classification processing by pattern classification, and the index signal S21 as the classification result is supplied to each coefficient memory M1 to Mn in the interpolation processing unit 33 as a signal representing a class into which the image signal S3 is classified. Originally, a plurality of interpolation processing units 33 are provided, but here, for the sake of convenience, the description will be given with one interpolation processing unit 33. Each coefficient memory M1
~ Mn is a ROM (Re
data signals K1 to Kn composed of coefficients for each class are sent to each of the multipliers MX1 to MXn by using the supplied index signal S21 as an address signal.

Here, the ADRC circuit 32 has the structure shown in FIG. 4, and the block signal S20 sent from the block circuit 30 (FIG. 3) is converted into a maximum value calculation circuit 39, a minimum value calculation circuit 40 and a delay circuit. 41 respectively.
The maximum value calculation circuit 39 finds the maximum pixel value MAX in the block indicated by the block signal S20, and the minimum value calculation circuit 40 finds the minimum pixel value MIN in the block. The maximum pixel value MAX thus obtained is the difference circuit 42.
And the minimum pixel value MIN is sent to the difference circuit 43 and the class selection circuit 44.

The difference circuit 42 sends to the class selection circuit 44 the dynamic range DR in the block which is the difference value between the maximum pixel value MAX and the minimum pixel value MIN. Further, the difference circuit 43 sends to the adaptive quantization circuit 45 the difference value obtained from the difference operation between each pixel value given via the delay circuit 41 and the minimum pixel value MIN. The adaptive quantizing circuit 45 converts each pixel represented by 8 bits by requantizing each pixel value based on the input difference value into a smaller n-bit quantization code X _i. And sends it to the class selection circuit 44. Class selection circuit 4
4 is the supplied dynamic range DR and the minimum pixel value M
Based on IN and the quantization code X _i , the index signal S21 indicating the class into which the block signal S20 is classified according to the state of each pixel value is transmitted.

Further, the class classification adaptive processing circuit 1 shown in FIG.
In 4A, the delay circuit 31 delays the input digital signal S3 by a predetermined time, and then the interpolation processing unit 33.
To the prediction tap selection circuit 35 and the delay circuit 36. The predictive tap selection circuit 35 forms a cluster tap data signal S23 from the pixel of the point of interest of the image indicated by the digital signal S3 and its peripheral pixels to form each of the multipliers MX1 to MX1.
Send to MXn. The multipliers MX1 to MXn are supplied with data signals K1 to Kn and a cluster data signal S, respectively.
23 are respectively processed to generate pixels to be interpolated,
It is sent to the adders ADD1 to ADDn.

The adders ADD1 to ADDn of each arithmetic unit are
The obtained pixels are combined and sent to the synthesizing circuit 38 as interpolation pixel signals S241 to S24n. The synthesizing circuit 38 synthesizes the image signal S3 delayed by the delay circuit 36 by a predetermined time and the interpolated pixel signals S241 to S24n for interpolating the image signal S3, and the image signal S3.
The image signal S5 composed of pixels having a double rate in the vertical direction is generated and output.

Further, although it has been described that each of the coefficient memories M1 to Mn is a ROM in which the coefficient for each class is stored in advance, the ROM can be created by using the following method. That is, the prediction coefficient generation circuit 50 shown in FIG. 5 inputs the input non-interlaced image signal S40 to the line thinning circuit 51 and the coefficient selection circuit 53.

The line thinning circuit 51 is provided with an image signal S40.
Of the image signal S41 converted into the interlaced format by thinning out the odd field or the even field of
It is sent to the RC circuit 52 and the line interpolation circuit 54. AD
The RC circuit 52 generates a class code signal S42 indicating the class into which the image signal S41 is classified, and the coefficient selection circuit 5
Send to 3. At the same time, the line interpolation circuit 54 interpolates the fields thinned by the line thinning circuit 51 and sends it to the coefficient selection circuit 53 as an interpolated image signal S43.

The coefficient selection circuit 53 is optimized for each class based on the non-interlaced image signal S40, the class code signal S42 and the interpolated image signal S43 generated by simply interpolating the thinned lines. A prediction coefficient for calculating such a pixel value is obtained by a method such as the least square method, and is output as a prediction coefficient S44.

As described above, the prediction coefficient generating circuit 40 receives the image signal S40 input in the non-interlaced format, and the class code signal S42 obtained by converting the image signal S40 into the interlaced format and then classifying the image. , An image signal in the interlaced format is converted into an image signal in the non-interlaced format by comparing with the interpolated image signal S43 obtained by performing interpolation processing after converting the image signal S40 into the interlaced format. It is possible to obtain the prediction coefficient S44 for

In the above structure, the image signals S5 and S5
6 is switched alternately for each field unit and alternately output, and the image signal S7 obtained thereby is output to the monitor 19 to display an image based on the image signal S7 in a time division manner. Further, by outputting the LCD drive signals S10 and S11 at the same cycle as the timing of switching the transmission of the image signals S5 and S6, the shutter operation in which the liquid crystal glasses 21A and 21B are alternately opened is performed.

As a result, the user wearing the liquid crystal glasses 21A can see the image when the image by the image signal S5 is displayed on the monitor 19 and the shutter by the liquid crystal is opened, but the image by the image signal S6 is displayed. When displayed on the monitor 19, the liquid crystal shutter is in a closed state and the image cannot be viewed. Also LCD glasses 2
When the image based on the image signal S6 is displayed on the monitor 19, the user applying 1B can see the image because the shutter by the liquid crystal is open, but the image based on the image signal S5 is displayed on the monitor 19. In this case, the liquid crystal shutter is closed and the image cannot be viewed.
Thus, the user wearing the liquid crystal glasses 21A and 21B can selectively see only one image.

Further, the image signals S1 and S2 in the interlaced format for forming one frame with two fields are taken out by the class classification adaptive processing circuits 14A and 14B, respectively, so that only odd fields or even fields are extracted,
By generating interpolation pixels using the class classification adaptive processing, the image signals are converted into non-interlaced image signals S5 and S6 that form one frame with one field. As a result, the interlaced image signals S1 and S
When converting 2 into an image signal of a non-interlaced format, it is possible to convert the image signals S5 and S6 of good images without degrading the image quality, and to display the image on the monitor 19 without changing the frequency. Can be displayed.

According to the above configuration, the image signals S1 and S2 in the interlaced format are converted into the image signals S5 and S6 in the non-interlaced format by the class classification adaptive processing, and the images by the image signals S5 and S6 are converted. Is alternately displayed on the monitor 19, and the image is viewed by using the liquid crystal glasses 21A and 21B that alternately perform the shutter operation in the same cycle as any one of the display cycles of the image. Accordingly, it is possible to realize the image display device 10 and the image display method capable of simultaneously displaying two types of images on one monitor and selectively viewing one of the displayed images. .

(3) Other Embodiments In the above embodiment, the input image signal S1 is input.
Although the case where the television broadcasting signal is used as S2 and S2 has been described, the present invention is not limited to this, and an image signal or the like obtained by reproducing the recording medium may be input from an external terminal (not shown) and used. As a result, the present invention can be applied to any image signal.

In the above embodiment, the image signal S
The case where the non-interlaced image signals S5 and S6 are generated by extracting the odd fields of 3 and the even fields of the image signal S4 and interpolating them respectively has been described, but the present invention is not limited to this. , The even field of the image signal S3 and the odd field of the image signal S4 may be respectively taken out and interpolated. Also in this case, the same effect as that of the embodiment can be obtained.

Further, in the above-described embodiment, the ADR is used when performing the class classification processing by the pattern classification by the image conversion means composed of the class classification adaptive processing circuits 14A and 14B.
The case where the classification result of the index signal S21 is obtained by using the ADRC encoding by the C circuit 32 has been described, but the present invention is not limited to this, and for example, DCT (DiscreatCo).
sine Transform) encoding, DPCM (differential encoding),
The class classification processing by pattern classification may be performed using a compression method such as vector quantization, subband coding, or wavelet transform.

Further, in the above-mentioned embodiment, the case where the ROM is used as the coefficient memories M1 to Mn for storing the prediction coefficient is described, but the present invention is not limited to this, and the RAM (Random Access Memory) is used instead of the ROM. And SRAM (St
atic RAM) or the like may be used.

[0038]

As described above, according to the present invention, the interlaced format is used in which one frame is formed by two fields.
By extracting an even field or an odd field from each type of image signal and interpolating pixels using the class classification adaptive processing, two types of image signals in non-interlaced format that form one frame with one field are generated. , The image signals are alternately displayed on the same screen in a predetermined cycle, and the two types of shutters are opened and closed in synchronization with one of the display cycles of one of the display images. It is possible to realize an image display device and an image display method capable of simultaneously displaying two types of images and selecting and viewing one of the images.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image display device according to an embodiment of the present invention.

2A and 2B are a schematic diagram and a timing chart provided for explaining a method of deinterlacing an input image signal and a timing of alternately outputting the image signal.

FIG. 3 is a block diagram showing an internal configuration of a class classification adaptive processing circuit.

FIG. 4 is a block diagram showing an internal configuration of an ADRC circuit.

FIG. 5 is a block diagram showing a prediction coefficient creating circuit.

FIG. 6 is a schematic diagram showing a conventional method of displaying a plurality of images.

[Explanation of symbols]

1 ... Television receiver, 2 ... Parent screen, 3 ... Child screen, 10 ... Image display device, 11 ... Antenna, 12
A, 12B ... China, 13A, 13B ... Analog / digital converter, 14A, 14B ... Class classification adaptive processing circuit, 15 ... Control circuit, 16A, 16B ... Frame memory, 17 ... Selection circuit, 18 ... Monitor drive circuit, 19 ... Monitor, 20A, 20B ... LCD drive circuit, 21A, 21B ... Liquid crystal glasses, 30 ... Blocking circuit, 31, 36, 41 ... Delay circuit, 32, 52
... ADRC circuit, 33 ... interpolation processing unit, 35 ... prediction tap selection circuit, 38 ... combination circuit, 39 ... maximum value calculation circuit, 40 ... minimum value calculation circuit, 42, 43 ... difference circuit, 44 ... Class selection circuit, 45 ... Adaptive quantization circuit, 50 ... Prediction coefficient creation circuit, 51 ... Line thinning circuit, 53 ... Coefficient selection circuit, 54 ... Line interpolation circuit, M1-Mn ... Coefficients Memory, MX1 to MXn ... Multiplier, ADD1 to ADDn ... Adder.

Claims (5)

[Claims] 1. An image signal in the first and second interlaced formats is respectively captured, an odd field is extracted from the first image signal in the interlaced format, and interpolation processing is performed in a vertical direction of the image. A non-interlaced format is obtained by generating a third image signal of non-interlaced format and extracting an even field from the second image signal of interlaced format and performing interpolation processing in the vertical direction of the image. Image conversion means for generating a fourth image signal, time division output means for alternately switching the third and fourth image signals to a display monitor at a predetermined cycle, and outputting the image by the third image signal. Is opened at the same timing as when is displayed, and an image is displayed by the first shutter that transmits image light and the fourth image signal. In an open state at the same timing to the image display device characterized by comprising a second shutter which transmits the image light. 2. The image conversion means classifies the first and second image signals, and generates interpolated pixel values for interpolating the first and second image signals according to the classification results. The image display device according to claim 1, wherein the third and fourth image signals having a higher resolution than the input first and second image signals are thereby generated. 3. The time division output means includes first and second frame memories for storing the third and fourth image signals, and a selection circuit for selecting and switching the input image signals to output. The third and fourth image signals stored in the first and second frame memories are switched by the selection circuit at a predetermined cycle and alternately output. The image display device described. 4. The image display device according to claim 1, wherein the first and second shutters are liquid crystal glasses. 5. An odd-numbered or even-numbered field extracted from an input interlaced first image signal and an even-numbered or odd-numbered field extracted from an interlaced second image signal belong to each pixel. In a non-italaced form, a class decision step for deciding a class and an interpolation pixel value which is not included in the odd or even field and the even or odd field are generated and interpolated according to the decided class. A conversion step for generating the third and fourth image signals, and a time-division output step for alternately outputting the images according to the third and fourth image signals to the display monitor at a predetermined cycle, and the third image The first shutter is opened at the same timing as when the image based on the signal is displayed, and the image based on the fourth image signal is displayed. The image display method characterized by comprising the Shiyatsutasutetsupu to the same timing as the timing indicated second shutters opened.